armv4cpuid.S 2.9 KB

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  1. #include "arm_arch.h"
  2. .text
  3. .code 32
  4. .align 5
  5. .global _armv7_neon_probe
  6. .type _armv7_neon_probe,%function
  7. _armv7_neon_probe:
  8. .word 0xf26ee1fe @ vorr q15,q15,q15
  9. .word 0xe12fff1e @ bx lr
  10. .size _armv7_neon_probe,.-_armv7_neon_probe
  11. .global _armv7_tick
  12. .type _armv7_tick,%function
  13. _armv7_tick:
  14. mrc p15,0,r0,c9,c13,0
  15. .word 0xe12fff1e @ bx lr
  16. .size _armv7_tick,.-_armv7_tick
  17. .global OPENSSL_atomic_add
  18. .type OPENSSL_atomic_add,%function
  19. OPENSSL_atomic_add:
  20. #if __ARM_ARCH__>=6
  21. .Ladd: ldrex r2,[r0]
  22. add r3,r2,r1
  23. strex r2,r3,[r0]
  24. cmp r2,#0
  25. bne .Ladd
  26. mov r0,r3
  27. .word 0xe12fff1e @ bx lr
  28. #else
  29. stmdb sp!,{r4-r6,lr}
  30. ldr r2,.Lspinlock
  31. adr r3,.Lspinlock
  32. mov r4,r0
  33. mov r5,r1
  34. add r6,r3,r2 @ &spinlock
  35. b .+8
  36. .Lspin: bl sched_yield
  37. mov r0,#-1
  38. swp r0,r0,[r6]
  39. cmp r0,#0
  40. bne .Lspin
  41. ldr r2,[r4]
  42. add r2,r5
  43. str r2,[r4]
  44. str r0,[r6] @ release spinlock
  45. ldmia sp!,{r4-r6,lr}
  46. tst lr,#1
  47. moveq pc,lr
  48. .word 0xe12fff1e @ bx lr
  49. #endif
  50. .size OPENSSL_atomic_add,.-OPENSSL_atomic_add
  51. .global OPENSSL_cleanse
  52. .type OPENSSL_cleanse,%function
  53. OPENSSL_cleanse:
  54. eor ip,ip,ip
  55. cmp r1,#7
  56. subhs r1,#4
  57. bhs .Lot
  58. cmp r1,#0
  59. beq .Lcleanse_done
  60. .Little:
  61. strb ip,[r0],#1
  62. subs r1,#1
  63. bhi .Little
  64. b .Lcleanse_done
  65. .Lot: tst r0,#3
  66. beq .Laligned
  67. strb ip,[r0],#1
  68. sub r1,#1
  69. b .Lot
  70. .Laligned:
  71. str ip,[r0],#4
  72. subs r1,#4
  73. bhs .Laligned
  74. adds r1,#4
  75. bne .Little
  76. .Lcleanse_done:
  77. tst lr,#1
  78. moveq pc,lr
  79. .word 0xe12fff1e @ bx lr
  80. .size OPENSSL_cleanse,.-OPENSSL_cleanse
  81. .global OPENSSL_wipe_cpu
  82. .type OPENSSL_wipe_cpu,%function
  83. OPENSSL_wipe_cpu:
  84. ldr r0,.LOPENSSL_armcap
  85. adr r1,.LOPENSSL_armcap
  86. ldr r0,[r1,r0]
  87. eor r2,r2,r2
  88. eor r3,r3,r3
  89. eor ip,ip,ip
  90. tst r0,#1
  91. beq .Lwipe_done
  92. .word 0xf3000150 @ veor q0, q0, q0
  93. .word 0xf3022152 @ veor q1, q1, q1
  94. .word 0xf3044154 @ veor q2, q2, q2
  95. .word 0xf3066156 @ veor q3, q3, q3
  96. .word 0xf34001f0 @ veor q8, q8, q8
  97. .word 0xf34221f2 @ veor q9, q9, q9
  98. .word 0xf34441f4 @ veor q10, q10, q10
  99. .word 0xf34661f6 @ veor q11, q11, q11
  100. .word 0xf34881f8 @ veor q12, q12, q12
  101. .word 0xf34aa1fa @ veor q13, q13, q13
  102. .word 0xf34cc1fc @ veor q14, q14, q14
  103. .word 0xf34ee1fe @ veor q15, q15, q15
  104. .Lwipe_done:
  105. mov r0,sp
  106. tst lr,#1
  107. moveq pc,lr
  108. .word 0xe12fff1e @ bx lr
  109. .size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
  110. .global OPENSSL_instrument_bus
  111. .type OPENSSL_instrument_bus,%function
  112. OPENSSL_instrument_bus:
  113. eor r0,r0,r0
  114. tst lr,#1
  115. moveq pc,lr
  116. .word 0xe12fff1e @ bx lr
  117. .size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
  118. .global OPENSSL_instrument_bus2
  119. .type OPENSSL_instrument_bus2,%function
  120. OPENSSL_instrument_bus2:
  121. eor r0,r0,r0
  122. tst lr,#1
  123. moveq pc,lr
  124. .word 0xe12fff1e @ bx lr
  125. .size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
  126. .align 5
  127. .LOPENSSL_armcap:
  128. .word OPENSSL_armcap_P-.LOPENSSL_armcap
  129. #if __ARM_ARCH__>=6
  130. .align 5
  131. #else
  132. .Lspinlock:
  133. .word atomic_add_spinlock-.Lspinlock
  134. .align 5
  135. .data
  136. .align 2
  137. atomic_add_spinlock:
  138. .word 0
  139. #endif
  140. .comm OPENSSL_armcap_P,4,4
  141. .hidden OPENSSL_armcap_P