OPENSSL_ia32cap.pod 5.8 KB

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  1. =pod
  2. =head1 NAME
  3. OPENSSL_ia32cap - the x86[_64] processor capabilities vector
  4. =head1 SYNOPSIS
  5. env OPENSSL_ia32cap=... <application>
  6. =head1 DESCRIPTION
  7. OpenSSL supports a range of x86[_64] instruction set extensions. These
  8. extensions are denoted by individual bits in capability vector returned
  9. by processor in EDX:ECX register pair after executing CPUID instruction
  10. with EAX=1 input value (see Intel Application Note #241618). This vector
  11. is copied to memory upon toolkit initialization and used to choose
  12. between different code paths to provide optimal performance across wide
  13. range of processors. For the moment of this writing following bits are
  14. significant:
  15. =over 4
  16. =item bit #4 denoting presence of Time-Stamp Counter.
  17. =item bit #19 denoting availability of CLFLUSH instruction;
  18. =item bit #20, reserved by Intel, is used to choose among RC4 code paths;
  19. =item bit #23 denoting MMX support;
  20. =item bit #24, FXSR bit, denoting availability of XMM registers;
  21. =item bit #25 denoting SSE support;
  22. =item bit #26 denoting SSE2 support;
  23. =item bit #28 denoting Hyperthreading, which is used to distinguish
  24. cores with shared cache;
  25. =item bit #30, reserved by Intel, denotes specifically Intel CPUs;
  26. =item bit #33 denoting availability of PCLMULQDQ instruction;
  27. =item bit #41 denoting SSSE3, Supplemental SSE3, support;
  28. =item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
  29. =item bit #54 denoting availability of MOVBE instruction;
  30. =item bit #57 denoting AES-NI instruction set extension;
  31. =item bit #58, XSAVE bit, lack of which in combination with MOVBE is used
  32. to identify Atom Silvermont core;
  33. =item bit #59, OSXSAVE bit, denoting availability of YMM registers;
  34. =item bit #60 denoting AVX extension;
  35. =item bit #62 denoting availability of RDRAND instruction;
  36. =back
  37. For example, in 32-bit application context clearing bit #26 at run-time
  38. disables high-performance SSE2 code present in the crypto library, while
  39. clearing bit #24 disables SSE2 code operating on 128-bit XMM register
  40. bank. You might have to do the latter if target OpenSSL application is
  41. executed on SSE2 capable CPU, but under control of OS that does not
  42. enable XMM registers. Historically address of the capability vector copy
  43. was exposed to application through OPENSSL_ia32cap_loc(), but not
  44. anymore. Now the only way to affect the capability detection is to set
  45. B<OPENSSL_ia32cap> environment variable prior target application start. To
  46. give a specific example, on Intel P4 processor
  47. C<env OPENSSL_ia32cap=0x16980010 apps/openssl>, or better yet
  48. C<env OPENSSL_ia32cap=~0x1000000 apps/openssl> would achieve the desired
  49. effect. Alternatively you can reconfigure the toolkit with no-sse2
  50. option and recompile.
  51. Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
  52. variable" terms. The truth is that it's not copied from CPUID output
  53. verbatim, but is adjusted to reflect whether or not the data cache is
  54. actually shared between logical cores. This in turn affects the decision
  55. on whether or not expensive countermeasures against cache-timing attacks
  56. are applied, most notably in AES assembler module.
  57. The capability vector is further extended with EBX value returned by
  58. CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
  59. =over 4
  60. =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
  61. =item bit #64+5 denoting availability of AVX2 instructions;
  62. =item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
  63. and RORX;
  64. =item bit #64+16 denoting availability of AVX512F extension;
  65. =item bit #64+18 denoting availability of RDSEED instruction;
  66. =item bit #64+19 denoting availability of ADCX and ADOX instructions;
  67. =item bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
  68. aka AVX512IFMA extension;
  69. =item bit #64+29 denoting availability of SHA extension;
  70. =item bit #64+30 denoting availability of AVX512BW extension;
  71. =item bit #64+31 denoting availability of AVX512VL extension;
  72. =item bit #64+41 denoting availability of VAES extension;
  73. =item bit #64+42 denoting availability of VPCLMULQDQ extension;
  74. =back
  75. To control this extended capability word use C<:> as delimiter when
  76. setting up B<OPENSSL_ia32cap> environment variable. For example assigning
  77. C<:~0x20> would disable AVX2 code paths, and C<:0> - all post-AVX
  78. extensions.
  79. It should be noted that whether or not some of the most "fancy"
  80. extension code paths are actually assembled depends on current assembler
  81. version. Base minimum of AES-NI/PCLMULQDQ, SSSE3 and SHA extension code
  82. paths are always assembled. Apart from that, minimum assembler version
  83. requirements are summarized in below table:
  84. Extension | GNU as | nasm | llvm
  85. ------------+--------+--------+--------
  86. AVX | 2.19 | 2.09 | 3.0
  87. AVX2 | 2.22 | 2.10 | 3.1
  88. ADCX/ADOX | 2.23 | 2.10 | 3.3
  89. AVX512 | 2.25 | 2.11.8 | see NOTES
  90. AVX512IFMA | 2.26 | 2.11.8 | see NOTES
  91. VAES | 2.30 | 2.13.3 |
  92. =head1 NOTES
  93. Even though AVX512 support was implemented in llvm 3.6, compilation of
  94. assembly modules apparently requires explicit -march flag. But then
  95. compiler generates processor-specific code, which in turn contradicts
  96. the mere idea of run-time switch execution facilitated by the variable
  97. in question. Till the limitation is lifted, it's possible to work around
  98. the problem by making build procedure use following script:
  99. #!/bin/sh
  100. exec clang -no-integrated-as "$@"
  101. instead of real clang. In which case it doesn't matter which clang
  102. version is used, as it is GNU assembler version that will be checked.
  103. =head1 RETURN VALUES
  104. Not available.
  105. =head1 COPYRIGHT
  106. Copyright 2004-2020 The OpenSSL Project Authors. All Rights Reserved.
  107. Licensed under the Apache License 2.0 (the "License"). You may not use
  108. this file except in compliance with the License. You can obtain a copy
  109. in the file LICENSE in the source distribution or at
  110. L<https://www.openssl.org/source/license.html>.
  111. =cut