OPENSSL_ia32cap.pod 2.8 KB

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  1. =pod
  2. =head1 NAME
  3. OPENSSL_ia32cap - the IA-32 processor capabilities vector
  4. =head1 SYNOPSIS
  5. unsigned int *OPENSSL_ia32cap_loc(void);
  6. #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
  7. =head1 DESCRIPTION
  8. Value returned by OPENSSL_ia32cap_loc() is address of a variable
  9. containing IA-32 processor capabilities bit vector as it appears in
  10. EDX:ECX register pair after executing CPUID instruction with EAX=1
  11. input value (see Intel Application Note #241618). Naturally it's
  12. meaningful on x86 and x86_64 platforms only. The variable is normally
  13. set up automatically upon toolkit initialization, but can be
  14. manipulated afterwards to modify crypto library behaviour. For the
  15. moment of this writing following bits are significant:
  16. =item bit #4 denoting presence of Time-Stamp Counter.
  17. =item bit #19 denoting availability of CLFLUSH instruction;
  18. =item bit #20, reserved by Intel, is used to choose among RC4 code paths;
  19. =item bit #23 denoting MMX support;
  20. =item bit #24, FXSR bit, denoting availability of XMM registers;
  21. =item bit #25 denoting SSE support;
  22. =item bit #26 denoting SSE2 support;
  23. =item bit #28 denoting Hyperthreading, which is used to distiguish
  24. cores with shared cache;
  25. =item bit #30, reserved by Intel, denotes specifically Intel CPUs;
  26. =item bit #33 denoting availability of PCLMULQDQ instruction;
  27. =item bit #41 denoting SSSE3, Supplemental SSE3, support;
  28. =item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
  29. =item bit #57 denoting AES-NI instruction set extension;
  30. =item bit #59, OSXSAVE bit, denoting availability of YMM registers;
  31. =item bit #60 denoting AVX extension;
  32. =item bit #62 denoting availability of RDRAND instruction;
  33. For example, clearing bit #26 at run-time disables high-performance
  34. SSE2 code present in the crypto library, while clearing bit #24
  35. disables SSE2 code operating on 128-bit XMM register bank. You might
  36. have to do the latter if target OpenSSL application is executed on SSE2
  37. capable CPU, but under control of OS that does not enable XMM
  38. registers. Even though you can manipulate the value programmatically,
  39. you most likely will find it more appropriate to set up an environment
  40. variable with the same name prior starting target application, e.g. on
  41. Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or
  42. better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same
  43. effect without modifying the application source code. Alternatively you
  44. can reconfigure the toolkit with no-sse2 option and recompile.
  45. Less intuituve is clearing bit #28. The truth is that it's not copied
  46. from CPUID output verbatim, but is adjusted to reflect whether or not
  47. the data cache is actually shared between logical cores. This in turn
  48. affects the decision on whether or not expensive countermeasures
  49. against cache-timing attacks are applied, most notably in AES assembler
  50. module.