sha512-armv4.pl 18 KB

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  1. #! /usr/bin/env perl
  2. # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
  3. #
  4. # Licensed under the Apache License 2.0 (the "License"). You may not use
  5. # this file except in compliance with the License. You can obtain a copy
  6. # in the file LICENSE in the source distribution or at
  7. # https://www.openssl.org/source/license.html
  8. # ====================================================================
  9. # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
  10. # project. The module is, however, dual licensed under OpenSSL and
  11. # CRYPTOGAMS licenses depending on where you obtain it. For further
  12. # details see http://www.openssl.org/~appro/cryptogams/.
  13. #
  14. # Permission to use under GPL terms is granted.
  15. # ====================================================================
  16. # SHA512 block procedure for ARMv4. September 2007.
  17. # This code is ~4.5 (four and a half) times faster than code generated
  18. # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
  19. # Xscale PXA250 core].
  20. #
  21. # July 2010.
  22. #
  23. # Rescheduling for dual-issue pipeline resulted in 6% improvement on
  24. # Cortex A8 core and ~40 cycles per processed byte.
  25. # February 2011.
  26. #
  27. # Profiler-assisted and platform-specific optimization resulted in 7%
  28. # improvement on Coxtex A8 core and ~38 cycles per byte.
  29. # March 2011.
  30. #
  31. # Add NEON implementation. On Cortex A8 it was measured to process
  32. # one byte in 23.3 cycles or ~60% faster than integer-only code.
  33. # August 2012.
  34. #
  35. # Improve NEON performance by 12% on Snapdragon S4. In absolute
  36. # terms it's 22.6 cycles per byte, which is disappointing result.
  37. # Technical writers asserted that 3-way S4 pipeline can sustain
  38. # multiple NEON instructions per cycle, but dual NEON issue could
  39. # not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
  40. # for further details. On side note Cortex-A15 processes one byte in
  41. # 16 cycles.
  42. # Byte order [in]dependence. =========================================
  43. #
  44. # Originally caller was expected to maintain specific *dword* order in
  45. # h[0-7], namely with most significant dword at *lower* address, which
  46. # was reflected in below two parameters as 0 and 4. Now caller is
  47. # expected to maintain native byte order for whole 64-bit values.
  48. $hi="HI";
  49. $lo="LO";
  50. # ====================================================================
  51. # $output is the last argument if it looks like a file (it has an extension)
  52. # $flavour is the first argument if it doesn't look like a file
  53. $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
  54. $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
  55. if ($flavour && $flavour ne "void") {
  56. $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
  57. ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
  58. ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
  59. die "can't locate arm-xlate.pl";
  60. open STDOUT,"| \"$^X\" $xlate $flavour \"$output\""
  61. or die "can't call $xlate: $!";
  62. } else {
  63. $output and open STDOUT,">$output";
  64. }
  65. $ctx="r0"; # parameter block
  66. $inp="r1";
  67. $len="r2";
  68. $Tlo="r3";
  69. $Thi="r4";
  70. $Alo="r5";
  71. $Ahi="r6";
  72. $Elo="r7";
  73. $Ehi="r8";
  74. $t0="r9";
  75. $t1="r10";
  76. $t2="r11";
  77. $t3="r12";
  78. ############ r13 is stack pointer
  79. $Ktbl="r14";
  80. ############ r15 is program counter
  81. $Aoff=8*0;
  82. $Boff=8*1;
  83. $Coff=8*2;
  84. $Doff=8*3;
  85. $Eoff=8*4;
  86. $Foff=8*5;
  87. $Goff=8*6;
  88. $Hoff=8*7;
  89. $Xoff=8*8;
  90. sub BODY_00_15() {
  91. my $magic = shift;
  92. $code.=<<___;
  93. @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
  94. @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
  95. @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
  96. mov $t0,$Elo,lsr#14
  97. str $Tlo,[sp,#$Xoff+0]
  98. mov $t1,$Ehi,lsr#14
  99. str $Thi,[sp,#$Xoff+4]
  100. eor $t0,$t0,$Ehi,lsl#18
  101. ldr $t2,[sp,#$Hoff+0] @ h.lo
  102. eor $t1,$t1,$Elo,lsl#18
  103. ldr $t3,[sp,#$Hoff+4] @ h.hi
  104. eor $t0,$t0,$Elo,lsr#18
  105. eor $t1,$t1,$Ehi,lsr#18
  106. eor $t0,$t0,$Ehi,lsl#14
  107. eor $t1,$t1,$Elo,lsl#14
  108. eor $t0,$t0,$Ehi,lsr#9
  109. eor $t1,$t1,$Elo,lsr#9
  110. eor $t0,$t0,$Elo,lsl#23
  111. eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
  112. adds $Tlo,$Tlo,$t0
  113. ldr $t0,[sp,#$Foff+0] @ f.lo
  114. adc $Thi,$Thi,$t1 @ T += Sigma1(e)
  115. ldr $t1,[sp,#$Foff+4] @ f.hi
  116. adds $Tlo,$Tlo,$t2
  117. ldr $t2,[sp,#$Goff+0] @ g.lo
  118. adc $Thi,$Thi,$t3 @ T += h
  119. ldr $t3,[sp,#$Goff+4] @ g.hi
  120. eor $t0,$t0,$t2
  121. str $Elo,[sp,#$Eoff+0]
  122. eor $t1,$t1,$t3
  123. str $Ehi,[sp,#$Eoff+4]
  124. and $t0,$t0,$Elo
  125. str $Alo,[sp,#$Aoff+0]
  126. and $t1,$t1,$Ehi
  127. str $Ahi,[sp,#$Aoff+4]
  128. eor $t0,$t0,$t2
  129. ldr $t2,[$Ktbl,#$lo] @ K[i].lo
  130. eor $t1,$t1,$t3 @ Ch(e,f,g)
  131. ldr $t3,[$Ktbl,#$hi] @ K[i].hi
  132. adds $Tlo,$Tlo,$t0
  133. ldr $Elo,[sp,#$Doff+0] @ d.lo
  134. adc $Thi,$Thi,$t1 @ T += Ch(e,f,g)
  135. ldr $Ehi,[sp,#$Doff+4] @ d.hi
  136. adds $Tlo,$Tlo,$t2
  137. and $t0,$t2,#0xff
  138. adc $Thi,$Thi,$t3 @ T += K[i]
  139. adds $Elo,$Elo,$Tlo
  140. ldr $t2,[sp,#$Boff+0] @ b.lo
  141. adc $Ehi,$Ehi,$Thi @ d += T
  142. teq $t0,#$magic
  143. ldr $t3,[sp,#$Coff+0] @ c.lo
  144. #ifdef __thumb2__
  145. it eq @ Thumb2 thing, sanity check in ARM
  146. #endif
  147. orreq $Ktbl,$Ktbl,#1
  148. @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
  149. @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
  150. @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
  151. mov $t0,$Alo,lsr#28
  152. mov $t1,$Ahi,lsr#28
  153. eor $t0,$t0,$Ahi,lsl#4
  154. eor $t1,$t1,$Alo,lsl#4
  155. eor $t0,$t0,$Ahi,lsr#2
  156. eor $t1,$t1,$Alo,lsr#2
  157. eor $t0,$t0,$Alo,lsl#30
  158. eor $t1,$t1,$Ahi,lsl#30
  159. eor $t0,$t0,$Ahi,lsr#7
  160. eor $t1,$t1,$Alo,lsr#7
  161. eor $t0,$t0,$Alo,lsl#25
  162. eor $t1,$t1,$Ahi,lsl#25 @ Sigma0(a)
  163. adds $Tlo,$Tlo,$t0
  164. and $t0,$Alo,$t2
  165. adc $Thi,$Thi,$t1 @ T += Sigma0(a)
  166. ldr $t1,[sp,#$Boff+4] @ b.hi
  167. orr $Alo,$Alo,$t2
  168. ldr $t2,[sp,#$Coff+4] @ c.hi
  169. and $Alo,$Alo,$t3
  170. and $t3,$Ahi,$t1
  171. orr $Ahi,$Ahi,$t1
  172. orr $Alo,$Alo,$t0 @ Maj(a,b,c).lo
  173. and $Ahi,$Ahi,$t2
  174. adds $Alo,$Alo,$Tlo
  175. orr $Ahi,$Ahi,$t3 @ Maj(a,b,c).hi
  176. sub sp,sp,#8
  177. adc $Ahi,$Ahi,$Thi @ h += T
  178. tst $Ktbl,#1
  179. add $Ktbl,$Ktbl,#8
  180. ___
  181. }
  182. my $_word = ($flavour =~ /win/ ? "DCDU" : ".word");
  183. $code=<<___;
  184. #ifndef __KERNEL__
  185. # include "arm_arch.h"
  186. # define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
  187. # define VFP_ABI_POP vldmia sp!,{d8-d15}
  188. #else
  189. # define __ARM_ARCH__ __LINUX_ARM_ARCH__
  190. # define __ARM_MAX_ARCH__ 7
  191. # define VFP_ABI_PUSH
  192. # define VFP_ABI_POP
  193. #endif
  194. #ifdef __ARMEL__
  195. # define LO 0
  196. # define HI 4
  197. # define WORD64(hi0,lo0,hi1,lo1) $_word lo0,hi0, lo1,hi1
  198. #else
  199. # define HI 0
  200. # define LO 4
  201. # define WORD64(hi0,lo0,hi1,lo1) $_word hi0,lo0, hi1,lo1
  202. #endif
  203. #if defined(__thumb2__)
  204. .syntax unified
  205. .thumb
  206. # define adrl adr
  207. #else
  208. .code 32
  209. #endif
  210. .text
  211. .type K512,%object
  212. .align 5
  213. K512:
  214. WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd)
  215. WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc)
  216. WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019)
  217. WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118)
  218. WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe)
  219. WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2)
  220. WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1)
  221. WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694)
  222. WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3)
  223. WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65)
  224. WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483)
  225. WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5)
  226. WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210)
  227. WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4)
  228. WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725)
  229. WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70)
  230. WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926)
  231. WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df)
  232. WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8)
  233. WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b)
  234. WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001)
  235. WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30)
  236. WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910)
  237. WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8)
  238. WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53)
  239. WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8)
  240. WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb)
  241. WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3)
  242. WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60)
  243. WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec)
  244. WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9)
  245. WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b)
  246. WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207)
  247. WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178)
  248. WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6)
  249. WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b)
  250. WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493)
  251. WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
  252. WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
  253. WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
  254. .size K512,.-K512
  255. #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
  256. .LOPENSSL_armcap:
  257. # ifdef _WIN32
  258. .word OPENSSL_armcap_P
  259. # else
  260. .word OPENSSL_armcap_P-.Lsha512_block_data_order
  261. # endif
  262. .skip 32-4
  263. #else
  264. .skip 32
  265. #endif
  266. .global sha512_block_data_order
  267. .type sha512_block_data_order,%function
  268. sha512_block_data_order:
  269. .Lsha512_block_data_order:
  270. #if __ARM_ARCH__<7 && !defined(__thumb2__)
  271. sub r3,pc,#8 @ sha512_block_data_order
  272. #else
  273. adr r3,.Lsha512_block_data_order
  274. #endif
  275. #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
  276. ldr r12,.LOPENSSL_armcap
  277. # if !defined(_WIN32)
  278. ldr r12,[r3,r12] @ OPENSSL_armcap_P
  279. # endif
  280. # if defined(__APPLE__) || defined(_WIN32)
  281. ldr r12,[r12]
  282. # endif
  283. tst r12,#ARMV7_NEON
  284. bne .LNEON
  285. #endif
  286. add $len,$inp,$len,lsl#7 @ len to point at the end of inp
  287. stmdb sp!,{r4-r12,lr}
  288. sub $Ktbl,r3,#672 @ K512
  289. sub sp,sp,#9*8
  290. ldr $Elo,[$ctx,#$Eoff+$lo]
  291. ldr $Ehi,[$ctx,#$Eoff+$hi]
  292. ldr $t0, [$ctx,#$Goff+$lo]
  293. ldr $t1, [$ctx,#$Goff+$hi]
  294. ldr $t2, [$ctx,#$Hoff+$lo]
  295. ldr $t3, [$ctx,#$Hoff+$hi]
  296. .Loop:
  297. str $t0, [sp,#$Goff+0]
  298. str $t1, [sp,#$Goff+4]
  299. str $t2, [sp,#$Hoff+0]
  300. str $t3, [sp,#$Hoff+4]
  301. ldr $Alo,[$ctx,#$Aoff+$lo]
  302. ldr $Ahi,[$ctx,#$Aoff+$hi]
  303. ldr $Tlo,[$ctx,#$Boff+$lo]
  304. ldr $Thi,[$ctx,#$Boff+$hi]
  305. ldr $t0, [$ctx,#$Coff+$lo]
  306. ldr $t1, [$ctx,#$Coff+$hi]
  307. ldr $t2, [$ctx,#$Doff+$lo]
  308. ldr $t3, [$ctx,#$Doff+$hi]
  309. str $Tlo,[sp,#$Boff+0]
  310. str $Thi,[sp,#$Boff+4]
  311. str $t0, [sp,#$Coff+0]
  312. str $t1, [sp,#$Coff+4]
  313. str $t2, [sp,#$Doff+0]
  314. str $t3, [sp,#$Doff+4]
  315. ldr $Tlo,[$ctx,#$Foff+$lo]
  316. ldr $Thi,[$ctx,#$Foff+$hi]
  317. str $Tlo,[sp,#$Foff+0]
  318. str $Thi,[sp,#$Foff+4]
  319. .L00_15:
  320. #if __ARM_ARCH__<7
  321. ldrb $Tlo,[$inp,#7]
  322. ldrb $t0, [$inp,#6]
  323. ldrb $t1, [$inp,#5]
  324. ldrb $t2, [$inp,#4]
  325. ldrb $Thi,[$inp,#3]
  326. ldrb $t3, [$inp,#2]
  327. orr $Tlo,$Tlo,$t0,lsl#8
  328. ldrb $t0, [$inp,#1]
  329. orr $Tlo,$Tlo,$t1,lsl#16
  330. ldrb $t1, [$inp],#8
  331. orr $Tlo,$Tlo,$t2,lsl#24
  332. orr $Thi,$Thi,$t3,lsl#8
  333. orr $Thi,$Thi,$t0,lsl#16
  334. orr $Thi,$Thi,$t1,lsl#24
  335. #else
  336. ldr $Tlo,[$inp,#4]
  337. ldr $Thi,[$inp],#8
  338. #ifdef __ARMEL__
  339. rev $Tlo,$Tlo
  340. rev $Thi,$Thi
  341. #endif
  342. #endif
  343. ___
  344. &BODY_00_15(0x94);
  345. $code.=<<___;
  346. tst $Ktbl,#1
  347. beq .L00_15
  348. ldr $t0,[sp,#`$Xoff+8*(16-1)`+0]
  349. ldr $t1,[sp,#`$Xoff+8*(16-1)`+4]
  350. bic $Ktbl,$Ktbl,#1
  351. .L16_79:
  352. @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
  353. @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25
  354. @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7
  355. mov $Tlo,$t0,lsr#1
  356. ldr $t2,[sp,#`$Xoff+8*(16-14)`+0]
  357. mov $Thi,$t1,lsr#1
  358. ldr $t3,[sp,#`$Xoff+8*(16-14)`+4]
  359. eor $Tlo,$Tlo,$t1,lsl#31
  360. eor $Thi,$Thi,$t0,lsl#31
  361. eor $Tlo,$Tlo,$t0,lsr#8
  362. eor $Thi,$Thi,$t1,lsr#8
  363. eor $Tlo,$Tlo,$t1,lsl#24
  364. eor $Thi,$Thi,$t0,lsl#24
  365. eor $Tlo,$Tlo,$t0,lsr#7
  366. eor $Thi,$Thi,$t1,lsr#7
  367. eor $Tlo,$Tlo,$t1,lsl#25
  368. @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
  369. @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26
  370. @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6
  371. mov $t0,$t2,lsr#19
  372. mov $t1,$t3,lsr#19
  373. eor $t0,$t0,$t3,lsl#13
  374. eor $t1,$t1,$t2,lsl#13
  375. eor $t0,$t0,$t3,lsr#29
  376. eor $t1,$t1,$t2,lsr#29
  377. eor $t0,$t0,$t2,lsl#3
  378. eor $t1,$t1,$t3,lsl#3
  379. eor $t0,$t0,$t2,lsr#6
  380. eor $t1,$t1,$t3,lsr#6
  381. ldr $t2,[sp,#`$Xoff+8*(16-9)`+0]
  382. eor $t0,$t0,$t3,lsl#26
  383. ldr $t3,[sp,#`$Xoff+8*(16-9)`+4]
  384. adds $Tlo,$Tlo,$t0
  385. ldr $t0,[sp,#`$Xoff+8*16`+0]
  386. adc $Thi,$Thi,$t1
  387. ldr $t1,[sp,#`$Xoff+8*16`+4]
  388. adds $Tlo,$Tlo,$t2
  389. adc $Thi,$Thi,$t3
  390. adds $Tlo,$Tlo,$t0
  391. adc $Thi,$Thi,$t1
  392. ___
  393. &BODY_00_15(0x17);
  394. $code.=<<___;
  395. #ifdef __thumb2__
  396. ittt eq @ Thumb2 thing, sanity check in ARM
  397. #endif
  398. ldreq $t0,[sp,#`$Xoff+8*(16-1)`+0]
  399. ldreq $t1,[sp,#`$Xoff+8*(16-1)`+4]
  400. beq .L16_79
  401. bic $Ktbl,$Ktbl,#1
  402. ldr $Tlo,[sp,#$Boff+0]
  403. ldr $Thi,[sp,#$Boff+4]
  404. ldr $t0, [$ctx,#$Aoff+$lo]
  405. ldr $t1, [$ctx,#$Aoff+$hi]
  406. ldr $t2, [$ctx,#$Boff+$lo]
  407. ldr $t3, [$ctx,#$Boff+$hi]
  408. adds $t0,$Alo,$t0
  409. str $t0, [$ctx,#$Aoff+$lo]
  410. adc $t1,$Ahi,$t1
  411. str $t1, [$ctx,#$Aoff+$hi]
  412. adds $t2,$Tlo,$t2
  413. str $t2, [$ctx,#$Boff+$lo]
  414. adc $t3,$Thi,$t3
  415. str $t3, [$ctx,#$Boff+$hi]
  416. ldr $Alo,[sp,#$Coff+0]
  417. ldr $Ahi,[sp,#$Coff+4]
  418. ldr $Tlo,[sp,#$Doff+0]
  419. ldr $Thi,[sp,#$Doff+4]
  420. ldr $t0, [$ctx,#$Coff+$lo]
  421. ldr $t1, [$ctx,#$Coff+$hi]
  422. ldr $t2, [$ctx,#$Doff+$lo]
  423. ldr $t3, [$ctx,#$Doff+$hi]
  424. adds $t0,$Alo,$t0
  425. str $t0, [$ctx,#$Coff+$lo]
  426. adc $t1,$Ahi,$t1
  427. str $t1, [$ctx,#$Coff+$hi]
  428. adds $t2,$Tlo,$t2
  429. str $t2, [$ctx,#$Doff+$lo]
  430. adc $t3,$Thi,$t3
  431. str $t3, [$ctx,#$Doff+$hi]
  432. ldr $Tlo,[sp,#$Foff+0]
  433. ldr $Thi,[sp,#$Foff+4]
  434. ldr $t0, [$ctx,#$Eoff+$lo]
  435. ldr $t1, [$ctx,#$Eoff+$hi]
  436. ldr $t2, [$ctx,#$Foff+$lo]
  437. ldr $t3, [$ctx,#$Foff+$hi]
  438. adds $Elo,$Elo,$t0
  439. str $Elo,[$ctx,#$Eoff+$lo]
  440. adc $Ehi,$Ehi,$t1
  441. str $Ehi,[$ctx,#$Eoff+$hi]
  442. adds $t2,$Tlo,$t2
  443. str $t2, [$ctx,#$Foff+$lo]
  444. adc $t3,$Thi,$t3
  445. str $t3, [$ctx,#$Foff+$hi]
  446. ldr $Alo,[sp,#$Goff+0]
  447. ldr $Ahi,[sp,#$Goff+4]
  448. ldr $Tlo,[sp,#$Hoff+0]
  449. ldr $Thi,[sp,#$Hoff+4]
  450. ldr $t0, [$ctx,#$Goff+$lo]
  451. ldr $t1, [$ctx,#$Goff+$hi]
  452. ldr $t2, [$ctx,#$Hoff+$lo]
  453. ldr $t3, [$ctx,#$Hoff+$hi]
  454. adds $t0,$Alo,$t0
  455. str $t0, [$ctx,#$Goff+$lo]
  456. adc $t1,$Ahi,$t1
  457. str $t1, [$ctx,#$Goff+$hi]
  458. adds $t2,$Tlo,$t2
  459. str $t2, [$ctx,#$Hoff+$lo]
  460. adc $t3,$Thi,$t3
  461. str $t3, [$ctx,#$Hoff+$hi]
  462. add sp,sp,#640
  463. sub $Ktbl,$Ktbl,#640
  464. teq $inp,$len
  465. bne .Loop
  466. add sp,sp,#8*9 @ destroy frame
  467. #if __ARM_ARCH__>=5
  468. ldmia sp!,{r4-r12,pc}
  469. #else
  470. ldmia sp!,{r4-r12,lr}
  471. tst lr,#1
  472. moveq pc,lr @ be binary compatible with V4, yet
  473. bx lr @ interoperable with Thumb ISA:-)
  474. #endif
  475. .size sha512_block_data_order,.-sha512_block_data_order
  476. ___
  477. {
  478. my @Sigma0=(28,34,39);
  479. my @Sigma1=(14,18,41);
  480. my @sigma0=(1, 8, 7);
  481. my @sigma1=(19,61,6);
  482. my $Ktbl="r3";
  483. my $cnt="r12"; # volatile register known as ip, intra-procedure-call scratch
  484. my @X=map("d$_",(0..15));
  485. my @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("d$_",(16..23));
  486. sub NEON_00_15() {
  487. my $i=shift;
  488. my ($a,$b,$c,$d,$e,$f,$g,$h)=@_;
  489. my ($t0,$t1,$t2,$T1,$K,$Ch,$Maj)=map("d$_",(24..31)); # temps
  490. $code.=<<___ if ($i<16 || $i&1);
  491. vshr.u64 $t0,$e,#@Sigma1[0] @ $i
  492. #if $i<16
  493. vld1.64 {@X[$i%16]},[$inp]! @ handles unaligned
  494. #endif
  495. vshr.u64 $t1,$e,#@Sigma1[1]
  496. #if $i>0
  497. vadd.i64 $a,$Maj @ h+=Maj from the past
  498. #endif
  499. vshr.u64 $t2,$e,#@Sigma1[2]
  500. ___
  501. $code.=<<___;
  502. vld1.64 {$K},[$Ktbl,:64]! @ K[i++]
  503. vsli.64 $t0,$e,#`64-@Sigma1[0]`
  504. vsli.64 $t1,$e,#`64-@Sigma1[1]`
  505. vmov $Ch,$e
  506. vsli.64 $t2,$e,#`64-@Sigma1[2]`
  507. #if $i<16 && defined(__ARMEL__)
  508. vrev64.8 @X[$i],@X[$i]
  509. #endif
  510. veor $t1,$t0
  511. vbsl $Ch,$f,$g @ Ch(e,f,g)
  512. vshr.u64 $t0,$a,#@Sigma0[0]
  513. veor $t2,$t1 @ Sigma1(e)
  514. vadd.i64 $T1,$Ch,$h
  515. vshr.u64 $t1,$a,#@Sigma0[1]
  516. vsli.64 $t0,$a,#`64-@Sigma0[0]`
  517. vadd.i64 $T1,$t2
  518. vshr.u64 $t2,$a,#@Sigma0[2]
  519. vadd.i64 $K,@X[$i%16]
  520. vsli.64 $t1,$a,#`64-@Sigma0[1]`
  521. veor $Maj,$a,$b
  522. vsli.64 $t2,$a,#`64-@Sigma0[2]`
  523. veor $h,$t0,$t1
  524. vadd.i64 $T1,$K
  525. vbsl $Maj,$c,$b @ Maj(a,b,c)
  526. veor $h,$t2 @ Sigma0(a)
  527. vadd.i64 $d,$T1
  528. vadd.i64 $Maj,$T1
  529. @ vadd.i64 $h,$Maj
  530. ___
  531. }
  532. sub NEON_16_79() {
  533. my $i=shift;
  534. if ($i&1) { &NEON_00_15($i,@_); return; }
  535. # 2x-vectorized, therefore runs every 2nd round
  536. my @X=map("q$_",(0..7)); # view @X as 128-bit vector
  537. my ($t0,$t1,$s0,$s1) = map("q$_",(12..15)); # temps
  538. my ($d0,$d1,$d2) = map("d$_",(24..26)); # temps from NEON_00_15
  539. my $e=@_[4]; # $e from NEON_00_15
  540. $i /= 2;
  541. $code.=<<___;
  542. vshr.u64 $t0,@X[($i+7)%8],#@sigma1[0]
  543. vshr.u64 $t1,@X[($i+7)%8],#@sigma1[1]
  544. vadd.i64 @_[0],d30 @ h+=Maj from the past
  545. vshr.u64 $s1,@X[($i+7)%8],#@sigma1[2]
  546. vsli.64 $t0,@X[($i+7)%8],#`64-@sigma1[0]`
  547. vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1]
  548. vsli.64 $t1,@X[($i+7)%8],#`64-@sigma1[1]`
  549. veor $s1,$t0
  550. vshr.u64 $t0,$s0,#@sigma0[0]
  551. veor $s1,$t1 @ sigma1(X[i+14])
  552. vshr.u64 $t1,$s0,#@sigma0[1]
  553. vadd.i64 @X[$i%8],$s1
  554. vshr.u64 $s1,$s0,#@sigma0[2]
  555. vsli.64 $t0,$s0,#`64-@sigma0[0]`
  556. vsli.64 $t1,$s0,#`64-@sigma0[1]`
  557. vext.8 $s0,@X[($i+4)%8],@X[($i+5)%8],#8 @ X[i+9]
  558. veor $s1,$t0
  559. vshr.u64 $d0,$e,#@Sigma1[0] @ from NEON_00_15
  560. vadd.i64 @X[$i%8],$s0
  561. vshr.u64 $d1,$e,#@Sigma1[1] @ from NEON_00_15
  562. veor $s1,$t1 @ sigma0(X[i+1])
  563. vshr.u64 $d2,$e,#@Sigma1[2] @ from NEON_00_15
  564. vadd.i64 @X[$i%8],$s1
  565. ___
  566. &NEON_00_15(2*$i,@_);
  567. }
  568. $code.=<<___;
  569. #if __ARM_MAX_ARCH__>=7
  570. .arch armv7-a
  571. .fpu neon
  572. .global sha512_block_data_order_neon
  573. .type sha512_block_data_order_neon,%function
  574. .align 4
  575. sha512_block_data_order_neon:
  576. .LNEON:
  577. dmb @ errata #451034 on early Cortex A8
  578. add $len,$inp,$len,lsl#7 @ len to point at the end of inp
  579. adr $Ktbl,K512
  580. VFP_ABI_PUSH
  581. vldmia $ctx,{$A-$H} @ load context
  582. .Loop_neon:
  583. ___
  584. for($i=0;$i<16;$i++) { &NEON_00_15($i,@V); unshift(@V,pop(@V)); }
  585. $code.=<<___;
  586. mov $cnt,#4
  587. .L16_79_neon:
  588. subs $cnt,#1
  589. ___
  590. for(;$i<32;$i++) { &NEON_16_79($i,@V); unshift(@V,pop(@V)); }
  591. $code.=<<___;
  592. bne .L16_79_neon
  593. vadd.i64 $A,d30 @ h+=Maj from the past
  594. vldmia $ctx,{d24-d31} @ load context to temp
  595. vadd.i64 q8,q12 @ vectorized accumulate
  596. vadd.i64 q9,q13
  597. vadd.i64 q10,q14
  598. vadd.i64 q11,q15
  599. vstmia $ctx,{$A-$H} @ save context
  600. teq $inp,$len
  601. sub $Ktbl,#640 @ rewind K512
  602. bne .Loop_neon
  603. VFP_ABI_POP
  604. ret @ bx lr
  605. .size sha512_block_data_order_neon,.-sha512_block_data_order_neon
  606. #endif
  607. ___
  608. }
  609. $code.=<<___;
  610. .asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
  611. .align 2
  612. #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
  613. .comm OPENSSL_armcap_P,4,4
  614. #endif
  615. ___
  616. $code =~ s/\`([^\`]*)\`/eval $1/gem;
  617. $code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
  618. $code =~ s/\bret\b/bx lr/gm;
  619. open SELF,$0;
  620. while(<SELF>) {
  621. next if (/^#!/);
  622. last if (!s/^#/@/ and !/^$/);
  623. print;
  624. }
  625. close SELF;
  626. print $code;
  627. close STDOUT or die "error closing STDOUT: $!"; # enforce flush