armv4cpuid.pl 5.6 KB

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  1. #! /usr/bin/env perl
  2. # Copyright 2015-2018 The OpenSSL Project Authors. All Rights Reserved.
  3. #
  4. # Licensed under the Apache License 2.0 (the "License"). You may not use
  5. # this file except in compliance with the License. You can obtain a copy
  6. # in the file LICENSE in the source distribution or at
  7. # https://www.openssl.org/source/license.html
  8. # $output is the last argument if it looks like a file (it has an extension)
  9. # $flavour is the first argument if it doesn't look like a file
  10. $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
  11. $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
  12. $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
  13. ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
  14. ( $xlate="${dir}perlasm/arm-xlate.pl" and -f $xlate) or
  15. die "can't locate arm-xlate.pl";
  16. open OUT,"| \"$^X\" $xlate $flavour \"$output\""
  17. or die "can't call $xlate: $!";
  18. *STDOUT=*OUT;
  19. $code.=<<___;
  20. #include "arm_arch.h"
  21. #if defined(__thumb2__) && !defined(__APPLE__)
  22. .syntax unified
  23. .thumb
  24. #else
  25. .code 32
  26. #undef __thumb2__
  27. #endif
  28. .text
  29. .align 5
  30. .global OPENSSL_atomic_add
  31. .type OPENSSL_atomic_add,%function
  32. OPENSSL_atomic_add:
  33. #if __ARM_ARCH__>=6
  34. .Ladd: ldrex r2,[r0]
  35. add r3,r2,r1
  36. strex r2,r3,[r0]
  37. cmp r2,#0
  38. bne .Ladd
  39. mov r0,r3
  40. bx lr
  41. #else
  42. stmdb sp!,{r4-r6,lr}
  43. ldr r2,.Lspinlock
  44. adr r3,.Lspinlock
  45. mov r4,r0
  46. mov r5,r1
  47. add r6,r3,r2 @ &spinlock
  48. b .+8
  49. .Lspin: bl sched_yield
  50. mov r0,#-1
  51. swp r0,r0,[r6]
  52. cmp r0,#0
  53. bne .Lspin
  54. ldr r2,[r4]
  55. add r2,r2,r5
  56. str r2,[r4]
  57. str r0,[r6] @ release spinlock
  58. ldmia sp!,{r4-r6,lr}
  59. tst lr,#1
  60. moveq pc,lr
  61. .word 0xe12fff1e @ bx lr
  62. #endif
  63. .size OPENSSL_atomic_add,.-OPENSSL_atomic_add
  64. .global OPENSSL_cleanse
  65. .type OPENSSL_cleanse,%function
  66. OPENSSL_cleanse:
  67. eor ip,ip,ip
  68. cmp r1,#7
  69. #ifdef __thumb2__
  70. itt hs
  71. #endif
  72. subhs r1,r1,#4
  73. bhs .Lot
  74. cmp r1,#0
  75. beq .Lcleanse_done
  76. .Little:
  77. strb ip,[r0],#1
  78. subs r1,r1,#1
  79. bhi .Little
  80. b .Lcleanse_done
  81. .Lot: tst r0,#3
  82. beq .Laligned
  83. strb ip,[r0],#1
  84. sub r1,r1,#1
  85. b .Lot
  86. .Laligned:
  87. str ip,[r0],#4
  88. subs r1,r1,#4
  89. bhs .Laligned
  90. adds r1,r1,#4
  91. bne .Little
  92. .Lcleanse_done:
  93. #if __ARM_ARCH__>=5
  94. bx lr
  95. #else
  96. tst lr,#1
  97. moveq pc,lr
  98. .word 0xe12fff1e @ bx lr
  99. #endif
  100. .size OPENSSL_cleanse,.-OPENSSL_cleanse
  101. .global CRYPTO_memcmp
  102. .type CRYPTO_memcmp,%function
  103. .align 4
  104. CRYPTO_memcmp:
  105. eor ip,ip,ip
  106. cmp r2,#0
  107. beq .Lno_data
  108. stmdb sp!,{r4,r5}
  109. .Loop_cmp:
  110. ldrb r4,[r0],#1
  111. ldrb r5,[r1],#1
  112. eor r4,r4,r5
  113. orr ip,ip,r4
  114. subs r2,r2,#1
  115. bne .Loop_cmp
  116. ldmia sp!,{r4,r5}
  117. .Lno_data:
  118. rsb r0,ip,#0
  119. mov r0,r0,lsr#31
  120. #if __ARM_ARCH__>=5
  121. bx lr
  122. #else
  123. tst lr,#1
  124. moveq pc,lr
  125. .word 0xe12fff1e @ bx lr
  126. #endif
  127. .size CRYPTO_memcmp,.-CRYPTO_memcmp
  128. #if __ARM_MAX_ARCH__>=7
  129. .arch armv7-a
  130. .fpu neon
  131. .align 5
  132. .global _armv7_neon_probe
  133. .type _armv7_neon_probe,%function
  134. _armv7_neon_probe:
  135. vorr q0,q0,q0
  136. bx lr
  137. .size _armv7_neon_probe,.-_armv7_neon_probe
  138. .global _armv7_tick
  139. .type _armv7_tick,%function
  140. _armv7_tick:
  141. #ifdef __APPLE__
  142. mrrc p15,0,r0,r1,c14 @ CNTPCT
  143. #else
  144. mrrc p15,1,r0,r1,c14 @ CNTVCT
  145. #endif
  146. bx lr
  147. .size _armv7_tick,.-_armv7_tick
  148. .global _armv8_aes_probe
  149. .type _armv8_aes_probe,%function
  150. _armv8_aes_probe:
  151. #if defined(__thumb2__) && !defined(__APPLE__)
  152. .byte 0xb0,0xff,0x00,0x03 @ aese.8 q0,q0
  153. #else
  154. .byte 0x00,0x03,0xb0,0xf3 @ aese.8 q0,q0
  155. #endif
  156. bx lr
  157. .size _armv8_aes_probe,.-_armv8_aes_probe
  158. .global _armv8_sha1_probe
  159. .type _armv8_sha1_probe,%function
  160. _armv8_sha1_probe:
  161. #if defined(__thumb2__) && !defined(__APPLE__)
  162. .byte 0x00,0xef,0x40,0x0c @ sha1c.32 q0,q0,q0
  163. #else
  164. .byte 0x40,0x0c,0x00,0xf2 @ sha1c.32 q0,q0,q0
  165. #endif
  166. bx lr
  167. .size _armv8_sha1_probe,.-_armv8_sha1_probe
  168. .global _armv8_sha256_probe
  169. .type _armv8_sha256_probe,%function
  170. _armv8_sha256_probe:
  171. #if defined(__thumb2__) && !defined(__APPLE__)
  172. .byte 0x00,0xff,0x40,0x0c @ sha256h.32 q0,q0,q0
  173. #else
  174. .byte 0x40,0x0c,0x00,0xf3 @ sha256h.32 q0,q0,q0
  175. #endif
  176. bx lr
  177. .size _armv8_sha256_probe,.-_armv8_sha256_probe
  178. .global _armv8_pmull_probe
  179. .type _armv8_pmull_probe,%function
  180. _armv8_pmull_probe:
  181. #if defined(__thumb2__) && !defined(__APPLE__)
  182. .byte 0xa0,0xef,0x00,0x0e @ vmull.p64 q0,d0,d0
  183. #else
  184. .byte 0x00,0x0e,0xa0,0xf2 @ vmull.p64 q0,d0,d0
  185. #endif
  186. bx lr
  187. .size _armv8_pmull_probe,.-_armv8_pmull_probe
  188. #endif
  189. .global OPENSSL_wipe_cpu
  190. .type OPENSSL_wipe_cpu,%function
  191. OPENSSL_wipe_cpu:
  192. #if __ARM_MAX_ARCH__>=7
  193. ldr r0,.LOPENSSL_armcap
  194. adr r1,.LOPENSSL_armcap
  195. ldr r0,[r1,r0]
  196. #ifdef __APPLE__
  197. ldr r0,[r0]
  198. #endif
  199. #endif
  200. eor r2,r2,r2
  201. eor r3,r3,r3
  202. eor ip,ip,ip
  203. #if __ARM_MAX_ARCH__>=7
  204. tst r0,#1
  205. beq .Lwipe_done
  206. veor q0, q0, q0
  207. veor q1, q1, q1
  208. veor q2, q2, q2
  209. veor q3, q3, q3
  210. veor q8, q8, q8
  211. veor q9, q9, q9
  212. veor q10, q10, q10
  213. veor q11, q11, q11
  214. veor q12, q12, q12
  215. veor q13, q13, q13
  216. veor q14, q14, q14
  217. veor q15, q15, q15
  218. .Lwipe_done:
  219. #endif
  220. mov r0,sp
  221. #if __ARM_ARCH__>=5
  222. bx lr
  223. #else
  224. tst lr,#1
  225. moveq pc,lr
  226. .word 0xe12fff1e @ bx lr
  227. #endif
  228. .size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
  229. .global OPENSSL_instrument_bus
  230. .type OPENSSL_instrument_bus,%function
  231. OPENSSL_instrument_bus:
  232. eor r0,r0,r0
  233. #if __ARM_ARCH__>=5
  234. bx lr
  235. #else
  236. tst lr,#1
  237. moveq pc,lr
  238. .word 0xe12fff1e @ bx lr
  239. #endif
  240. .size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
  241. .global OPENSSL_instrument_bus2
  242. .type OPENSSL_instrument_bus2,%function
  243. OPENSSL_instrument_bus2:
  244. eor r0,r0,r0
  245. #if __ARM_ARCH__>=5
  246. bx lr
  247. #else
  248. tst lr,#1
  249. moveq pc,lr
  250. .word 0xe12fff1e @ bx lr
  251. #endif
  252. .size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
  253. .align 5
  254. #if __ARM_MAX_ARCH__>=7
  255. .LOPENSSL_armcap:
  256. .word OPENSSL_armcap_P-.
  257. #endif
  258. #if __ARM_ARCH__>=6
  259. .align 5
  260. #else
  261. .Lspinlock:
  262. .word atomic_add_spinlock-.Lspinlock
  263. .align 5
  264. .data
  265. .align 2
  266. atomic_add_spinlock:
  267. .word 0
  268. #endif
  269. .comm OPENSSL_armcap_P,4,4
  270. .hidden OPENSSL_armcap_P
  271. ___
  272. print $code;
  273. close STDOUT;