OPENSSL_ia32cap.pod 2.1 KB

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  1. =pod
  2. =head1 NAME
  3. OPENSSL_ia32cap - finding the IA-32 processor capabilities
  4. =head1 SYNOPSIS
  5. unsigned int *OPENSSL_ia32cap_loc(void);
  6. #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
  7. =head1 DESCRIPTION
  8. Value returned by OPENSSL_ia32cap_loc() is address of a variable
  9. containing IA-32 processor capabilities bit vector as it appears in
  10. EDX:ECX register pair after executing CPUID instruction with EAX=1
  11. input value (see Intel Application Note #241618). Naturally it's
  12. meaningful on x86 and x86_64 platforms only. The variable is normally
  13. set up automatically upon toolkit initialization, but can be
  14. manipulated afterwards to modify crypto library behaviour. For the
  15. moment of this writing seven bits are significant, namely:
  16. 1. bit #4 denoting presence of Time-Stamp Counter.
  17. 2. bit #20, reserved by Intel, is used to choose between RC4 code
  18. paths;
  19. 3. bit #23 denoting MMX support;
  20. 4. bit #25 denoting SSE support;
  21. 5. bit #26 denoting SSE2 support;
  22. 6. bit #28 denoting Hyperthreading, which is used to distiguish
  23. cores with shared cache;
  24. 7. bit #57 denoting Intel AES instruction set extension;
  25. For example, clearing bit #26 at run-time disables high-performance
  26. SSE2 code present in the crypto library. You might have to do this if
  27. target OpenSSL application is executed on SSE2 capable CPU, but under
  28. control of OS which does not support SSE2 extentions. Even though you
  29. can manipulate the value programmatically, you most likely will find it
  30. more appropriate to set up an environment variable with the same name
  31. prior starting target application, e.g. on Intel P4 processor 'env
  32. OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
  33. without modifying the application source code. Alternatively you can
  34. reconfigure the toolkit with no-sse2 option and recompile.
  35. Less intuituve is clearing bit #28. The truth is that it's not copied
  36. from CPUID output verbatim, but is adjusted to reflect whether or not
  37. the data cache is actually shared between logical cores. This in turn
  38. affects the decision on whether or not expensive countermeasures
  39. against cache-timing attacks are applied, most notably in AES assembler
  40. module.
  41. =cut