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devices.h 9.6 KB

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  1. /* devices.h
  2. *
  3. * Copyright (C) 2006-2023 wolfSSL Inc.
  4. *
  5. * This file is part of wolfSSL.
  6. *
  7. * wolfSSL is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * wolfSSL is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  20. */
  21. /* Minimalist BSP for IoT-Safe example based on
  22. * ST P-L596G-CELL02 + Quectel BG96 modem
  23. */
  24. #ifndef STM32L496_DEVICES
  25. #define STM32L496_DEVICES
  26. /* CPU clock speed */
  27. //#define CLOCK_SPEED 14200000
  28. //#define CLOCK_SPEED 6000000
  29. #define CLOCK_SPEED 40000000
  30. /* Memory mapping */
  31. #define USART1_BASE (0x40013800UL)
  32. #define USART2_BASE (0x40004400UL)
  33. #define GPIOA_BASE (0x48000000UL)
  34. #define GPIOB_BASE (0x48000400UL)
  35. #define GPIOC_BASE (0x48000800UL)
  36. #define GPIOD_BASE (0x48000C00UL)
  37. #define GPIOE_BASE (0x48001000UL)
  38. #define GPIOF_BASE (0x48001400UL)
  39. #define GPIOG_BASE (0x48001800UL)
  40. #define GPIOH_BASE (0x48001C00UL)
  41. #define GPIOI_BASE (0x48002000UL)
  42. #define RCC_BASE (0x40021000UL)
  43. #define PWR_BASE (0x40007000UL)
  44. /* USART */
  45. #define USART_CR1(x) (*((volatile uint32_t *)(x + 0x00)))
  46. #define USART_CR2(x) (*((volatile uint32_t *)(x + 0x04)))
  47. #define USART_CR3(x) (*((volatile uint32_t *)(x + 0x08)))
  48. #define USART_BRR(x) (*((volatile uint32_t *)(x + 0x0C)))
  49. #define USART_ISR(x) (*((volatile uint32_t *)(x + 0x1C)))
  50. #define USART_ICR(x) (*((volatile uint32_t *)(x + 0x20)))
  51. #define USART_RDR(x) (*((volatile uint8_t *)(x + 0x24)))
  52. #define USART_TDR(x) (*((volatile uint8_t *)(x + 0x28)))
  53. /* GPIO */
  54. #define GPIO_MODE(x) (*((volatile uint32_t *)(x + 0x00)))
  55. #define GPIO_SPEED(x) (*((volatile uint32_t *)(x + 0x08)))
  56. #define GPIO_PUPD(x) (*((volatile uint32_t *)(x + 0x0C)))
  57. #define GPIO_AFL(x) (*((volatile uint32_t *)(x + 0x20)))
  58. #define GPIO_AFH(x) (*((volatile uint32_t *)(x + 0x24)))
  59. #define GPIO_BSSR(x) (*((volatile uint32_t *)(x + 0x18)))
  60. /* RCC */
  61. #define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
  62. #define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
  63. #define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C))
  64. #define RCC_CCIPR (*(volatile uint32_t *)(RCC_BASE + 0x88))
  65. #define RCC_AHB1_ENR (*(volatile uint32_t *)(RCC_BASE + 0x48))
  66. #define RCC_AHB2_ENR (*(volatile uint32_t *)(RCC_BASE + 0x4C))
  67. #define RCC_AHB3_ENR (*(volatile uint32_t *)(RCC_BASE + 0x50))
  68. #define RCC_APB1_ENR (*(volatile uint32_t *)(RCC_BASE + 0x58))
  69. #define RCC_APB2_ENR (*(volatile uint32_t *)(RCC_BASE + 0x60))
  70. /* PWR */
  71. #define PWR_CR1 (*(volatile uint32_t *)(PWR_BASE + 0x00))
  72. #define PWR_CR2 (*(volatile uint32_t *)(PWR_BASE + 0x04))
  73. #define PWR_SR2 (*(volatile uint32_t *)(PWR_BASE + 0x014))
  74. #define PWR_CR1_DBP (1 << 8)
  75. #define PWR_CR2_PVME2 (1 << 5)
  76. #define PWR_CR2_IOSV (1 << 9)
  77. #define PWR_SR2_PVMO2 (1 << 13)
  78. /* FLASH registers + latency mask */
  79. #define FLASH_BASE 0x40022000
  80. #define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
  81. #define FLASH_ACR_LATENCY_MASK (0x03)
  82. /* RCC: Periph enable flags */
  83. #define USART1_APB2_CLOCK_ER_VAL (1 << 14)
  84. #define USART2_APB1_CLOCK_ER_VAL (1 << 17)
  85. #define PWR_APB1_CLOCK_ER_VAL (1 << 28)
  86. #define GPIOA_AHB2_CLOCK_ER_VAL (1 << 0)
  87. #define GPIOB_AHB2_CLOCK_ER_VAL (1 << 1)
  88. #define GPIOC_AHB2_CLOCK_ER_VAL (1 << 2)
  89. #define GPIOD_AHB2_CLOCK_ER_VAL (1 << 3)
  90. #define GPIOE_AHB2_CLOCK_ER_VAL (1 << 4)
  91. #define GPIOF_AHB2_CLOCK_ER_VAL (1 << 5)
  92. #define GPIOG_AHB2_CLOCK_ER_VAL (1 << 6)
  93. #define GPIOH_AHB2_CLOCK_ER_VAL (1 << 7)
  94. #define GPIOI_AHB2_CLOCK_ER_VAL (1 << 8)
  95. /* Pinout: USART */
  96. #define USART1_PIN_RX (10) /* PG10 */
  97. #define USART1_PIN_TX (6) /* PB6 */
  98. #define USART1_PIN_CTS (11) /* PG11 */
  99. #define USART1_PIN_RTS (12) /* PG12 */
  100. #define USART1_AF (7)
  101. #define USART2_PIN_RX (6) /* PD6 */
  102. #define USART2_PIN_TX (2) /* PA2 */
  103. #define USART2_AF (7)
  104. /* USART registers: flags */
  105. #define USART_CR1_ENABLE (1 << 0)
  106. #define USART_CR1_TX_ENABLE (1 << 3)
  107. #define USART_CR1_RX_ENABLE (1 << 2)
  108. #define USART_CR1_RXNEIE (1 << 5)
  109. #define USART_CR1_PEIE (1 << 8)
  110. #define USART_CR1_PARITY_ODD (1 << 9)
  111. #define USART_CR1_PARITY_ENABLED (1 << 10)
  112. #define USART_CR1_SYMBOL_LEN (1 << 28)
  113. #define USART_CR2_ABREN (1 << 20)
  114. #define USART_CR3_EIE (1 << 0)
  115. #define USART_CR3_RTSE (1 << 8)
  116. #define USART_CR3_CTSE (1 << 9)
  117. #define USART_ISR_TXE (1 << 7)
  118. #define USART_ISR_RXNE (1 << 5)
  119. #define USART_ICR_CTSCF (1 << 9)
  120. #define USART_ICR_CMCF (1 << 17)
  121. /* RCC_CR/CFGR/PLLCFGR values */
  122. #define RCC_PRESCALER_DIV_NONE 0
  123. #define RCC_PRESCALER_DIV_2 8
  124. #define RCC_PRESCALER_DIV_4 9
  125. #define RCC_CR_PLLRDY (1 << 25)
  126. #define RCC_CR_PLLON (1 << 24)
  127. #define RCC_CR_MSIRGSEL (1 << 3)
  128. #define RCC_CR_MSIRDY (1 << 1)
  129. #define RCC_CR_MSION (1 << 0)
  130. #define RCC_CR_HSIRDY (1 << 10)
  131. #define RCC_CR_HSION (1 << 8)
  132. #define RCC_CR_MSIRANGE_SHIFT 4
  133. #define RCC_CR_MSIRANGE_9 (0x09 << 4)
  134. #define RCC_CR_MSIRANGE_6 (0x06 << 4)
  135. #define RCC_CR_MSIRANGE_Msk (0x0F << 4)
  136. #define RCC_CFGR_HPRE_MASK 0x0F
  137. #define RCC_CFGR_PPRE1_MASK 0x07
  138. #define RCC_CFGR_PPRE2_MASK 0x07
  139. #define RCC_CFGR_HPRE_SHIFT 4
  140. #define RCC_CFGR_PPRE1_SHIFT 8
  141. #define RCC_CFGR_PPRE2_SHIFT 11
  142. #define RCC_CFGR_SW_MSI 0x0
  143. #define RCC_CFGR_SW_PLL 0x3
  144. #define RCC_CFGR_SW_MASK 0x3
  145. /* Bits 0:1 SRC */
  146. #define RCC_PLLCFGR_SRC_SHIFT 0
  147. #define RCC_PLLCFGR_PLLSRC_MSI 0x1
  148. #define RCC_PLLCFGR_PLLSRC_MASK 0x3
  149. /* Bits 4:6 PLLM */
  150. //#define PLLCFGR_PLLM (0x4 << 4)
  151. #define PLLCFGR_PLLM (0x1 << 4)
  152. #define RCC_PLLCFGR_PLLM_MASK (0x7 << 4)
  153. /* Bits 8:14 PLLN */
  154. //#define PLLCFGR_PLLN (71 << 8)
  155. #define PLLCFGR_PLLN (40 << 8)
  156. #define RCC_PLLCFGR_PLLN_MASK (0x7f << 8)
  157. /* Bits 27:31 PLLPDIV */
  158. #define PLLCFGR_PLLP (2 << 27)
  159. #define RCC_PLLCFGR_PLLP_MASK (0x1F << 27)
  160. /* Bits 21:22 PLLQ */
  161. #define PLLCFGR_PLLQ (0 << 21)
  162. #define RCC_PLLCFGR_PLLQ_MASK (0x3 << 21)
  163. /* Bits 25:26 PLLR */
  164. //#define PLLCFGR_PLLR (2 << 25)
  165. #define PLLCFGR_PLLR (0 << 25)
  166. #define RCC_PLLCFGR_PLLR_MASK (0x3 << 25)
  167. /* Enablers */
  168. #define RCC_PLLCFGR_PLLP_EN (0 << 16)
  169. #define RCC_PLLCFGR_PLLQ_EN (0 << 20)
  170. #define RCC_PLLCFGR_PLLR_EN (1 << 24)
  171. /* Systick */
  172. #define SYSTICK_BASE (0xE000E010)
  173. #define SYSTICK_CSR (*(volatile uint32_t *)(SYSTICK_BASE + 0x00))
  174. #define SYSTICK_RVR (*(volatile uint32_t *)(SYSTICK_BASE + 0x04))
  175. #define SYSTICK_CVR (*(volatile uint32_t *)(SYSTICK_BASE + 0x08))
  176. #define SYSTICK_CALIB (*(volatile uint32_t *)(SYSTICK_BASE + 0x0C))
  177. /* STMod+ connector pinout
  178. *
  179. * Connector STM32L4
  180. * pins pins
  181. *
  182. * 1 11 PG11 PH2
  183. * 2 12 PB6 PB2
  184. * 3 13 PG10 PA4
  185. * 4 14 PG12 PA0
  186. * 5 15 GND 5V
  187. * 6 16 5V GND
  188. * 7 17 PB8 PC7
  189. * 8 18 PI3 PC2
  190. * 9 19 PD3 PB12
  191. * 10 20 PB7 PC2
  192. *
  193. */
  194. #define STMOD_EN_PORT GPIOD_BASE
  195. #define STMOD_EN_PIN 3
  196. #define STMOD_SIM_SELECT0_PORT GPIOC_BASE
  197. #define STMOD_SIM_SELECT0_PIN 2
  198. #define STMOD_SIM_SELECT1_PORT GPIOI_BASE
  199. #define STMOD_SIM_SELECT1_PIN 3
  200. #define STMOD_MODEM_RST_PORT GPIOB_BASE
  201. #define STMOD_MODEM_RST_PIN 2
  202. #define STMOD_MODEM_DTR_PORT GPIOA_BASE
  203. #define STMOD_MODEM_DTR_PIN 0
  204. void stmod_modem_enable(void);
  205. void stmod_modem_disable(void);
  206. /* inline functions for GPIO */
  207. static inline void gpio_set(uint32_t port, uint32_t pin)
  208. {
  209. GPIO_BSSR(port) |= (1 << pin);
  210. }
  211. static inline void gpio_clear(uint32_t port, uint32_t pin)
  212. {
  213. GPIO_BSSR(port) |= (1 << (16 + pin));
  214. }
  215. /* Exported functions (from devices.c) */
  216. void clock_pll_on(void);
  217. int usart_init(uint32_t dev, uint32_t bitrate, uint8_t data, char parity, uint8_t stop);
  218. int usart_tx(uint32_t dev, const uint8_t c);
  219. int usart_rx(uint32_t dev, uint8_t *c);
  220. void systick_enable(void);
  221. void sleep_ms(unsigned ms);
  222. /* Assembly helpers */
  223. #define DMB() __asm__ volatile ("dmb")
  224. /* Nvic */
  225. #define NVIC_ISER_BASE (0xE000E100)
  226. #define NVIC_ICER_BASE (0xE000E180)
  227. #define NVIC_ICPR_BASE (0xE000E280)
  228. #define NVIC_IPRI_BASE (0xE000E400)
  229. static inline void nvic_irq_enable(uint8_t n)
  230. {
  231. int i = n / 32;
  232. volatile uint32_t *nvic_iser = ((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i));
  233. *nvic_iser |= (1 << (n % 32));
  234. }
  235. static inline void nvic_irq_disable(uint8_t n)
  236. {
  237. int i = n / 32;
  238. volatile uint32_t *nvic_icer = ((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i));
  239. *nvic_icer |= (1 << (n % 32));
  240. }
  241. static inline void nvic_irq_setprio(uint8_t n, uint8_t prio)
  242. {
  243. volatile uint8_t *nvic_ipri = ((volatile uint8_t *)(NVIC_IPRI_BASE + n));
  244. *nvic_ipri = prio;
  245. }
  246. static inline void nvic_irq_clear(uint8_t n)
  247. {
  248. int i = n / 32;
  249. volatile uint8_t *nvic_icpr = ((volatile uint8_t *)(NVIC_ICPR_BASE + 4 * i));
  250. *nvic_icpr = (1 << (n % 32));
  251. }
  252. #endif /* guard */