timer.c 15 KB

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  1. /*++
  2. Copyright (c) 2015 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. timer.c
  5. Abstract:
  6. This module implements platform timer services for the RK3288 SoC.
  7. Author:
  8. Evan Green 9-Jul-2015
  9. Environment:
  10. Firmware
  11. --*/
  12. //
  13. // ------------------------------------------------------------------- Includes
  14. //
  15. #include <uefifw.h>
  16. #include "veyronfw.h"
  17. //
  18. // --------------------------------------------------------------------- Macros
  19. //
  20. //
  21. // This macro reads from an RK32xx timer. _Base should be a pointer, and
  22. // _Register should be a RK32_TIMER_REGISTER value.
  23. //
  24. #define READ_TIMER_REGISTER(_Base, _Register) \
  25. EfiReadRegister32((_Base) + (_Register))
  26. //
  27. // This macro writes to an RK32xx timer. _Base should be a pointer,
  28. // _Register should be RK32_TIMER_REGISTER value, and _Value should be a 32-bit
  29. // integer.
  30. //
  31. #define WRITE_TIMER_REGISTER(_Base, _Register, _Value) \
  32. EfiWriteRegister32((_Base) + (_Register), (_Value))
  33. //
  34. // These macros read from and write to the watchdog timer.
  35. //
  36. #define RK32_READ_WATCHDOG(_Register) \
  37. EfiReadRegister32((VOID *)RK32_WATCHDOG_BASE + (_Register))
  38. #define RK32_WRITE_WATCHDOG(_Register, _Value) \
  39. EfiWriteRegister32((VOID *)RK32_WATCHDOG_BASE + (_Register), (_Value))
  40. //
  41. // ---------------------------------------------------------------- Definitions
  42. //
  43. //
  44. // Define the number of 24MHz clock ticks per interrupt. Shoot for 64
  45. // interrupts per second.
  46. //
  47. #define VEYRON_TIMER_TICK_COUNT (RK32_TIMER_FREQUENCY / 64)
  48. //
  49. // ------------------------------------------------------ Data Type Definitions
  50. //
  51. /*++
  52. Structure Description:
  53. This structure stores the internal state associated with an RK32xx timer.
  54. Members:
  55. Base - Stores the virtual address of the timer.
  56. CountDown - Stores a boolean indicating whether the timer counts down
  57. (TRUE) or up (FALSE).
  58. --*/
  59. typedef struct _RK32_TIMER_DATA {
  60. VOID *Base;
  61. BOOLEAN CountDown;
  62. } RK32_TIMER_DATA, *PRK32_TIMER_DATA;
  63. //
  64. // ----------------------------------------------- Internal Function Prototypes
  65. //
  66. VOID
  67. EfipPlatformServiceTimerInterrupt (
  68. UINT32 InterruptNumber
  69. );
  70. UINT64
  71. EfipPlatformReadTimer (
  72. VOID
  73. );
  74. VOID
  75. EfipRk32TimerInitialize (
  76. PRK32_TIMER_DATA Context
  77. );
  78. UINT64
  79. EfipRk32TimerRead (
  80. PRK32_TIMER_DATA Context
  81. );
  82. VOID
  83. EfipRk32TimerArm (
  84. PRK32_TIMER_DATA Context,
  85. BOOLEAN Periodic,
  86. UINT64 TickCount
  87. );
  88. VOID
  89. EfipRk32TimerDisarm (
  90. PRK32_TIMER_DATA Context
  91. );
  92. VOID
  93. EfipRk32TimerAcknowledgeInterrupt (
  94. PRK32_TIMER_DATA Context
  95. );
  96. EFI_STATUS
  97. EfipRk32QueryApbAlivePclkFrequency (
  98. UINT32 *Frequency
  99. );
  100. //
  101. // -------------------------------------------------------------------- Globals
  102. //
  103. RK32_TIMER_DATA EfiVeyronClockTimer;
  104. RK32_TIMER_DATA EfiVeyronTimeCounter;
  105. //
  106. // The watchdog timer runs on the APB Alive APB PCLK, whose frequency is
  107. // calculated from the general PLL.
  108. //
  109. UINT32 EfiRk32ApbAlivePclkFrequency = 0;
  110. //
  111. // ------------------------------------------------------------------ Functions
  112. //
  113. EFIAPI
  114. EFI_STATUS
  115. EfiPlatformSetWatchdogTimer (
  116. UINTN Timeout,
  117. UINT64 WatchdogCode,
  118. UINTN DataSize,
  119. CHAR16 *WatchdogData
  120. )
  121. /*++
  122. Routine Description:
  123. This routine sets the system's watchdog timer.
  124. Arguments:
  125. Timeout - Supplies the number of seconds to set the timer for.
  126. WatchdogCode - Supplies a numeric code to log on a watchdog timeout event.
  127. DataSize - Supplies the size of the watchdog data.
  128. WatchdogData - Supplies an optional buffer that includes a null-terminated
  129. string, optionally followed by additional binary data.
  130. Return Value:
  131. EFI_SUCCESS on success.
  132. EFI_INVALID_PARAMETER if the supplied watchdog code is invalid.
  133. EFI_UNSUPPORTED if there is no watchdog timer.
  134. EFI_DEVICE_ERROR if an error occurred accessing the device hardware.
  135. --*/
  136. {
  137. UINT32 Control;
  138. UINT32 CurrentCount;
  139. UINT64 DesiredCount;
  140. UINT32 Frequency;
  141. UINT32 RangeIndex;
  142. EFI_STATUS Status;
  143. //
  144. // Query the APB Alive PCLK frequency if necessary.
  145. //
  146. if (EfiRk32ApbAlivePclkFrequency == 0) {
  147. Status = EfipRk32QueryApbAlivePclkFrequency(&Frequency);
  148. if (EFI_ERROR(Status)) {
  149. return Status;
  150. }
  151. EfiRk32ApbAlivePclkFrequency = Frequency;
  152. }
  153. DesiredCount = (Timeout * EfiRk32ApbAlivePclkFrequency);
  154. if (DesiredCount > RK32_WATCHDOG_MAX) {
  155. DesiredCount = RK32_WATCHDOG_MAX;
  156. }
  157. //
  158. // First, disable the watchdog timer.
  159. //
  160. Control = RK32_READ_WATCHDOG(Rk32WatchdogControl);
  161. Control &= ~RK32_WATCHDOG_CONTROL_ENABLE;
  162. RK32_WRITE_WATCHDOG(Rk32WatchdogControl, Control);
  163. //
  164. // If the watchdog timer is being enabled, set the count value and fire it
  165. // back up.
  166. //
  167. if ((DesiredCount != 0) && (EfiDisableWatchdog == FALSE)) {
  168. //
  169. // Figure out the proper range index for the requested count. The
  170. // allowable ranges go 0x0000FFFF, 0x0001FFFF, 0x0003FFFF, 0x0007FFFF,
  171. // 0x000FFFFF, etc all the way up to 0x7FFFFFFF.
  172. //
  173. RangeIndex = 0;
  174. CurrentCount = RK32_WATCHDOG_MIN;
  175. while (CurrentCount < DesiredCount) {
  176. RangeIndex += 1;
  177. CurrentCount = (CurrentCount << 1) | 0x1;
  178. }
  179. RK32_WRITE_WATCHDOG(Rk32WatchdogTimeoutRange, RangeIndex);
  180. //
  181. // Restart the counter. The TRM cruelly refers to this as "kicking the
  182. // dog".
  183. //
  184. RK32_WRITE_WATCHDOG(Rk32WatchdogCounterRestart,
  185. RK32_WATCHDOG_RESTART_VALUE);
  186. //
  187. // Enable the watchdog.
  188. //
  189. Control |= RK32_WATCHDOG_CONTROL_ENABLE;
  190. Control &= ~RK32_WATCHDOG_CONTROL_BARK_FIRST;
  191. RK32_WRITE_WATCHDOG(Rk32WatchdogControl, Control);
  192. }
  193. return EFI_SUCCESS;
  194. }
  195. EFI_STATUS
  196. EfiPlatformInitializeTimers (
  197. UINT32 *ClockTimerInterruptNumber,
  198. EFI_PLATFORM_SERVICE_TIMER_INTERRUPT *ClockTimerServiceRoutine,
  199. EFI_PLATFORM_READ_TIMER *ReadTimerRoutine,
  200. UINT64 *ReadTimerFrequency,
  201. UINT32 *ReadTimerWidth
  202. )
  203. /*++
  204. Routine Description:
  205. This routine initializes platform timer services. There are actually two
  206. different timer services returned in this routine. The periodic timer tick
  207. provides a periodic interrupt. The read timer provides a free running
  208. counter value. These are likely serviced by different timers. For the
  209. periodic timer tick, this routine should start the periodic interrupts
  210. coming in. The periodic rate of the timer can be anything reasonable, as
  211. the time counter will be used to count actual duration. The rate should be
  212. greater than twice the rollover rate of the time counter to ensure proper
  213. time accounting. Interrupts are disabled at the processor core for the
  214. duration of this routine.
  215. Arguments:
  216. ClockTimerInterruptNumber - Supplies a pointer where the interrupt line
  217. number of the periodic timer tick will be returned.
  218. ClockTimerServiceRoutine - Supplies a pointer where a pointer to a routine
  219. called when the periodic timer tick interrupt occurs will be returned.
  220. ReadTimerRoutine - Supplies a pointer where a pointer to a routine
  221. called to read the current timer value will be returned.
  222. ReadTimerFrequency - Supplies the frequency of the counter.
  223. ReadTimerWidth - Supplies a pointer where the read timer bit width will be
  224. returned.
  225. Return Value:
  226. EFI Status code.
  227. --*/
  228. {
  229. EFI_STATUS Status;
  230. *ClockTimerInterruptNumber = RK32_INTERRUPT_TIMER0;
  231. *ClockTimerServiceRoutine = EfipPlatformServiceTimerInterrupt;
  232. *ReadTimerRoutine = EfipPlatformReadTimer;
  233. *ReadTimerFrequency = RK32_TIMER_FREQUENCY;
  234. *ReadTimerWidth = 64;
  235. //
  236. // Use timer 0 for the clock timer and timer 1 for the time counter. Both
  237. // run at 24MHz, and both count down.
  238. //
  239. EfiVeyronClockTimer.Base = (VOID *)(RK32_TIMER0_5_BASE +
  240. (0 * RK32_TIMER_REGISTER_STRIDE));
  241. EfiVeyronClockTimer.CountDown = TRUE;
  242. EfiVeyronTimeCounter.Base = (VOID *)(RK32_TIMER0_5_BASE +
  243. (1 * RK32_TIMER_REGISTER_STRIDE));
  244. EfiVeyronTimeCounter.CountDown = TRUE;
  245. EfipRk32TimerInitialize(&EfiVeyronClockTimer);
  246. EfipRk32TimerArm(&EfiVeyronClockTimer, TRUE, VEYRON_TIMER_TICK_COUNT);
  247. EfipRk32TimerInitialize(&EfiVeyronTimeCounter);
  248. Status = EfipPlatformSetInterruptLineState(*ClockTimerInterruptNumber,
  249. TRUE,
  250. FALSE);
  251. return Status;
  252. }
  253. VOID
  254. EfiPlatformTerminateTimers (
  255. VOID
  256. )
  257. /*++
  258. Routine Description:
  259. This routine terminates timer services in preparation for the termination
  260. of boot services.
  261. Arguments:
  262. None.
  263. Return Value:
  264. None.
  265. --*/
  266. {
  267. EfipRk32TimerDisarm(&EfiVeyronClockTimer);
  268. return;
  269. }
  270. //
  271. // --------------------------------------------------------- Internal Functions
  272. //
  273. VOID
  274. EfipPlatformServiceTimerInterrupt (
  275. UINT32 InterruptNumber
  276. )
  277. /*++
  278. Routine Description:
  279. This routine is called to acknowledge a platform timer interrupt. This
  280. routine is responsible for quiescing the interrupt.
  281. Arguments:
  282. InterruptNumber - Supplies the interrupt number that occurred.
  283. Return Value:
  284. None.
  285. --*/
  286. {
  287. EfipRk32TimerAcknowledgeInterrupt(&EfiVeyronClockTimer);
  288. return;
  289. }
  290. UINT64
  291. EfipPlatformReadTimer (
  292. VOID
  293. )
  294. /*++
  295. Routine Description:
  296. This routine is called to read the current platform time value. The timer
  297. is assumed to be free running at a constant frequency, and should have a
  298. bit width as reported in the initialize function. The UEFI core will
  299. manage software bit extension out to 64 bits, this routine should just
  300. reporte the hardware timer value.
  301. Arguments:
  302. None.
  303. Return Value:
  304. Returns the hardware timer value.
  305. --*/
  306. {
  307. return EfipRk32TimerRead(&EfiVeyronTimeCounter);
  308. }
  309. VOID
  310. EfipRk32TimerInitialize (
  311. PRK32_TIMER_DATA Context
  312. )
  313. /*++
  314. Routine Description:
  315. This routine initializes an RK32xx timer.
  316. Arguments:
  317. Context - Supplies the pointer to the timer's context.
  318. Return Value:
  319. None.
  320. --*/
  321. {
  322. if (Context->Base == NULL) {
  323. return;
  324. }
  325. //
  326. // Program the timer in free running mode with no interrupt.
  327. //
  328. WRITE_TIMER_REGISTER(Context->Base,
  329. Rk32TimerControl,
  330. RK32_TIMER_CONTROL_ENABLE);
  331. //
  332. // Set the load count register to the maximum period.
  333. //
  334. WRITE_TIMER_REGISTER(Context->Base,
  335. Rk32TimerLoadCountHigh,
  336. 0xFFFFFFFF);
  337. WRITE_TIMER_REGISTER(Context->Base,
  338. Rk32TimerLoadCountLow,
  339. 0xFFFFFFFF);
  340. //
  341. // Clear any previously pending interrupts.
  342. //
  343. WRITE_TIMER_REGISTER(Context->Base, Rk32TimerInterruptStatus, 1);
  344. return;
  345. }
  346. UINT64
  347. EfipRk32TimerRead (
  348. PRK32_TIMER_DATA Context
  349. )
  350. /*++
  351. Routine Description:
  352. This routine returns the hardware counter's raw value.
  353. Arguments:
  354. Context - Supplies the pointer to the timer's context.
  355. Return Value:
  356. Returns the timer's current count.
  357. --*/
  358. {
  359. UINT32 High1;
  360. UINT32 High2;
  361. UINT32 Low;
  362. UINT64 Value;
  363. //
  364. // Do a high-low-high read to make sure sure the words didn't tear.
  365. //
  366. do {
  367. High1 = READ_TIMER_REGISTER(Context->Base, Rk32TimerCurrentValueHigh);
  368. Low = READ_TIMER_REGISTER(Context->Base, Rk32TimerCurrentValueLow);
  369. High2 = READ_TIMER_REGISTER(Context->Base, Rk32TimerCurrentValueHigh);
  370. } while (High1 != High2);
  371. Value = (((UINT64)High1) << 32) | Low;
  372. if (Context->CountDown != FALSE) {
  373. Value = ~Value;
  374. }
  375. return Value;
  376. }
  377. VOID
  378. EfipRk32TimerArm (
  379. PRK32_TIMER_DATA Context,
  380. BOOLEAN Periodic,
  381. UINT64 TickCount
  382. )
  383. /*++
  384. Routine Description:
  385. This routine arms the timer to fire an interrupt after the specified number
  386. of ticks.
  387. Arguments:
  388. Context - Supplies the pointer to the timer's context.
  389. Periodic - Supplies a boolean indicating if the timer should be armed
  390. periodically or one-shot.
  391. TickCount - Supplies the interval, in ticks, from now for the timer to fire
  392. in.
  393. Return Value:
  394. None.
  395. --*/
  396. {
  397. UINT32 Control;
  398. if (Context->CountDown == FALSE) {
  399. TickCount = 0 - TickCount;
  400. }
  401. //
  402. // Stop the timer before programming it, as demanded by the TRM.
  403. //
  404. WRITE_TIMER_REGISTER(Context->Base, Rk32TimerControl, 0);
  405. //
  406. // Program the new tick count.
  407. //
  408. WRITE_TIMER_REGISTER(Context->Base,
  409. Rk32TimerLoadCountHigh,
  410. TickCount >> 32);
  411. WRITE_TIMER_REGISTER(Context->Base, Rk32TimerLoadCountLow, TickCount);
  412. Control = RK32_TIMER_CONTROL_ENABLE | RK32_TIMER_CONTROL_INTERRUPT_ENABLE;
  413. if (Periodic == FALSE) {
  414. Control |= RK32_TIMER_CONTROL_ONE_SHOT;
  415. }
  416. WRITE_TIMER_REGISTER(Context->Base, Rk32TimerControl, Control);
  417. return;
  418. }
  419. VOID
  420. EfipRk32TimerDisarm (
  421. PRK32_TIMER_DATA Context
  422. )
  423. /*++
  424. Routine Description:
  425. This routine disarms the timer, stopping interrupts from firing.
  426. Arguments:
  427. Context - Supplies the pointer to the timer's context.
  428. Return Value:
  429. None.
  430. --*/
  431. {
  432. //
  433. // Just stop the timer completely.
  434. //
  435. WRITE_TIMER_REGISTER(Context->Base, Rk32TimerControl, 0);
  436. return;
  437. }
  438. VOID
  439. EfipRk32TimerAcknowledgeInterrupt (
  440. PRK32_TIMER_DATA Context
  441. )
  442. /*++
  443. Routine Description:
  444. This routine performs any actions necessary upon reciept of a timer's
  445. interrupt. This may involve writing to an acknowledge register to re-enable
  446. the timer to fire again, or other hardware specific actions.
  447. Arguments:
  448. Context - Supplies the pointer to the timer's context.
  449. Return Value:
  450. None.
  451. --*/
  452. {
  453. WRITE_TIMER_REGISTER(Context->Base, Rk32TimerInterruptStatus, 1);
  454. return;
  455. }
  456. EFI_STATUS
  457. EfipRk32QueryApbAlivePclkFrequency (
  458. UINT32 *Frequency
  459. )
  460. /*++
  461. Routine Description:
  462. This routine queries the APB Alive PCLK frequency.
  463. Arguments:
  464. Frequency - Supplies a pointer that receives the current frequency.
  465. Return Value:
  466. Status code.
  467. --*/
  468. {
  469. UINT32 Divisor;
  470. UINT32 GeneralPllFrequency;
  471. EFI_STATUS Status;
  472. UINT32 Value;
  473. //
  474. // The APB Alive PCLK timer is taken from the General PLL and divided by
  475. // the value stored in clock select register 33.
  476. //
  477. Status = EfipRk32GetPllClockFrequency(Rk32PllGeneral, &GeneralPllFrequency);
  478. if (EFI_ERROR(Status)) {
  479. return Status;
  480. }
  481. Value = EfiReadRegister32((VOID *)RK32_CRU_BASE + Rk32CruClockSelect33);
  482. Divisor = (Value & RK32_CRU_CLOCK_SELECT33_ALIVE_PCLK_DIVIDER_MASK) >>
  483. RK32_CRU_CLOCK_SELECT33_ALIVE_PCLK_DIVIDER_SHIFT;
  484. *Frequency = GeneralPllFrequency / (Divisor + 1);
  485. return EFI_SUCCESS;
  486. }