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@@ -0,0 +1,116 @@
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+typedef struct Mii Mii;
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+typedef struct MiiPhy MiiPhy;
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+
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+enum { /* registers */
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+ Bmcr = 0x00, /* Basic Mode Control */
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+ Bmsr = 0x01, /* Basic Mode Status */
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+ Phyidr1 = 0x02, /* PHY Identifier #1 */
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+ Phyidr2 = 0x03, /* PHY Identifier #2 */
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+ Anar = 0x04, /* Auto-Negotiation Advertisement */
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+ Anlpar = 0x05, /* AN Link Partner Ability */
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+ Aner = 0x06, /* AN Expansion */
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+ Annptr = 0x07, /* AN Next Page TX */
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+ Annprr = 0x08, /* AN Next Page RX */
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+ Mscr = 0x09, /* MASTER-SLAVE Control */
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+ Mssr = 0x0A, /* MASTER-SLAVE Status */
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+ Esr = 0x0F, /* Extended Status */
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+
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+ NMiiPhyr = 32,
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+ NMiiPhy = 32,
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+};
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+
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+enum { /* Bmcr */
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+ BmcrSs1 = 0x0040, /* Speed Select[1] */
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+ BmcrCte = 0x0080, /* Collision Test Enable */
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+ BmcrDm = 0x0100, /* Duplex Mode */
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+ BmcrRan = 0x0200, /* Restart Auto-Negotiation */
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+ BmcrI = 0x0400, /* Isolate */
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+ BmcrPd = 0x0800, /* Power Down */
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+ BmcrAne = 0x1000, /* Auto-Negotiation Enable */
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+ BmcrSs0 = 0x2000, /* Speed Select[0] */
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+ BmcrLe = 0x4000, /* Loopback Enable */
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+ BmcrR = 0x8000, /* Reset */
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+};
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+
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+enum { /* Bmsr */
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+ BmsrEc = 0x0001, /* Extended Capability */
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+ BmsrJd = 0x0002, /* Jabber Detect */
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+ BmsrLs = 0x0004, /* Link Status */
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+ BmsrAna = 0x0008, /* Auto-Negotiation Ability */
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+ BmsrRf = 0x0010, /* Remote Fault */
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+ BmsrAnc = 0x0020, /* Auto-Negotiation Complete */
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+ BmsrPs = 0x0040, /* Preamble Suppression Capable */
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+ BmsrEs = 0x0100, /* Extended Status */
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+ Bmsr100T2HD = 0x0200, /* 100BASE-T2 HD Capable */
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+ Bmsr100T2FD = 0x0400, /* 100BASE-T2 FD Capable */
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+ Bmsr10THD = 0x0800, /* 100BASE-T HD Capable */
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+ Bmsr10TFD = 0x1000, /* 10BASE-T FD Capable */
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+ Bmsr100TXHD = 0x2000, /* 100BASE-TX HD Capable */
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+ Bmsr100TXFD = 0x4000, /* 100BASE-TX FD Capable */
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+ Bmsr100T4 = 0x8000, /* 100BASE-T4 Capable */
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+};
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+
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+enum { /* Anar/Anlpar */
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+ Ana10HD = 0x0020, /* Advertise 10BASE-T */
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+ Ana10FD = 0x0040, /* Advertise 10BASE-T FD */
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+ AnaTXHD = 0x0080, /* Advertise 100BASE-TX */
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+ AnaTXFD = 0x0100, /* Advertise 100BASE-TX FD */
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+ AnaT4 = 0x0200, /* Advertise 100BASE-T4 */
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+ AnaP = 0x0400, /* Pause */
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+ AnaAP = 0x0800, /* Asymmetrical Pause */
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+ AnaRf = 0x2000, /* Remote Fault */
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+ AnaAck = 0x4000, /* Acknowledge */
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+ AnaNp = 0x8000, /* Next Page Indication */
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+};
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+
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+enum { /* Mscr */
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+ Mscr1000THD = 0x0100, /* Advertise 1000BASE-T HD */
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+ Mscr1000TFD = 0x0200, /* Advertise 1000BASE-T FD */
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+};
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+
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+enum { /* Mssr */
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+ Mssr1000THD = 0x0400, /* Link Partner 1000BASE-T HD able */
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+ Mssr1000TFD = 0x0800, /* Link Partner 1000BASE-T FD able */
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+};
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+
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+enum { /* Esr */
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+ Esr1000THD = 0x1000, /* 1000BASE-T HD Capable */
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+ Esr1000TFD = 0x2000, /* 1000BASE-T FD Capable */
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+ Esr1000XHD = 0x4000, /* 1000BASE-X HD Capable */
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+ Esr1000XFD = 0x8000, /* 1000BASE-X FD Capable */
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+};
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+
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+typedef struct Mii {
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+ Lock;
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+ int nphy;
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+ int mask;
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+ MiiPhy* phy[NMiiPhy];
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+ MiiPhy* curphy;
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+
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+ void* ctlr;
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+ int (*mir)(Mii*, int, int);
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+ int (*miw)(Mii*, int, int, int);
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+} Mii;
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+
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+typedef struct MiiPhy {
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+ Mii* mii;
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+ int oui;
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+ int phyno;
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+
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+ int anar;
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+ int fc;
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+ int mscr;
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+
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+ int link;
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+ int speed;
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+ int fd;
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+ int rfc;
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+ int tfc;
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+};
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+
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+extern int mii(Mii*, int);
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+extern int miiane(Mii*, int, int, int);
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+extern int miimir(Mii*, int);
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+extern int miimiw(Mii*, int, int);
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+extern int miireset(Mii*);
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+extern int miistatus(Mii*);
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