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@@ -15,20 +15,20 @@
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#define BI2BY 8 /* bits per byte */
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#define BI2WD 32 /* bits per word */
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#define BY2WD 4 /* bytes per word */
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-#define BY2V 8 /* bytes per vlong */
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-#define BY2PG 4096 /* bytes per page */
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-#define WD2PG (BY2PG/BY2WD) /* words per page */
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+#define BY2V 8 /* bytes per vlong */
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+#define BY2PG 4096 /* bytes per page */
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+#define WD2PG (BY2PG/BY2WD) /* words per page */
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#define PGSHIFT 12 /* log(BY2PG) */
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-#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
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-#define PGROUND(s) ROUND(s, BY2PG)
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+#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
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+#define PGROUND(s) ROUND(s, BY2PG)
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#define CACHELINELOG 5
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#define CACHELINESZ (1<<CACHELINELOG)
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#define BLOCKALIGN CACHELINESZ
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-#define MHz 1000000
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+#define MHz 1000000
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-#define BY2PTE 8 /* bytes per pte entry */
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-#define BY2PTEG 64 /* bytes per pte group */
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+#define BY2PTE 8 /* bytes per pte entry */
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+#define BY2PTEG 64 /* bytes per pte group */
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#define MAXMACH 1 /* max # cpus system can run */
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#define MACHSIZE BY2PG
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@@ -77,11 +77,11 @@
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/*
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* PPC604e-specific Special Purpose Registers (OEA)
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*/
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-#define MMCR0 952 /* Monitor Control Register 0 */
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+#define MMCR0 952 /* Monitor Control Register 0 */
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#define PMC1 953 /* Performance Monitor Counter 1 */
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#define PMC2 954 /* Performance Monitor Counter 2 */
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#define SIA 955 /* Sampled Instruction Address */
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-#define MMCR1 956 /* Monitor Control Register 0 */
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+#define MMCR1 956 /* Monitor Control Register 0 */
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#define PMC3 957 /* Performance Monitor Counter 3 */
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#define PMC4 958 /* Performance Monitor Counter 4 */
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#define SDA 959 /* Sampled Data Address */
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@@ -102,15 +102,15 @@
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*/
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#define HID2 1011 /* Hardware Implementation Dependent Register 2 */
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-#define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */
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-#define SBIT(n) ((ushort)1<<(15-(n)))
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+#define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */
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+#define SBIT(n) ((ushort)1<<(15-(n)))
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#define RBIT(b,n) (1<<(8*sizeof(n)-1-(b)))
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/*
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* Bit encodings for Machine State Register (MSR)
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*/
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#define MSR_POW BIT(13) /* Enable Power Management */
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-#define MSR_TGPR BIT(14) /* Temporary GPR Registers in use (603e) */
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+#define MSR_TGPR BIT(14) /* Temporary GPR Registers in use (603e) */
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#define MSR_ILE BIT(15) /* Interrupt Little-Endian enable */
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#define MSR_EE BIT(16) /* External Interrupt enable */
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#define MSR_PR BIT(17) /* Supervisor/User privilege */
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@@ -129,9 +129,9 @@
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/* SRR1 bits for TLB operations */
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#define MSR_SR0 0xf0000000 /* Saved bits from CR register */
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#define MSR_KEY BIT(12) /* Copy of Ks or Kp bit */
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-#define MSR_IMISS BIT(13) /* It was an I miss */
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+#define MSR_IMISS BIT(13) /* It was an I miss */
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#define MSR_WAY BIT(14) /* TLB set to be replaced */
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-#define MSR_STORE BIT(15) /* Miss caused by a store */
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+#define MSR_STORE BIT(15) /* Miss caused by a store */
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/*
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* Exception codes (trap vectors)
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@@ -141,27 +141,27 @@
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#define CDSI 0x03
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#define CISI 0x04
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#define CEI 0x05
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-#define CALIGN 0x06
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+#define CALIGN 0x06
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#define CPROG 0x07
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#define CFPU 0x08
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#define CDEC 0x09
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#define CSYSCALL 0x0C
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-#define CTRACE 0x0D /* optional */
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-#define CFPA 0x0E /* not implemented in 603e */
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+#define CTRACE 0x0D /* optional */
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+#define CFPA 0x0E /* not implemented in 603e */
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/* PPC603e-specific: */
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#define CIMISS 0x10 /* Instruction TLB miss */
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-#define CLMISS 0x11 /* Data load TLB miss */
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-#define CSMISS 0x12 /* Data store TLB miss */
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-#define CIBREAK 0x13
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+#define CLMISS 0x11 /* Data load TLB miss */
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+#define CSMISS 0x12 /* Data store TLB miss */
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+#define CIBREAK 0x13
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#define CSMI 0x14
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/*
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* Magic registers
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*/
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-#define MACH 30 /* R30 is m-> */
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-#define USER 29 /* R29 is up-> */
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+#define MACH 30 /* R30 is m-> */
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+#define USER 29 /* R29 is up-> */
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/*
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@@ -181,25 +181,25 @@
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/*
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* Second pte word; WIMG & PP(RW/RO) common to page table and BATs
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*/
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-#define PTE1_R BIT(23)
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-#define PTE1_C BIT(24)
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+#define PTE1_R BIT(23)
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+#define PTE1_C BIT(24)
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-#define PTE1_W BIT(25)
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-#define PTE1_I BIT(26)
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-#define PTE1_M BIT(27)
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-#define PTE1_G BIT(28)
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+#define PTE1_W BIT(25)
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+#define PTE1_I BIT(26)
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+#define PTE1_M BIT(27)
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+#define PTE1_G BIT(28)
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-#define PTE1_RW BIT(30)
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-#define PTE1_RO BIT(31)
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+#define PTE1_RW BIT(30)
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+#define PTE1_RO BIT(31)
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/* HID0 register bits */
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#define HID_ICE BIT(16)
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#define HID_DCE BIT(17)
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#define HID_ILOCK BIT(18)
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#define HID_DLOCK BIT(19)
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-#define HID_ICFI BIT(20)
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-#define HID_DCFI BIT(21)
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-#define HID_IFEM BIT(24)
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+#define HID_ICFI BIT(20)
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+#define HID_DCFI BIT(21)
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+#define HID_IFEM BIT(24)
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/*
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* Address spaces
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@@ -207,16 +207,16 @@
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#define KZERO 0x80000000 /* base of kernel address space */
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#define KTZERO 0x80100000 /* first address in kernel text */
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-#define UZERO 0 /* base of user address space */
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-#define UTZERO (UZERO+BY2PG) /* first address in user text */
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+#define UZERO 0 /* base of user address space */
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+#define UTZERO (UZERO+BY2PG) /* first address in user text */
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#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
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#define TSTKTOP KZERO /* top of temporary stack */
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#define TSTKSIZ 100
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-#define USTKSIZE (4*1024*1024) /* size of user stack */
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-#define UREGSIZE ((8+40)*4)
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+#define USTKSIZE (4*1024*1024) /* size of user stack */
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+#define UREGSIZE ((8+40)*4)
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#define MACHADDR (KTZERO-MAXMACH*MACHSIZE)
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#define MACHPADDR (MACHADDR&~KZERO)
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-#define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE))
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+#define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE))
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#define isphys(x) (((ulong)x&KZERO)!=0)
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