Browse Source

End use of m->externup everywhere.
Declare up at top of function as Proc *up = machp()->externup;
Fix the places it is assigned
Converted the 500 error cases by sed and hand-editing.
Since we're touching everything, decided to clean up some white spaces too.

Change-Id: I62478889af307f4a2695adb5c4972f5c5b579acc
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Ronald G. Minnich 4 years ago
parent
commit
23298ed0ad
100 changed files with 1172 additions and 1134 deletions
  1. 1 1
      sys/src/9/386/aoe.h
  2. 3 3
      sys/src/9/386/devether.c
  3. 12 12
      sys/src/9/386/devrtc.c
  4. 1 1
      sys/src/9/386/ether8169.c
  5. 11 11
      sys/src/9/386/ether82557.c
  6. 2 2
      sys/src/9/386/ether82563.c
  7. 2 2
      sys/src/9/386/etherigbe.c
  8. 11 11
      sys/src/9/386/etherm10g.c
  9. 11 11
      sys/src/9/386/pci.c
  10. 8 8
      sys/src/9/386/random.c
  11. 6 15
      sys/src/9/386/sdiahci.c
  12. 4 4
      sys/src/9/386/uarti8250.c
  13. 20 20
      sys/src/9/amd64pv/acore.c
  14. 3 3
      sys/src/9/amd64pv/acpi.h
  15. 3 3
      sys/src/9/amd64pv/amd64.h
  16. 6 6
      sys/src/9/amd64pv/apic.c
  17. 1 1
      sys/src/9/amd64pv/apic.h
  18. 6 6
      sys/src/9/amd64pv/arch.c
  19. 20 20
      sys/src/9/amd64pv/archk10.c
  20. 5 5
      sys/src/9/amd64pv/asm.c
  21. 1 1
      sys/src/9/amd64pv/backtrace.c
  22. 3 3
      sys/src/9/amd64pv/dat.h
  23. 9 9
      sys/src/9/amd64pv/devacpi.c
  24. 6 6
      sys/src/9/amd64pv/devarch.c
  25. 18 18
      sys/src/9/amd64pv/devusb.c
  26. 10 10
      sys/src/9/amd64pv/entry.S
  27. 1 1
      sys/src/9/amd64pv/ether8139.c
  28. 7 7
      sys/src/9/amd64pv/ether82563.c
  29. 1 1
      sys/src/9/amd64pv/etherif.h
  30. 1 1
      sys/src/9/amd64pv/fns.h
  31. 44 44
      sys/src/9/amd64pv/fpu.c
  32. 1 1
      sys/src/9/amd64pv/io.h
  33. 1 1
      sys/src/9/amd64pv/ioapic.c
  34. 1 1
      sys/src/9/amd64pv/iob.h
  35. 1 1
      sys/src/9/amd64pv/l64acidt.S
  36. 7 7
      sys/src/9/amd64pv/l64idt.S
  37. 5 5
      sys/src/9/amd64pv/l64vsyscall.S
  38. 42 42
      sys/src/9/amd64pv/main.c
  39. 1 1
      sys/src/9/amd64pv/mem.h
  40. 72 72
      sys/src/9/amd64pv/mmu.c
  41. 1 1
      sys/src/9/amd64pv/physalloc.c
  42. 14 14
      sys/src/9/amd64pv/pmcio.c
  43. 5 5
      sys/src/9/amd64pv/qmalloc.c
  44. 99 99
      sys/src/9/amd64pv/syscall.c
  45. 51 51
      sys/src/9/amd64pv/tcore.c
  46. 54 54
      sys/src/9/amd64pv/trap.c
  47. 19 19
      sys/src/9/amd64pv/usbohci.c
  48. 22 22
      sys/src/9/amd64pv/usbuhci.c
  49. 2 2
      sys/src/9/amd64pv/vsvm.c
  50. 1 1
      sys/src/9/boot/boot.c
  51. 1 1
      sys/src/9/boot/boot.h
  52. 3 3
      sys/src/9/ip/arp.c
  53. 1 1
      sys/src/9/ip/chandial.c
  54. 11 11
      sys/src/9/ip/devip.c
  55. 3 3
      sys/src/9/ip/esp.c
  56. 9 9
      sys/src/9/ip/ethermedium.c
  57. 4 4
      sys/src/9/ip/inferno.c
  58. 1 1
      sys/src/9/ip/ip.c
  59. 6 6
      sys/src/9/ip/ipifc.c
  60. 1 1
      sys/src/9/ip/iproute.c
  61. 1 1
      sys/src/9/ip/ipv6.c
  62. 4 4
      sys/src/9/ip/loopbackmedium.c
  63. 4 4
      sys/src/9/ip/netdevmedium.c
  64. 4 4
      sys/src/9/ip/netlog.c
  65. 3 3
      sys/src/9/ip/rudp.c
  66. 8 8
      sys/src/9/ip/tcp.c
  67. 27 27
      sys/src/9/k10/acore.c
  68. 8 8
      sys/src/9/k10/acore.c.old
  69. 3 3
      sys/src/9/k10/acpi.h
  70. 13 13
      sys/src/9/k10/apic.c
  71. 1 1
      sys/src/9/k10/apic.h
  72. 6 6
      sys/src/9/k10/arch.c
  73. 42 42
      sys/src/9/k10/archk10.c
  74. 6 6
      sys/src/9/k10/asm.c
  75. 1 1
      sys/src/9/k10/backtrace.c
  76. 34 0
      sys/src/9/k10/cga.c
  77. 3 3
      sys/src/9/k10/dat.h
  78. 10 9
      sys/src/9/k10/devacpi.c
  79. 13 12
      sys/src/9/k10/devarch.c
  80. 18 18
      sys/src/9/k10/devusb.c
  81. 10 10
      sys/src/9/k10/entry.S
  82. 1 1
      sys/src/9/k10/ether8139.c
  83. 7 7
      sys/src/9/k10/ether82563.c
  84. 1 1
      sys/src/9/k10/etherif.h
  85. 3 1
      sys/src/9/k10/fns.h
  86. 50 50
      sys/src/9/k10/fpu.c
  87. 1 1
      sys/src/9/k10/fpu.c.old
  88. 1 1
      sys/src/9/k10/io.h
  89. 1 1
      sys/src/9/k10/ioapic.c
  90. 1 1
      sys/src/9/k10/iob.h
  91. 1 1
      sys/src/9/k10/l64acidt.S
  92. 7 7
      sys/src/9/k10/l64idt.S
  93. 5 5
      sys/src/9/k10/l64vsyscall.S
  94. 102 93
      sys/src/9/k10/main.c
  95. 1 1
      sys/src/9/k10/mem.h
  96. 75 75
      sys/src/9/k10/mmu.c
  97. 1 1
      sys/src/9/k10/physalloc.c
  98. 14 14
      sys/src/9/k10/pmcio.c
  99. 5 5
      sys/src/9/k10/qmalloc.c
  100. 0 0
      sys/src/9/k10/sdata.c

+ 1 - 1
sys/src/9/386/aoe.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No

+ 3 - 3
sys/src/9/386/devether.c

@@ -23,7 +23,7 @@ static Ether *etherxx[MaxEther];
 Chan*
 etherattach(char* spec)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t ctlrno;
 	char *p;
 	Chan *chan;
@@ -253,7 +253,7 @@ etheroq(Ether* ether, Block* bp)
 static int32_t
 etherwrite(Chan* chan, void* buf, int32_t n, int64_t mm)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Ether *ether;
 	Block *bp;
 	int nn, onoff;
@@ -303,7 +303,7 @@ etherwrite(Chan* chan, void* buf, int32_t n, int64_t mm)
 static int32_t
 etherbwrite(Chan* chan, Block* bp, int64_t mm)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Ether *ether;
 	int32_t n;
 

+ 12 - 12
sys/src/9/386/devrtc.c

@@ -76,13 +76,13 @@ rtcattach(char* spec)
 	return devattach('r', spec);
 }
 
-static Walkqid*	 
+static Walkqid*
 rtcwalk(Chan* c, Chan *nc, char** name, int nname)
 {
 	return devwalk(c, nc, name, nname, rtcdir, nelem(rtcdir), devgen);
 }
 
-static int32_t	 
+static int32_t
 rtcstat(Chan* c, uint8_t* dp, int32_t n)
 {
 	return devstat(c, dp, n, rtcdir, nelem(rtcdir), devgen);
@@ -91,28 +91,28 @@ rtcstat(Chan* c, uint8_t* dp, int32_t n)
 static Chan*
 rtcopen(Chan* c, int omode)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	omode = openmode(omode);
 	switch((uint32_t)c->qid.path){
 	case Qrtc:
-		if(strcmp(m->externup->user, eve)!=0 && omode!=OREAD)
+		if(strcmp(up->user, eve)!=0 && omode!=OREAD)
 			error(Eperm);
 		break;
 	case Qnvram:
-		if(strcmp(m->externup->user, eve)!=0)
+		if(strcmp(up->user, eve)!=0)
 			error(Eperm);
 	}
 	return devopen(c, omode, rtcdir, nelem(rtcdir), devgen);
 }
 
-static void	 
+static void
 rtcclose(Chan* c)
 {
 }
 
 #define GETBCD(o) ((bcdclock[o]&0xf) + 10*(bcdclock[o]>>4))
 
-static int32_t	 
+static int32_t
 rtcextract(void)
 {
 	uint8_t bcdclock[Nbcd];
@@ -182,10 +182,10 @@ rtctime(void)
 	return t;
 }
 
-static int32_t	 
+static int32_t
 rtcread(Chan* c, void* buf, int32_t n, int64_t off)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t t;
 	char *a, *start;
 	uint32_t offset = off;
@@ -230,10 +230,10 @@ rtcread(Chan* c, void* buf, int32_t n, int64_t off)
 
 #define PUTBCD(n,o) bcdclock[o] = (n % 10) | (((n / 10) % 10)<<4)
 
-static int32_t	 
+static int32_t
 rtcwrite(Chan* c, void* buf, int32_t n, int64_t off)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int t;
 	char *a, *start;
 	Rtc rtc;
@@ -288,7 +288,7 @@ rtcwrite(Chan* c, void* buf, int32_t n, int64_t off)
 			return 0;
 		if(n > Nvsize)
 			n = Nvsize;
-	
+
 		start = a = smalloc(n);
 		if(waserror()){
 			free(start);

+ 1 - 1
sys/src/9/386/ether8169.c

@@ -508,7 +508,7 @@ rtl8169multicast(void* ether, unsigned char *eaddr, int add)
 static int32_t
 rtl8169ifstat(Ether* edev, void* a, int32_t n, uint32_t offset)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char *p, *s, *e;
 	Ctlr *ctlr;
 	Dtcc *dtcc;

+ 11 - 11
sys/src/9/386/ether82557.c

@@ -249,15 +249,15 @@ static uint8_t configdata[24] = {
 	0x03,				/* discard short Rx frames */
 	0x00,				/* 503/MII */
 
-	0x00,	
+	0x00,
 	0x2E,				/* normal operation, NSAI */
 	0x00,				/* linear priority */
 	0x60,				/* inter-frame spacing */
-	0x00,	
-	0xF2,	
+	0x00,
+	0xF2,
 	0xC8,				/* 503, promiscuous mode off */
-	0x00,	
-	0x40,	
+	0x00,
+	0x40,
 	0xF3,				/* transmit padding enable */
 	0x80,				/* full duplex pin enable */
 	0x3F,				/* no Multi IA */
@@ -354,14 +354,14 @@ static void txstart(Ether*);
 static void
 watchdog(void* arg)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Ether *ether;
 	Ctlr *ctlr;
 	//static void txstart(Ether*);
 
 	ether = arg;
 	for(;;){
-		tsleep(&m->externup->sleep, return0, 0, 4000);
+		tsleep(&up->sleep, return0, 0, 4000);
 
 		/*
 		 * Hmmm. This doesn't seem right. Currently
@@ -370,7 +370,7 @@ watchdog(void* arg)
 		 */
 		ctlr = ether->ctlr;
 		if(ctlr == nil || ctlr->state == 0){
-			print("%s: exiting\n", m->externup->text);
+			print("%s: exiting\n", up->text);
 			pexit("disabled", 0);
 		}
 
@@ -634,7 +634,7 @@ receive(Ether* ether)
 	for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
 		/*
 		 * If it's an OK receive frame
-		 * 1) save the count 
+		 * 1) save the count
 		 * 2) if it's small, try to allocate a block and copy
 		 *    the data, then adjust the necessary fields for reuse;
 		 * 3) if it's big, try to allocate a new Rfd and if
@@ -1216,7 +1216,7 @@ reset(Ether* ether)
 						break;
 				}
 				miiw(ctlr, phyaddr, 0x1A, 0x2000);
-					
+
 				anar = miir(ctlr, phyaddr, 0x04);
 				anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
 				anar &= anlpar;
@@ -1241,7 +1241,7 @@ reset(Ether* ether)
 					medium = k;
 					break;
 				}
-		
+
 				switch(medium){
 				default:
 					break;

+ 2 - 2
sys/src/9/386/ether82563.c

@@ -696,7 +696,7 @@ static Cmdtab i82563ctlmsg[] = {
 static int32_t
 i82563ctl(Ether* edev, void* buf, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t v;
 	char *p;
 	Ctlr *ctlr;
@@ -1222,7 +1222,7 @@ i82563tproc(void *v)
 static void
 i82563attach(Ether* edev)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Block *bp;
 	Ctlr *ctlr;
 	char name[KNAMELEN];

+ 2 - 2
sys/src/9/386/etherigbe.c

@@ -707,7 +707,7 @@ static Cmdtab igbectlmsg[] = {
 static int32_t
 igbectl(Ether* edev, void* buf, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int v;
 	char *p;
 	Ctlr *ctlr;
@@ -1235,7 +1235,7 @@ igberproc(void* arg)
 static void
 igbeattach(Ether* edev)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Block *bp;
 	Ctlr *ctlr;
 	char name[KNAMELEN];

+ 11 - 11
sys/src/9/386/etherm10g.c

@@ -485,7 +485,7 @@ prepcmd(uint *cmd, int i)
 uint32_t
 cmd(Ctlr *c, int type, uint64_t data)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t buf[16], i;
 	Cmd *cmd;
 
@@ -513,7 +513,7 @@ cmd(Ctlr *c, int type, uint64_t data)
 				dprint("[%ux]", i);
 			return i;
 		}
-		tsleep(&m->externup->sleep, return0, 0, 1);
+		tsleep(&up->sleep, return0, 0, 1);
 	}
 	qunlock(&c->cmdl);
 	iprint("m10g: cmd timeout [%ux %ux] cmd=%d\n",
@@ -525,7 +525,7 @@ cmd(Ctlr *c, int type, uint64_t data)
 uint32_t
 maccmd(Ctlr *c, int type, uint8_t *mac)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t buf[16], i;
 	Cmd *cmd;
 
@@ -553,7 +553,7 @@ maccmd(Ctlr *c, int type, uint8_t *mac)
 				dprint("[%ux]", i);
 			return i;
 		}
-		tsleep(&m->externup->sleep, return0, 0, 1);
+		tsleep(&up->sleep, return0, 0, 1);
 	}
 	qunlock(&c->cmdl);
 	iprint("m10g: maccmd timeout [%ux %ux] cmd=%d\n",
@@ -571,7 +571,7 @@ enum {
 uint32_t
 dmatestcmd(Ctlr *c, int type, uint64_t addr, int len)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t buf[16], i;
 
 	memset(buf, 0, sizeof buf);
@@ -596,7 +596,7 @@ dmatestcmd(Ctlr *c, int type, uint64_t addr, int len)
 			poperror();
 			return i;
 		}
-		tsleep(&m->externup->sleep, return0, 0, 5);
+		tsleep(&up->sleep, return0, 0, 5);
 	}
 	error(Etimeout);
 	return ~0;			/* silence! */
@@ -605,7 +605,7 @@ dmatestcmd(Ctlr *c, int type, uint64_t addr, int len)
 uint32_t
 rdmacmd(Ctlr *c, int on)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t buf[16], i;
 
 	memset(buf, 0, sizeof buf);
@@ -627,7 +627,7 @@ rdmacmd(Ctlr *c, int on)
 			poperror();
 			return gbit32(c->cmd->c);
 		}
-		tsleep(&m->externup->sleep, return0, 0, 1);
+		tsleep(&up->sleep, return0, 0, 1);
 	}
 	error(Etimeout);
 	iprint("m10g: rdmacmd timeout\n");
@@ -775,7 +775,7 @@ chkfw(Ctlr *c)
 static int
 reset(Ether *e, Ctlr *c)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t i, sz;
 
 	if(waserror()){
@@ -1339,7 +1339,7 @@ m10ginterrupt(Ureg *ureg, void *v)
 static void
 m10gattach(Ether *e)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Ctlr *c;
 	char name[12];
 
@@ -1499,7 +1499,7 @@ static Cmdtab ctab[] = {
 static int32_t
 m10gctl(Ether *e, void *v, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int i;
 	Cmdbuf *c;
 	Cmdtab *t;

+ 11 - 11
sys/src/9/386/pci.c

@@ -253,7 +253,7 @@ pcilscan(int bno, Pcidev** list)
 	return maxubn;
 }
 
-static uint8_t 
+static uint8_t
 pIIxget(Pcidev *router, uint8_t link)
 {
 	uint8_t pirq;
@@ -263,13 +263,13 @@ pIIxget(Pcidev *router, uint8_t link)
 	return (pirq < 16)? pirq: 0;
 }
 
-static void 
+static void
 pIIxset(Pcidev *router, uint8_t link, uint8_t irq)
 {
 	pcicfgw8(router, link, irq);
 }
 
-static uint8_t 
+static uint8_t
 viaget(Pcidev *router, uint8_t link)
 {
 	uint8_t pirq;
@@ -280,7 +280,7 @@ viaget(Pcidev *router, uint8_t link)
 	return (link & 1)? (pirq >> 4): (pirq & 15);
 }
 
-static void 
+static void
 viaset(Pcidev *router, uint8_t link, uint8_t irq)
 {
 	uint8_t pirq;
@@ -297,7 +297,7 @@ struct Bridge
 	uint16_t	vid;
 	uint16_t	did;
 	uint8_t	(*get)(Pcidev *, uint8_t);
-	void	(*set)(Pcidev *, uint8_t, uint8_t);	
+	void	(*set)(Pcidev *, uint8_t, uint8_t);
 };
 
 static Bridge southbridges[] = {
@@ -396,7 +396,7 @@ pcirouting(void)
 			if(pci == nil)
 				continue;
 			pin = pcicfgr8(pci, PciINTP);
-			if(pin == 0 || pin == 0xff) 
+			if(pin == 0 || pin == 0xff)
 				continue;
 
 			map = &e->maps[(pin - 1) * 3];
@@ -422,7 +422,7 @@ pcireservemem(void)
 {
 	int i;
 	Pcidev *p;
-	
+
 	for(p = nil; p = pcimatch(p, 0, 0); )
 		for(i=0; i<nelem(p->mem); i++)
 			if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
@@ -458,7 +458,7 @@ pcicfginit(void)
 			pcicfgmode = 1;
 	}
 	outl(PciADDR, n);
-	
+
 	if(pcicfgmode < 0){
 		unlock(&pcicfginitlock);
 		return;
@@ -475,7 +475,7 @@ pcicfginit(void)
 			continue;
 		/*
 		 * If we have found a PCI-to-Cardbus bridge, make sure
-		 * it has no valid mappings anymore.  
+		 * it has no valid mappings anymore.
 		 */
 		for(p = pciroot; p != nil; p = p->link){
 			if (p->ccrb == 6 && p->ccru == 7) {
@@ -486,7 +486,7 @@ pcicfginit(void)
 		}
 	}
 
-	// no longer. 
+	// no longer.
 	//if(pciroot != nil && getconf("*nopcirouting") == nil)
 	pcirouting();
 	pcireservemem();
@@ -692,7 +692,7 @@ pcicap(Pcidev *p, int cap)
 
 	/* status register bit 4 has capabilities */
 	if((pcicfgr16(p, PciPSR) & 1<<4) == 0)
-		return -1;	
+		return -1;
 	switch(pcicfgr8(p, PciHDT) & 0x7f){
 	default:
 		return -1;

+ 8 - 8
sys/src/9/386/random.c

@@ -50,9 +50,9 @@ rbnotempty(void* v)
 static void
 genrandom(void* v)
 {
-	Mach *m = machp();
-	m->externup->basepri = PriNormal;
-	m->externup->priority = m->externup->basepri;
+	Proc *up = machp()->externup;
+	up->basepri = PriNormal;
+	up->priority = up->basepri;
 
 	for(;;){
 		for(;;)
@@ -109,7 +109,7 @@ uint32_t
 randomread(void *xp, uint32_t n)
 {
 
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint8_t *e, *p;
 	uint32_t x;
 
@@ -121,7 +121,7 @@ randomread(void *xp, uint32_t n)
 	}
 
 	qlock(&rb);
-	
+
 	/** WORKAROUND **/
 	for(e = p + n; p < e; ){
 		x = (2 * rb.randn +1)%1103515245;
@@ -167,19 +167,19 @@ randomread(void *xp, uint32_t n)
 uint32_t
 urandomread(void *xp, uint32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint64_t seed[16];
 	uint8_t *e, *p;
 	uint32_t x=0;
 	uint64_t s0;
 	uint64_t s1;
-	
+
 	if(waserror()){
 		nexterror();
 	}
 	//The initial seed is from a good random pool.
 	randomread(seed, sizeof(seed));
-	
+
 	p = xp;
 	for(e = p + n; p < e; ){
 		s0 = seed[ x ];

+ 6 - 15
sys/src/9/386/sdiahci.c

@@ -267,12 +267,10 @@ dreg(char *s, Aport *p)
 static void
 esleep(int ms)
 {
-	Mach *m;
-
-	m = machp();
+	Proc *up = machp()->externup;
 	if(waserror())
 		return;
-	tsleep(&m->externup->sleep, return0, 0, ms);
+	tsleep(&up->sleep, return0, 0, ms);
 	poperror();
 }
 
@@ -288,9 +286,6 @@ ahciclear(void *v)
 static void
 aesleep(Aportm *pm, Asleep *a, int ms)
 {
-	Mach *m;
-
-	m = machp();
 	if(waserror())
 		return;
 	tsleep(pm, ahciclear, a, ms);
@@ -385,10 +380,8 @@ setudmamode(Aportc *pc, unsigned char f)
 static void
 asleep(int ms)
 {
-	Mach *m;
-
-	m = machp();
-	if(m->externup == nil)
+	Proc *up = machp()->externup;
+	if(up == nil)
 		delay(ms);
 	else
 		esleep(ms);
@@ -1307,12 +1300,10 @@ portreset:
 static void
 satakproc(void *v)
 {
-	Mach *m;
+	Proc *up = machp()->externup;
 	int i;
-
-	m = machp();
 	for(;;){
-		tsleep(&m->externup->sleep, return0, 0, Nms);
+		tsleep(&up->sleep, return0, 0, Nms);
 		for(i = 0; i < niadrive; i++)
 			if(iadrive[i] != nil)
 				checkdrive(iadrive[i], i);

+ 4 - 4
sys/src/9/386/uarti8250.c

@@ -185,7 +185,7 @@ i8250status(Uart* uart, void* buf, int32_t n, int32_t offset)
 		(msr & Dsr) != 0,
 		uart->hup_dsr,
 		(lcr & WlsMASK) + 5,
-		(ier & Ems) != 0, 
+		(ier & Ems) != 0,
 		(lcr & Pen) ? ((lcr & Eps) ? 'e': 'o'): 'n',
 		(mcr & Rts) != 0,
 		(lcr & Stb) ? 2: 1,
@@ -430,7 +430,7 @@ i8250baud(Uart* uart, int baud)
 static void
 i8250break(Uart* uart, int ms)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Ctlr *ctlr;
 
 	/*
@@ -441,7 +441,7 @@ i8250break(Uart* uart, int ms)
 
 	ctlr = uart->regs;
 	csr8w(ctlr, Lcr, Brk);
-	tsleep(&m->externup->sleep, return0, 0, ms);
+	tsleep(&up->sleep, return0, 0, ms);
 	csr8w(ctlr, Lcr, 0);
 }
 
@@ -782,7 +782,7 @@ i8250console(char* cfg)
 		break;
 	case 1:
 		uart = &i8250uart[1];
-		break;	
+		break;
 	}
 
 	/*

+ 20 - 20
sys/src/9/amd64pv/acore.c

@@ -50,14 +50,14 @@ extern void _actrapret(void);
 
 ACVctl *acvctl[256];
 
-/* 
+/*
  * Test inter core calls by calling a cores to print something, and then
  * waiting for it to complete.
  */
 static void
 testiccfn(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	print("called: %s\n", ( char *)m->icc->data);
 }
 
@@ -87,13 +87,13 @@ testicc(int i)
 static void
 acstackok(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char dummy;
 	char *sstart;
 
 	sstart = (char *)m - PGSZ - 4*PTSZ - MACHSTKSZ;
 	if(&dummy < sstart + 4*KiB){
-		print("ac kernel stack overflow, cpu%d stopped\n", m->machno);
+		print("ac kernel stack overflow, cpu%d stopped\n", machp()->machno);
 		DONE();
 	}
 }
@@ -109,16 +109,16 @@ acstackok(void)
 void
 acsched(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	acmmuswitch();
 	for(;;){
 		acstackok();
 		mwait(&m->icc->fn);
 		if(m->icc->flushtlb)
 			acmmuswitch();
-		DBG("acsched: cpu%d: fn %#p\n", m->machno, m->icc->fn);
+		DBG("acsched: cpu%d: fn %#p\n", machp()->machno, m->icc->fn);
 		m->icc->fn();
-		DBG("acsched: cpu%d: idle\n", m->machno);
+		DBG("acsched: cpu%d: idle\n", machp()->machno);
 		mfence();
 		m->icc->fn = nil;
 	}
@@ -127,13 +127,13 @@ acsched(void)
 void
 acmmuswitch(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	extern Page mach0pml4;
 
-	DBG("acmmuswitch mpl4 %#p mach0pml4 %#p m0pml4 %#p\n", m->pml4->pa, mach0pml4.pa, sys->machptr[0]->pml4->pa);
+	DBG("acmmuswitch mpl4 %#p mach0pml4 %#p m0pml4 %#p\n", machp()->pml4->pa, mach0pml4.pa, sys->machptr[0]->pml4->pa);
 
 
-	cr3put(m->pml4->pa);
+	cr3put(machp()->pml4->pa);
 }
 
 /*
@@ -149,7 +149,7 @@ actouser(void)
 	acfpusysprocsetup(m->proc);
 
 	u = m->proc->dbgreg;
-	DBG("cpu%d: touser usp = %#p entry %#p\n", m->machno, u->sp, u->ip);
+	DBG("cpu%d: touser usp = %#p entry %#p\n", machp()->machno, u->sp, u->ip);
 	xactouser(u->sp);
 #endif
 	panic("actouser");
@@ -163,12 +163,12 @@ actrapret(void)
 
 /*
  * Entered in AP core context, upon traps (system calls go through acsyscall)
- * using m->externup->dbgreg means cores MUST be homogeneous.
+ * using up->dbgreg means cores MUST be homogeneous.
  *
  * BUG: We should setup some trapenable() mechanism for the AC,
  * so that code like fpu.c could arrange for handlers specific for
  * the AC, instead of doint that by hand here.
- * 
+ *
  * All interrupts are masked while in the "kernel"
  */
 void
@@ -189,7 +189,7 @@ actrap(Ureg *u)
 	if(u->type < nelem(acvctl)){
 		v = acvctl[u->type];
 		if(v != nil){
-			DBG("actrap: cpu%d: %ulld\n", m->machno, u->type);
+			DBG("actrap: cpu%d: %ulld\n", machp()->machno, u->type);
 			n = v->f(u, v->a);
 			if(n != nil)
 				goto Post;
@@ -203,7 +203,7 @@ actrap(Ureg *u)
 		ndnr();
 	case IdtIPI:
 		m->intr++;
-		DBG("actrap: cpu%d: IPI\n", m->machno);
+		DBG("actrap: cpu%d: IPI\n", machp()->machno);
 		apiceoi(IdtIPI);
 		break;
 	case IdtTIMER:
@@ -213,10 +213,10 @@ actrap(Ureg *u)
 	case IdtPF:
 		/* this case is here for debug only */
 		m->pfault++;
-		DBG("actrap: cpu%d: PF cr2 %#ullx\n", m->machno, cr2get());
+		DBG("actrap: cpu%d: PF cr2 %#ullx\n", machp()->machno, cr2get());
 		break;
 	default:
-		print("actrap: cpu%d: %ulld\n", m->machno, u->type);
+		print("actrap: cpu%d: %ulld\n", machp()->machno, u->type);
 	}
 Post:
 	m->icc->rc = ICCTRAP;
@@ -254,7 +254,7 @@ acsyscall(void)
 	 * There's nothing else we have to do.
 	 * Otherwise, we should m->proc->dbgregs = u;
 	 */
-	DBG("acsyscall: cpu%d\n", m->machno);
+	DBG("acsyscall: cpu%d\n", machp()->machno);
 
 	_pmcupdate(m);
 	p = m->proc;
@@ -299,7 +299,7 @@ dumpreg(void *u)
 	ndnr();
 }
 
-char *rolename[] = 
+char *rolename[] =
 {
 	[NIXAC]	"AC",
 	[NIXTC]	"TC",
@@ -310,7 +310,7 @@ char *rolename[] =
 void
 acmodeset(int mode)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	switch(mode){
 	case NIXAC:
 	case NIXKC:

+ 3 - 3
sys/src/9/amd64pv/acpi.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
@@ -151,7 +151,7 @@ struct Reg
 	int	accsz;		/* access size */
 };
 
-/* Generic address structure. 
+/* Generic address structure.
  */
 struct Gas
 {
@@ -321,7 +321,7 @@ struct Srat
 			uint64_t	addr;	/* base address */
 			uint64_t	len;
 			int	hplug;	/* hot pluggable */
-			int	nvram;	/* non volatile */	
+			int	nvram;	/* non volatile */
 		} mem;
 		struct{
 			int	dom;	/* proximity domain */

+ 3 - 3
sys/src/9/amd64pv/amd64.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
@@ -156,7 +156,7 @@ enum {						/* Segment Descriptor */
  * Performance Counter Configuration
  */
 enum {						/* Performance Event Selector */
-    				 
+
 	PeHo		= 0x0000020000000000ull,/* Host only */
 	PeGo		= 0x0000010000000000ull,/* Guest only */
 	PeEvMskH	= 0x0000000f00000000ull,/* Event mask H */
@@ -202,4 +202,4 @@ enum {
  * Extern registers.
  */
 #define RMACH		R15			/* m-> */
-#define RUSER		R14			/* m->externup-> */
+#define RUSER		R14			/* up-> */

+ 6 - 6
sys/src/9/amd64pv/apic.c

@@ -118,7 +118,7 @@ apicisr(int vecno)
 void
 apicinit(int apicno, uintmem pa, int isbp)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Apic *apic;
 
 	/*
@@ -198,7 +198,7 @@ apictimer(Ureg* ureg, void* v)
 int
 apiconline(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Apic *apic;
 	uint64_t tsc;
 	uint32_t dfr, ver;
@@ -275,7 +275,7 @@ apiconline(void)
 	apic->min = apic->hz/(100*HZ);
 	apic->div = ((m->cpuhz/apic->max)+HZ/2)/HZ;
 
-	if(m->machno == 0 || DBGFLG){
+	if(machp()->machno == 0 || DBGFLG){
 		print("apic%d: hz %lld max %lld min %lld div %lld\n", apicno,
 			apic->hz, apic->max, apic->min, apic->div);
 	}
@@ -319,7 +319,7 @@ apiconline(void)
 	 * then lower the task priority to allow interrupts to be
 	 * accepted by the APIC.
 	 */
-	microdelay((TK2MS(1)*1000/apmachno) * m->machno);
+	microdelay((TK2MS(1)*1000/apmachno) * machp()->machno);
 
 	if(apic->machno == 0){
 		apicrput(Tic, apic->max);
@@ -327,7 +327,7 @@ apiconline(void)
 		apicrput(Tlvt, Periodic|IrqTIMER);
 	}
 
-	if(m->machno == 0)
+	if(machp()->machno == 0)
 		apicrput(Tp, 0);
 
 	xlapicmachptr[apicno] = m;
@@ -352,7 +352,7 @@ apictimerenab(void)
 void
 apictimerset(uint64_t next)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Mpl pl;
 	Apic *apic;
 	int64_t period;

+ 1 - 1
sys/src/9/amd64pv/apic.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No

+ 6 - 6
sys/src/9/amd64pv/arch.c

@@ -21,11 +21,11 @@
 #include "../port/error.h"
 
 /* the rules are different for different compilers. We need to define up. */
-// Initialize it to force it into data. 
+// Initialize it to force it into data.
 // That way, if we set them in assembly, they won't get zero'd by the bss init in main
 // N.B. There was an interesting hack in plan 9 c. You could grab up to two registers for your
 // program. In the case of Plan 9, m was r15, and up was r14. Very slick, and if there is a way to do
-// this in gcc or clang I don't know it. This also nicely handled per cpu info; R15/14 were always right for 
+// this in gcc or clang I don't know it. This also nicely handled per cpu info; R15/14 were always right for
 // your core and context.
 //Mach *m = (void *)0;
 
@@ -87,9 +87,9 @@ procsave(Proc *p)
 static void
 linkproc(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	spllo();
-	m->externup->kpfun(m->externup->kparg);
+	up->kpfun(up->kparg);
 	pexit("kproc dying", 0);
 }
 
@@ -119,12 +119,12 @@ kprocchild(Proc* p, void (*func)(void*), void* arg)
 void
 idlehands(void)
 {
-Mach *m = machp();
+Proc *up = machp()->externup;
 if(sys->nmach <= 1)
 {
 	halt();
 }
 if(0)
-	if(m->machno != 0)
+	if(machp()->machno != 0)
 		halt();
 }

+ 20 - 20
sys/src/9/amd64pv/archk10.c

@@ -19,7 +19,7 @@
 static int
 cpuidinit(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t eax, info[4];
 
 	/*
@@ -43,7 +43,7 @@ cpuidinit(void)
 
 	/* is mnonitor supported? */
 	if (m->cpuinfo[1][2] & 8) {
-		cpuid(5, 0, m->cpuinfo[2]);	
+		cpuid(5, 0, m->cpuinfo[2]);
 		mwait = k10mwait;
 	}
 
@@ -53,7 +53,7 @@ cpuidinit(void)
 static int
 cpuidinfo(uint32_t eax, uint32_t ecx, uint32_t info[4])
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	if(m->ncpuinfos == 0 && cpuidinit() == 0)
 		return 0;
 
@@ -214,7 +214,7 @@ print("\n");*/
 void
 cpuiddump(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int i;
 	uint32_t info[4];
 
@@ -239,7 +239,7 @@ cpuiddump(void)
 int64_t
 archhz(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int64_t hz;
 	uint32_t info0[4], info1[4];
 
@@ -254,7 +254,7 @@ archhz(void)
 	}
 
 	hz = cpuidhz(info0, info1);
-	if(hz != 0 || m->machno != 0)
+	if(hz != 0 || machp()->machno != 0)
 		return hz;
 
 	iprint("arch hz, cpuidhz failed, going to i8254hz\n");
@@ -264,11 +264,11 @@ archhz(void)
 int
 archmmu(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t info[4];
 
 	/*
-	 * Should the check for m->machno != 0 be here
+	 * Should the check for machp()->machno != 0 be here
 	 * or in the caller (mmuinit)?
 	 *
 	 * To do here:
@@ -283,9 +283,9 @@ archmmu(void)
 	 */
 	assert(PGSZ == 4*KiB);
 
-	m->pgszlg2[0] = 12;
-	m->pgszmask[0] = (1<<12)-1;
-	m->pgsz[0] = 1<<12;
+	machp()->pgszlg2[0] = 12;
+	machp()->pgszmask[0] = (1<<12)-1;
+	machp()->pgsz[0] = 1<<12;
 	m->npgsz = 1;
 	if(m->ncpuinfos == 0 && cpuidinit() == 0)
 		return 1;
@@ -296,18 +296,18 @@ archmmu(void)
 	 */
 	if(!(m->cpuinfo[1][3] & 0x00000008))
 		return 1;
-	m->pgszlg2[1] = 21;
-	m->pgszmask[1] = (1<<21)-1;
-	m->pgsz[1] = 1<<21;
+	machp()->pgszlg2[1] = 21;
+	machp()->pgszmask[1] = (1<<21)-1;
+	machp()->pgsz[1] = 1<<21;
 	m->npgsz = 2;
 
 	/*
 	 * Check the Page1GB bit in function 0x80000001 DX for 1*GiB support.
 	 */
 	if(cpuidinfo(0x80000001, 0, info) && (info[3] & 0x04000000)){
-		m->pgszlg2[2] = 30;
-		m->pgszmask[2] = (1<<30)-1;
-		m->pgsz[2] = 1<<30;
+		machp()->pgszlg2[2] = 30;
+		machp()->pgszmask[2] = (1<<30)-1;
+		machp()->pgsz[2] = 1<<30;
 		m->npgsz = 3;
 	}
 
@@ -357,7 +357,7 @@ fmtW(Fmt *f)
 	return fmtprint(f, "%#ullx=0x[%ullx][%ullx][%ullx][%ullx][%ullx]", va,
 		PTLX(va, 3), PTLX(va, 2), PTLX(va, 1), PTLX(va, 0),
 		va & ((1<<PGSHFT)-1));
-		
+
 }
 
 void
@@ -389,7 +389,7 @@ archidle(void)
 void
 microdelay(int microsecs)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint64_t r, t;
 
 	r = rdtsc();
@@ -400,7 +400,7 @@ microdelay(int microsecs)
 void
 millidelay(int millisecs)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint64_t r, t;
 
 	r = rdtsc();

+ 5 - 5
sys/src/9/amd64pv/asm.c

@@ -317,7 +317,7 @@ asmwalkalloc(usize size)
 void
 asmmeminit(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int i, l;
 	Asm* assem;
 	PTE *pte, *pml4;
@@ -327,7 +327,7 @@ asmmeminit(void)
 	int cx;
 #endif /* ConfCrap */
 
-	assert(!((sys->vmunmapped|sys->vmend) & m->pgszmask[1]));
+	assert(!((sys->vmunmapped|sys->vmend) & machp()->pgszmask[1]));
 
 	if((pa = mmuphysaddr(sys->vmunused)) == ~0)
 		panic("asmmeminit 1");
@@ -339,7 +339,7 @@ asmmeminit(void)
 
 	/* assume already 2MiB aligned*/
 	assert(ALIGNED(sys->vmunmapped, 2*MiB));
-	pml4 = UINT2PTR(m->pml4->va);
+	pml4 = UINT2PTR(machp()->pml4->va);
 	while(sys->vmunmapped < sys->vmend){
 		l = mmuwalk(pml4, sys->vmunmapped, 1, &pte, asmwalkalloc);
 		DBG("%#p l %d\n", sys->vmunmapped, l);
@@ -363,11 +363,11 @@ asmmeminit(void)
 		hi = assem->addr+assem->size;
 		/* Convert a range into pages */
 		for(mem = lo; mem < hi; mem = nextmem){
-			nextmem = (mem + PGLSZ(0)) & ~m->pgszmask[0];
+			nextmem = (mem + PGLSZ(0)) & ~machp()->pgszmask[0];
 
 			/* Try large pages first */
 			for(i = m->npgsz - 1; i >= 0; i--){
-				if((mem & m->pgszmask[i]) != 0)
+				if((mem & machp()->pgszmask[i]) != 0)
 					continue;
 				if(mem + PGLSZ(i) > hi)
 					continue;

+ 1 - 1
sys/src/9/amd64pv/backtrace.c

@@ -29,7 +29,7 @@ int backtrace_list(uintptr_t pc, uintptr_t fp, uintptr_t *pcs, size_t nr_slots)
 
 #if 0
 void backtrace_frame(uintptr_t eip, uintptr_t ebp)
-{ 
+{
 	char *func_name;
 	#define MAX_BT_DEPTH 20
 	uintptr_t pcs[MAX_BT_DEPTH];

+ 3 - 3
sys/src/9/amd64pv/dat.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
@@ -162,7 +162,7 @@ struct MFPU
 struct NIX
 {
 	ICC*	icc;			/* inter-core call */
-	int	nixtype;	
+	int	nixtype;
 };
 
 /*
@@ -422,7 +422,7 @@ extern char*rolename[];
 /*
  * Horrid.
  */
-// HARVEY: TODO: bring this back, it's actually nice. Or do something better. 
+// HARVEY: TODO: bring this back, it's actually nice. Or do something better.
 // Talk to Ron before you condemn it.
 
 #ifdef _DBGC_

+ 9 - 9
sys/src/9/amd64pv/devacpi.c

@@ -273,21 +273,21 @@ cfgset32(uintptr_t p, uint32_t v, void* r)
 	pcicfgw32(&d, p, v);
 }
 
-static Regio memio = 
+static Regio memio =
 {
 	nil,
 	mget8, mset8, mget16, mset16,
 	mget32, mset32, mget64, mset64
 };
 
-static Regio ioio = 
+static Regio ioio =
 {
 	nil,
 	ioget8, ioset8, ioget16, ioset16,
 	ioget32, ioset32, nil, nil
 };
 
-static Regio cfgio = 
+static Regio cfgio =
 {
 	nil,
 	cfgget8, cfgset8, cfgget16, cfgset16,
@@ -777,7 +777,7 @@ static void
 dumpslit(Slit *sl)
 {
 	int i;
-	
+
 	DBG("acpi slit:\n");
 	for(i = 0; i < sl->rowlen*sl->rowlen; i++){
 		DBG("slit: %ux\n", sl->e[i/sl->rowlen][i%sl->rowlen].dist);
@@ -819,7 +819,7 @@ acpislit(uint8_t *p, int len)
 	dumpslit(slit);
 	for(i = 0; i < slit->rowlen; i++)
 		qsort(slit->e[i], slit->rowlen, sizeof(slit->e[0][0]), cmpslitent);
-	
+
 	dumpslit(slit);
 	return nil;	/* can be unmapped once parsed */
 }
@@ -846,7 +846,7 @@ acpimblocksize(uintmem addr, int *dom)
 int
 corecolor(int core)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Srat *sl;
 	static int colors[32];
 
@@ -1455,7 +1455,7 @@ acpiintr(Ureg* ureg, void *j)
 	if(sts&1)
 		print("power button\n");
 	// XXX serve other interrupts here.
-	setpm1sts(sts);	
+	setpm1sts(sts);
 }
 
 static void
@@ -1615,7 +1615,7 @@ acpiread(Chan *c, void *a, int32_t n, int64_t off)
 				}
 				s = ns;
 			}
-					
+
 		}
 		return readstr(off, a, n, ttext);
 	case Qio:
@@ -1630,7 +1630,7 @@ acpiread(Chan *c, void *a, int32_t n, int64_t off)
 static int32_t
 acpiwrite(Chan *c, void *a, int32_t n, int64_t off)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Cmdtab *ct;
 	Cmdbuf *cb;
 	Reg *r;

+ 6 - 6
sys/src/9/amd64pv/devarch.c

@@ -296,7 +296,7 @@ iounused(int start, int end)
 	for(map = iomap.map; map; map = map->next){
 		if(start >= map->start && start < map->end
 		|| start <= map->start && end > map->start)
-			return 0; 
+			return 0;
 	}
 	return 1;
 }
@@ -436,7 +436,7 @@ archread(Chan *c, void *a, int32_t n, int64_t offset)
 			}
 #endif
 		error("Not yet");
-	
+
 		break;
 	}
 
@@ -525,7 +525,7 @@ void (*coherence)(void) = mfence;
 static int32_t
 cputyperead(Chan* c, void *a, int32_t n, int64_t off)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char buf[512], *s, *e;
 	int i, k;
 
@@ -576,7 +576,7 @@ archreset(void)
 uint64_t
 fastticks(uint64_t* hz)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	if(hz != nil)
 		*hz = m->cpuhz;
 	return rdtsc();
@@ -608,7 +608,7 @@ cycles(uint64_t* t)
 void
 delay(int millisecs)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint64_t r, t;
 
 	if(millisecs <= 0)
@@ -618,7 +618,7 @@ delay(int millisecs)
 		;
 }
 
-/*  
+/*
  *  performance measurement ticks.  must be low overhead.
  *  doesn't have to count over a second.
  */

+ 18 - 18
sys/src/9/amd64pv/devusb.c

@@ -276,7 +276,7 @@ addhcitype(char* t, int (*r)(Hci*))
 static char*
 seprintep(char *s, char *se, Ep *ep, int all)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	static char* dsnames[] = { "config", "enabled", "detached", "reset" };
 	Udev *d;
 	int i;
@@ -410,7 +410,7 @@ putep(Ep *ep)
 static void
 dumpeps(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int i;
 	static char buf[512];
 	char *s;
@@ -547,7 +547,7 @@ epdataperm(int mode)
 static int
 usbgen(Chan *c, char *l, Dirtab *d, int n, int s, Dir *dp)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Qid q;
 	Dirtab *dir;
 	int perm;
@@ -619,12 +619,12 @@ usbgen(Chan *c, char *l, Dirtab *d, int n, int s, Dir *dp)
 			putep(ep);
 			nexterror();
 		}
-		se = m->externup->genbuf+sizeof(m->externup->genbuf);
-		seprint(m->externup->genbuf, se, "ep%d.%d", ep->dev->nb, ep->nb);
+		se = up->genbuf+sizeof(up->genbuf);
+		seprint(up->genbuf, se, "ep%d.%d", ep->dev->nb, ep->nb);
 		mkqid(&q, Qep0dir+4*s, 0, QTDIR);
 		putep(ep);
 		poperror();
-		devdir(c, q, m->externup->genbuf, 0, eve, 0755, dp);
+		devdir(c, q, up->genbuf, 0, eve, 0755, dp);
 		if(0)ddprint("ok\n");
 		return 1;
 
@@ -835,7 +835,7 @@ usbload(int speed, int maxpkt)
 static Chan*
 usbopen(Chan *c, int omode)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int q;
 	Ep *ep;
 	int mode;
@@ -892,7 +892,7 @@ usbopen(Chan *c, int omode)
 static void
 epclose(Ep *ep)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	qlock(ep);
 	if(waserror()){
 		qunlock(ep);
@@ -909,7 +909,7 @@ epclose(Ep *ep)
 static void
 usbclose(Chan *c)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int q;
 	Ep *ep;
 
@@ -939,7 +939,7 @@ usbclose(Chan *c)
 static int32_t
 ctlread(Chan *c, void *a, int32_t n, int64_t offset)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int q;
 	char *s;
 	char *us;
@@ -1056,7 +1056,7 @@ rhubwrite(Ep *ep, void *a, int32_t n)
 static int32_t
 usbread(Chan *c, void *a, int32_t n, int64_t offset)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int q;
 	Ep *ep;
 	int nr;
@@ -1134,7 +1134,7 @@ setmaxpkt(Ep *ep, char* s)
 static int32_t
 epctl(Ep *ep, Chan *c, void *a, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int i, l, mode, nb, tt;
 	char *b, *s;
 	Cmdbuf *cb;
@@ -1190,9 +1190,9 @@ epctl(Ep *ep, Chan *c, void *a, int32_t n)
 		/* next read request will read
 		 * the name for the new endpoint
 		 */
-		l = sizeof(m->externup->genbuf);
-		snprint(m->externup->genbuf, l, "ep%d.%d", nep->dev->nb, nep->nb);
-		kstrdup((char**)&c->aux, m->externup->genbuf);
+		l = sizeof(up->genbuf);
+		snprint(up->genbuf, l, "ep%d.%d", nep->dev->nb, nep->nb);
+		kstrdup((char**)&c->aux, up->genbuf);
 		break;
 	case CMhub:
 		deprint("usb epctl %s\n", cb->f[0]);
@@ -1348,7 +1348,7 @@ epctl(Ep *ep, Chan *c, void *a, int32_t n)
 static int32_t
 usbctl(void *a, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Cmdtab *ct;
 	Cmdbuf *cb;
 	Ep *ep;
@@ -1388,7 +1388,7 @@ usbctl(void *a, int32_t n)
 static int32_t
 ctlwrite(Chan *c, void *a, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int q;
 	Ep *ep;
 
@@ -1420,7 +1420,7 @@ ctlwrite(Chan *c, void *a, int32_t n)
 static int32_t
 usbwrite(Chan *c, void *a, int32_t n, int64_t off)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int nr, q;
 	Ep *ep;
 

+ 10 - 10
sys/src/9/amd64pv/entry.S

@@ -6,7 +6,7 @@
 
 // It gets REALLY ugly to try  to link this at some low address and then have the rest of the
 // kernel linked high. Really, really ugly. And that defines any attempt to load at a randome
-// address. So, you have to learn to write position independent code here. 
+// address. So, you have to learn to write position independent code here.
 // It will make you stronger. Assuming you survive the training.
 .code32
 
@@ -90,7 +90,7 @@ gdt_end:
  *	cache will be reloaded.
  */
 	.align	4
-1: 
+1:
 //	jmp 1b
 .globl protected_start
 protected_start:
@@ -316,7 +316,7 @@ _start64v:
 // Don't undo this until all APs are started. Then we don't need to bother
 // having the APs remap it. Save work.
 	// OK, this part is called "we climbed up the tree on a ladder, now pull
-	// the ladder up after us.". We remove the identity mapping. 
+	// the ladder up after us.". We remove the identity mapping.
 _zap0pml4:
 	cmpq	$PML4O(KZERO), %rdx		/* KZER0 & 0x0000ff8000000000 */
 	JE	_zap0pdp
@@ -340,7 +340,7 @@ _zap0done:
 
 	addq	$(2*PTSZ+4*KiB), %rax		/* PD+PT+vsvm */
 	movq	%rax, entrym
-	movq	$0, (%rax) 				/* m->machno = 0 */
+	movq	$0, (%rax) 				/* machp()->machno = 0 */
 
 	PUSHQ	%rdx				/* clear flags */
 	POPFQ
@@ -437,7 +437,7 @@ gdtptr78:
 	.quad	0x0020980000000000		/* Long mode CS */
 gdt78_end:
 .global e1978
-e1978:	
+e1978:
 
 /*
  * Protected mode. Welcome to 1982.
@@ -467,7 +467,7 @@ e1978:
 #define PDO(v)		((PTLX((v), 1))<<3)
 #define PTO(v)		((PTLX((v), 0))<<3)
 
-_approtected:	
+_approtected:
 	MOVL	$0xfee00000, %ebp	/* apicbase */
 	MOVL	0x20(%eBP), %eBP	/* Id */
 	SHRL	$24, %eBP		/* becomes RARG later */
@@ -504,7 +504,7 @@ _approtected:
  *	make an inter-segment jump to the Long Mode code.
  * It's all in 32-bit mode until the jump is made.
  */
-aplme:	
+aplme:
 	MOVL	%CR4, %eAX
 	ANDL	$~Pse, %eAX			/* Page Size */
 	ORL	$(Pge|Pae), %eAX			/* Page Global, Phys. Address */
@@ -532,12 +532,12 @@ aplme:
  */
 .code64
 
-_apidentity:	
+_apidentity:
 	MOVQ	$_apstart64v, %rAX
 	JMP	*%rAX
 
 .section .text
-_apstart64v:	
+_apstart64v:
 	MOVQ	$_gdtptr64v, %rAX
 
 	lgdt	(%rax)
@@ -554,7 +554,7 @@ _apstart64v:
 
 	MOVQ	%rAX, %rSP			/* set stack */
 
-	// DON'T ZAP. 
+	// DON'T ZAP.
 	// DO IT LATER.
 	//MOVQ	%rDX, PML4O(0)(%rAX)		/* zap identity map */
 

+ 1 - 1
sys/src/9/amd64pv/ether8139.c

@@ -754,7 +754,7 @@ rtl8139match(Ether* edev, int id)
 
 		if(pcigetpms(p) > 0){
 			pcisetpms(p, 0);
-	
+
 			for(i = 0; i < 6; i++)
 				pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
 			pcicfgw8(p, PciINTL, p->intl);

+ 7 - 7
sys/src/9/amd64pv/ether82563.c

@@ -8,7 +8,7 @@
  */
 
  /*
- * Intel 8256[367], 8257[1-9], 82573[ev], 
+ * Intel 8256[367], 8257[1-9], 82573[ev],
  * 82575eb, 82576, 82577, 82579, 8258[03]
  *	Gigabit Ethernet PCI-Express Controllers
  * Coraid EtherDriveĀ® hba
@@ -488,7 +488,7 @@ enum {
 	i82575,
 	i82576,
 	i82577,
-	i82577m,	
+	i82577m,
 	i82578,
 	i82578m,
 	i82579,
@@ -879,7 +879,7 @@ i82563txinit(Ctlr* ctlr)
 	csr32w(ctlr, Tdt, 0);
 	for(i = 0; i < ctlr->ntd; i++){
 		if((bp = ctlr->tb[i]) != nil){
-			ctlr->tb[i] = nil;	
+			ctlr->tb[i] = nil;
 			freeb(bp);
 		}
 		memset(&ctlr->tdba[i], 0, sizeof(Td));
@@ -1423,7 +1423,7 @@ i82563tproc(void *v)
 static void
 i82563attach(Ether* edev)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char name[KNAMELEN];
 	Block *bp;
 	Ctlr *ctlr;
@@ -1809,7 +1809,7 @@ static Cmdtab i82563ctlmsg[] = {
 static int32_t
 i82563ctl(Ether *edev, void *buf, int32_t n)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char *p;
 	uint32_t v;
 	Ctlr *ctlr;
@@ -1923,7 +1923,7 @@ didtype(int d)
 	case 0x150f:		/* fiber */
 	case 0x1510:		/* backplane */
 	case 0x1511:		/* sfp */
-	case 0x1516:		
+	case 0x1516:
 		return i82580;
 	case 0x1506:		/* v */
 		return i82583;
@@ -1974,7 +1974,7 @@ i82563pci(void)
 		if((type = didtype(p->did)) == -1)
 			continue;
 		ctlr = malloc(sizeof(Ctlr));
-		if(ctlr == nil) 
+		if(ctlr == nil)
 			error(Enomem);
 		ctlr->type = type;
 		ctlr->pcidev = p;

+ 1 - 1
sys/src/9/amd64pv/etherif.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No

+ 1 - 1
sys/src/9/amd64pv/fns.h

@@ -205,7 +205,7 @@ void	acsyscallentry(void);
 void	syscallreturn(void);
 void	sysrforkret(void);
 
-#define	waserror()	(m->externup->nerrlab++, setlabel(&m->externup->errlab[m->externup->nerrlab-1]))
+#define	waserror()	(up->nerrlab++, setlabel(&up->errlab[up->nerrlab-1]))
 
 #define	dcflush(a, b)
 

+ 44 - 44
sys/src/9/amd64pv/fpu.c

@@ -120,7 +120,7 @@ fpudevprocio(Proc* proc, void* a, int32_t n, uintptr_t offset, int write)
 void
 fpunotify(Ureg* u)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	/*
 	 * Called when a note is about to be delivered to a
 	 * user process, usually at the end of a system call.
@@ -128,55 +128,55 @@ fpunotify(Ureg* u)
 	 * the state is marked (after saving if necessary) and
 	 * checked in the Device Not Available handler.
 	 */
-	if(m->externup->fpustate == Busy){
-		_fxsave(m->externup->fpusave);
+	if(up->fpustate == Busy){
+		_fxsave(up->fpusave);
 		_stts();
-		m->externup->fpustate = Idle;
+		up->fpustate = Idle;
 	}
-	m->externup->fpustate |= Hold;
+	up->fpustate |= Hold;
 }
 
 void
 fpunoted(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	/*
 	 * Called from sysnoted() via the machine-dependent
 	 * noted() routine.
 	 * Clear the flag set above in fpunotify().
 	 */
-	m->externup->fpustate &= ~Hold;
+	up->fpustate &= ~Hold;
 }
 
 void
 fpusysrfork(Ureg* u)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	/*
 	 * Called early in the non-interruptible path of
 	 * sysrfork() via the machine-dependent syscall() routine.
 	 * Save the state so that it can be easily copied
 	 * to the child process later.
 	 */
-	if(m->externup->fpustate != Busy)
+	if(up->fpustate != Busy)
 		return;
 
-	_fxsave(m->externup->fpusave);
+	_fxsave(up->fpusave);
 	_stts();
-	m->externup->fpustate = Idle;
+	up->fpustate = Idle;
 }
 
 void
 fpusysrforkchild(Proc* child, Proc* parent)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	/*
 	 * Called later in sysrfork() via the machine-dependent
 	 * sysrforkchild() routine.
 	 * Copy the parent FPU state to the child.
 	 */
 	child->fpustate = parent->fpustate;
-	child->fpusave = (void*)((PTR2UINT(m->externup->fxsave) + 15) & ~15);
+	child->fpusave = (void*)((PTR2UINT(up->fxsave) + 15) & ~15);
 	if(child->fpustate == Init)
 		return;
 
@@ -212,7 +212,7 @@ fpuprocsave(Proc* p)
 	/*
 	 * Save the FPU state without handling pending
 	 * unmasked exceptions and disable. Postnote() can't
-	 * be called here as sleep() already has m->externup->rlock,
+	 * be called here as sleep() already has up->rlock,
 	 * so the handling of pending exceptions is delayed
 	 * until the process runs again and generates a
 	 * Device Not Available exception fault to activate
@@ -266,7 +266,7 @@ acfpusysprocsetup(Proc *p)
 static char*
 fpunote(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint16_t fsw;
 	Fxsave *fpusave;
 	char *cm;
@@ -276,7 +276,7 @@ fpunote(void)
 	 * cleared or there's no way to tell if the exception was an
 	 * invalid operation or a stack fault.
 	 */
-	fpusave = m->externup->fpusave;
+	fpusave = up->fpusave;
 	fsw = (fpusave->fsw & ~fpusave->fcw) & (Sff|P|U|O|Z|D|I);
 	if(fsw & I){
 		if(fsw & Sff){
@@ -301,16 +301,16 @@ fpunote(void)
 	else
 		cm =  "Unknown";
 
-	snprint(m->externup->genbuf, sizeof(m->externup->genbuf),
+	snprint(up->genbuf, sizeof(up->genbuf),
 		"sys: fp: %s Exception ipo=%#llux fsw=%#ux",
 		cm, fpusave->rip, fsw);
-	return m->externup->genbuf;
+	return up->genbuf;
 }
 
 char*
 xfpuxf(Ureg* ureg, void* v)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint32_t mxcsr;
 	Fxsave *fpusave;
 	char *cm;
@@ -322,10 +322,10 @@ xfpuxf(Ureg* ureg, void* v)
 	/*
 	 * Save FPU state to check out the error.
 	 */
-	fpusave = m->externup->fpusave;
+	fpusave = up->fpusave;
 	_fxsave(fpusave);
 	_stts();
-	m->externup->fpustate = Idle;
+	up->fpustate = Idle;
 
 	if(ureg->ip & KZERO)
 		panic("#MF: ip=%#p", ureg->ip);
@@ -352,20 +352,20 @@ xfpuxf(Ureg* ureg, void* v)
 	else
 		cm =  "Unknown";
 
-	snprint(m->externup->genbuf, sizeof(m->externup->genbuf),
+	snprint(up->genbuf, sizeof(up->genbuf),
 		"sys: fp: %s Exception mxcsr=%#ux", cm, mxcsr);
-	return m->externup->genbuf;
+	return up->genbuf;
 }
 
 void
 fpuxf(Ureg *ureg, void *p)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char *n;
 
 	n = xfpuxf(ureg, p);
 	if(n != nil)
-		postnote(m->externup, 1, n, NDebug);
+		postnote(up, 1, n, NDebug);
 }
 
 char*
@@ -377,7 +377,7 @@ acfpuxf(Ureg *ureg, void *p)
 static char*
 xfpumf(Ureg* ureg, void* v)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Fxsave *fpusave;
 
 	/*
@@ -387,10 +387,10 @@ xfpumf(Ureg* ureg, void* v)
 	/*
 	 * Save FPU state to check out the error.
 	 */
-	fpusave = m->externup->fpusave;
+	fpusave = up->fpusave;
 	_fxsave(fpusave);
 	_stts();
-	m->externup->fpustate = Idle;
+	up->fpustate = Idle;
 
 	if(ureg->ip & KZERO)
 		panic("#MF: ip=%#p rip=%#p", ureg->ip, fpusave->rip);
@@ -414,12 +414,12 @@ xfpumf(Ureg* ureg, void* v)
 void
 fpumf(Ureg *ureg, void *p)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char *n;
 
 	n = xfpumf(ureg, p);
 	if(n != nil)
-		postnote(m->externup, 1, n, NDebug);
+		postnote(up, 1, n, NDebug);
 }
 
 char*
@@ -431,30 +431,30 @@ acfpumf(Ureg *ureg, void *p)
 static char*
 xfpunm(Ureg* ureg, void* v)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Fxsave *fpusave;
 
 	/*
 	 * #NM - Device Not Available (Vector 7).
 	 */
-	if(m->externup == nil)
+	if(up == nil)
 		panic("#NM: fpu in kernel: ip %#p\n", ureg->ip);
 
 	/*
 	 * Someone tried to use the FPU in a note handler.
 	 * That's a no-no.
 	 */
-	if(m->externup->fpustate & Hold)
+	if(up->fpustate & Hold)
 		return "sys: floating point in note handler";
 
 	if(ureg->ip & KZERO)
 		panic("#NM: proc %d %s state %d ip %#p\n",
-			m->externup->pid, m->externup->text, m->externup->fpustate, ureg->ip);
+			up->pid, up->text, up->fpustate, ureg->ip);
 
-	switch(m->externup->fpustate){
+	switch(up->fpustate){
 	case Busy:
 	default:
-		panic("#NM: state %d ip %#p\n", m->externup->fpustate, ureg->ip);
+		panic("#NM: state %d ip %#p\n", up->fpustate, ureg->ip);
 		break;
 	case Init:
 		/*
@@ -470,8 +470,8 @@ xfpunm(Ureg* ureg, void* v)
 		_fwait();
 		_fldcw(m->fcw);
 		_ldmxcsr(m->mxcsr);
-		m->externup->fpusave = (void*)((PTR2UINT(m->externup->fxsave) + 15) & ~15);
-		m->externup->fpustate = Busy;
+		up->fpusave = (void*)((PTR2UINT(up->fxsave) + 15) & ~15);
+		up->fpustate = Busy;
 		break;
 	case Idle:
 		/*
@@ -479,7 +479,7 @@ xfpunm(Ureg* ureg, void* v)
 		 * exceptions, there's no way to restore the state without
 		 * generating an unmasked exception.
 		 */
-		fpusave = m->externup->fpusave;
+		fpusave = up->fpusave;
 		if((fpusave->fsw & ~fpusave->fcw) & (Sff|P|U|O|Z|D|I))
 			return fpunote();
 
@@ -489,7 +489,7 @@ xfpunm(Ureg* ureg, void* v)
 		fpusave->fcw &= ~Sff;
 		_clts();
 		_fxrstor(fpusave);
-		m->externup->fpustate = Busy;
+		up->fpustate = Busy;
 		break;
 	}
 	return nil;
@@ -498,12 +498,12 @@ xfpunm(Ureg* ureg, void* v)
 void
 fpunm(Ureg *ureg, void *p)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char *n;
 
 	n = xfpunm(ureg, p);
 	if(n != nil)
-		postnote(m->externup, 1, n, NDebug);
+		postnote(up, 1, n, NDebug);
 }
 
 char*
@@ -515,7 +515,7 @@ acfpunm(Ureg *ureg, void *p)
 void
 fpuinit(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uint64_t r;
 	Fxsave *fxsave;
 	uint8_t buf[sizeof(Fxsave)+15];
@@ -544,7 +544,7 @@ fpuinit(void)
 	m->mxcsr = (Rn|Pm|Um|Dm) & m->mxcsrmask;
 	_stts();
 
-	if(m->machno != 0)
+	if(machp()->machno != 0)
 		return;
 
 	/*

+ 1 - 1
sys/src/9/amd64pv/io.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No

+ 1 - 1
sys/src/9/amd64pv/ioapic.c

@@ -266,7 +266,7 @@ ioapicintrdd(uint32_t* hi, uint32_t* lo)
 				break;
 		}
 		unlock(&dflock);
-	
+
 		*hi = i<<24;
 		break;
 	}

+ 1 - 1
sys/src/9/amd64pv/iob.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No

+ 1 - 1
sys/src/9/amd64pv/l64acidt.S

@@ -83,7 +83,7 @@ _aciretnested:
 	iretq
 
 .globl acidthandlers
-acidthandlers:	
+acidthandlers:
 	CALL _acintrp; .byte IdtDE		/* #DE Divide-by-Zero Error */
 	CALL _acintrp; .byte IdtDB		/* #DB Debug */
 	CALL _acintrp; .byte IdtNMI		/* #NMI Borked */

+ 7 - 7
sys/src/9/amd64pv/l64idt.S

@@ -20,7 +20,7 @@
 	* EIP of interrupted code 8(%rsp)
 	* EIP from the call from the idthandlers. (%rsp)
 	* We, finally, need to push the error code and type.,
-	* then the registers. 
+	* then the registers.
 	* Why the call from IDThandlers? So we can get a way to point
 	* to the type. We don't need to save 0(%rsp), we just need
 	* it to get the type. We can pop it and throw it away when
@@ -37,14 +37,14 @@
 	* is on the stack. For others, it's not. To make the stacks
 	* look identical for the common code and exit we save %rax and line things up.
 	*/
-	
+
 .globl ire
 .globl irx
 .globl irxe
-// When we enter: 
+// When we enter:
 // registers are NOT saved. We need to save them all.
 // return PC is on the stat8(%rsp). It should be left there.
-// @ (%rsp) is the PC from the vector table. 
+// @ (%rsp) is the PC from the vector table.
 // So indirecting on that will get us the interrupt #.
 // We need to get what the return PC is pointing to into %rdi.
 // We no longer need to make the stack look the same as in Plan 9
@@ -58,8 +58,8 @@ _intrp:
 	// Now %rax points to the vector number.
 	JMP	_intrcommon
 
-// For intre, error is at top of stack on trap. But then we call here 
-// from the interrupt vectors so error is at 8(%rsp). 
+// For intre, error is at top of stack on trap. But then we call here
+// from the interrupt vectors so error is at 8(%rsp).
 // I just realized I think intre means interrupt exception, e.g. page fault.
 .globl _intre
 _intre:
@@ -69,7 +69,7 @@ _intre:
 	XCHGQ	%rax, (%rsp)
 	// Now %rax points to the vector number.
 
-// When we get here: 
+// When we get here:
 // %RAX points to our vector number, i.e. "return" pc from calls below.
 // For intrp, (%rsp) is bogus code, 8(%rsp) is pointer to vno
 // for intre, (%rsp) is pointer to vno, 8(%rsp) is error code.

+ 5 - 5
sys/src/9/amd64pv/l64vsyscall.S

@@ -10,7 +10,7 @@
  * starting the user program up. First time.
  */
 	.globl touser
-touser:	
+touser:
 	CLI
 	SWAPGS
 	// we should be able to skip this step. We'll see.
@@ -34,7 +34,7 @@ touser:
 .global syscallentry
 syscallentry:
 	incq	sce
-	SWAPGS	
+	SWAPGS
 	movq	%gs:0, %r15
 	movq	16(%r15), %r15			/* m->proc */
 	// NOTE! This assumes sizeof(Label) == 16!
@@ -76,7 +76,7 @@ syscallentry:
 	CALL	syscall
 
 	.globl	syscallreturn
-syscallreturn:	
+syscallreturn:
 #ifdef NOTNOW
 	/* we do the TLS setup in linuxsyscall.c.
 	 * Leave this here in case we ever think it should be done
@@ -125,7 +125,7 @@ _linuxsyscallreturn:
 	MOVW	4(%rsp), FS
 	*/
 	MOVW	6(%rsp), GS
-#endif	
+#endif
 
 	MOVQ	0(%rsp), %rCX			/* ip */
 	MOVQ	16(%rsp), %r11			/* flags */
@@ -137,7 +137,7 @@ _linuxsyscallreturn:
 //	BYTE $0x48; SYSRET			/* SYSRETQ */
 
 	.globl sysrforkret
-sysrforkret:	
+sysrforkret:
 //	CALL	linuxclonefinish(SB)
 	// DEBUG
 	MOVQ	$0, %rAX

+ 42 - 42
sys/src/9/amd64pv/main.c

@@ -106,7 +106,7 @@ squidboy(int apicno, Mach *m)
 {
 	// FIX QEMU. extern int64_t hz;
 	int64_t hz;
-	sys->machptr[m->machno] = m;
+	sys->machptr[machp()->machno] = m;
 	/*
 	 * Need something for initial delays
 	 * until a timebase is worked out.
@@ -123,7 +123,7 @@ squidboy(int apicno, Mach *m)
 	// PRINT WILL PANIC. So wait.
 	vsvminit(MACHSTKSZ, m->nixtype, m);
 
-	DBG("Hello Squidboy %d %d\n", apicno, m->machno);
+	DBG("Hello Squidboy %d %d\n", apicno, machp()->machno);
 
 
 	/*
@@ -156,7 +156,7 @@ squidboy(int apicno, Mach *m)
 	m->rdtsc = rdtsc();
 
 	print("cpu%d color %d role %s tsc %lld\n",
-		m->machno, corecolor(m->machno), rolename[m->nixtype], m->rdtsc);
+		machp()->machno, corecolor(machp()->machno), rolename[m->nixtype], m->rdtsc);
 	switch(m->nixtype){
 	case NIXAC:
 		acmmuswitch();
@@ -214,7 +214,7 @@ testiccs(void)
 static void
 nixsquids(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Mach *mp;
 	int i;
 	uint64_t now, start;
@@ -275,7 +275,7 @@ void wave(int c)
 	outb(0x3f8, c);
 }
 
-void hi(char *s) 
+void hi(char *s)
 {
 	if (! s)
 		s = "<NULL>";
@@ -284,14 +284,14 @@ void hi(char *s)
 }
 
 /*
- * for gdb: 
- * call this anywhere in your code. 
+ * for gdb:
+ * call this anywhere in your code.
  *   die("yourturn with gdb\n");
  *   gdb 9k
  *   target remote localhost:1234
  *   display/i $pc
  *   set staydead = 0
- *   stepi, and debug. 
+ *   stepi, and debug.
  * note, you can always resume after a die. Just set staydead = 0
  */
 
@@ -341,14 +341,14 @@ void put64(uint64_t v)
 
 void debugtouser(void *va)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	uintptr_t uva = (uintptr_t) va;
 	PTE *pte, *pml4;
 
-	pml4 = UINT2PTR(m->pml4->va);
+	pml4 = UINT2PTR(machp()->pml4->va);
 	mmuwalk(pml4, uva, 0, &pte, nil);
-	iprint("va %p m %p m>pml4 %p m->pml4->va %p pml4 %p PTE 0x%lx\n", va,
-			m, m->pml4, m->pml4->va, (void *)pml4, *pte);
+	iprint("va %p m %p m>pml4 %p machp()->pml4->va %p pml4 %p PTE 0x%lx\n", va,
+			m, machp()->pml4, machp()->pml4->va, (void *)pml4, *pte);
 }
 
 /*
@@ -381,7 +381,7 @@ teardownidmap(Mach *m)
 	 * report if there were that many, as that is odd.
 	 */
 	for(i = 0; i < 512; i++, va += BIGPGSZ) {
-		if (mmuwalk(UINT2PTR(m->pml4->va), va, 1, &p, nil) != 1)
+		if (mmuwalk(UINT2PTR(machp()->pml4->va), va, 1, &p, nil) != 1)
 			break;
 		if (! *p)
 			break;
@@ -391,7 +391,7 @@ teardownidmap(Mach *m)
 	iprint("Teardown: zapped %d PML1 entries\n", i);
 
 	for(i = 2; i < 4; i++) {
-		if (mmuwalk(UINT2PTR(m->pml4->va), 0, i, &p, nil) != i) {
+		if (mmuwalk(UINT2PTR(machp()->pml4->va), 0, i, &p, nil) != i) {
 			iprint("weird; 0 not mapped at %d\n", i);
 			continue;
 		}
@@ -407,10 +407,10 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 {
 	Mach *m = entrym;
 	/* when we get here, entrym is set to core0 mach. */
-	sys->machptr[m->machno] = m;
+	sys->machptr[machp()->machno] = m;
 	// Very special case for BSP only. Too many things
 	// assume this is set.
-	wrmsr(GSbase, PTR2UINT(&sys->machptr[m->machno]));
+	wrmsr(GSbase, PTR2UINT(&sys->machptr[machp()->machno]));
 	if (machp() != m)
 		panic("m and machp() are different!!\n");
 	assert(sizeof(Mach) <= PGSZ);
@@ -419,7 +419,7 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 	 * Check that our data is on the right boundaries.
 	 * This works because the immediate value is in code.
 	 */
-	if (x != 0x123456) 
+	if (x != 0x123456)
 		panic("Data is not set up correctly\n");
 	memset(edata, 0, end - edata);
 
@@ -428,19 +428,19 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 
 	/*
 	 * ilock via i8250enable via i8250console
-	 * needs m->machno, sys->machptr[] set, and
+	 * needs machp()->machno, sys->machptr[] set, and
 	 * also 'up' set to nil.
 	 */
 	cgapost(sizeof(uintptr_t)*8);
 	memset(m, 0, sizeof(Mach));
 
-	m->machno = 0;
+	machp()->machno = 0;
 	m->online = 1;
 	m->nixtype = NIXTC;
-	sys->machptr[m->machno] = &sys->mach;
+	sys->machptr[machp()->machno] = &sys->mach;
 	m->stack = PTR2UINT(sys->machstk);
 	m->vsvm = sys->vsvmpage;
-	m->externup = (void *)0;
+	up = (void *)0;
 	active.nonline = 1;
 	active.exiting = 0;
 	active.nbooting = 0;
@@ -458,7 +458,7 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 
 	cgainit();
 	i8250console("0");
-	
+
 	consputs = cgaconsputs;
 
 	/* It all ends here. */
@@ -466,9 +466,9 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 	if (machp() != m)
 		panic("After vsvminit, m and machp() are different");
 	fmtinit();
-	
+
 	print("\nHarvey\n");
-	sys->nmach = 1;			
+	sys->nmach = 1;
 
 	if(1){
 		multiboot(mbmagic, mbaddress, 1);
@@ -484,7 +484,7 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 
 	/*
 	 * Mmuinit before meminit because it
-	 * flushes the TLB via m->pml4->pa.
+	 * flushes the TLB via machp()->pml4->pa.
 	 */
 	mmuinit();
 	ioinit();
@@ -494,9 +494,9 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 	archinit();
 	mallocinit();
 
-	/* test malloc. It's easier to find out it's broken here, 
+	/* test malloc. It's easier to find out it's broken here,
 	 * not deep in some call chain.
-	 * See next note. 
+	 * See next note.
 	 *
 	void *v = malloc(1234);
 	hi("v "); put64((uint64_t)v); hi("\n");
@@ -514,7 +514,7 @@ main(uint32_t mbmagic, uint32_t mbaddress)
 	 * things like that completely broken).
 	 */
 if (0){	acpiinit(); hi("	acpiinit();\n");}
-	
+
 	umeminit();
 	trapinit();
 	printinit();
@@ -558,10 +558,10 @@ if (0){	acpiinit(); hi("	acpiinit();\n");}
 void
 init0(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	char buf[2*KNAMELEN];
 
-	m->externup->nerrlab = 0;
+	up->nerrlab = 0;
 
 	/*
 	 * if(consuart == nil)
@@ -573,10 +573,10 @@ init0(void)
 	 * These are o.k. because rootinit is null.
 	 * Then early kproc's will have a root and dot.
 	 */
-	m->externup->slash = namec("#/", Atodir, 0, 0);
-	pathclose(m->externup->slash->path);
-	m->externup->slash->path = newpath("/");
-	m->externup->dot = cclone(m->externup->slash);
+	up->slash = namec("#/", Atodir, 0, 0);
+	pathclose(up->slash->path);
+	up->slash->path = newpath("/");
+	up->dot = cclone(up->slash);
 
 	devtabinit();
 
@@ -608,10 +608,10 @@ bootargs(uintptr_t base)
 	 * Push the boot args onto the stack.
 	 * Make sure the validaddr check in syscall won't fail
 	 * because there are fewer than the maximum number of
-	 * args by subtracting sizeof(m->externup->arg).
+	 * args by subtracting sizeof(up->arg).
 	 */
 	i = oargblen+1;
-	p = UINT2PTR(STACKALIGN(base + BIGPGSZ - sizeof(entrym->externup->arg) - i));
+	p = UINT2PTR(STACKALIGN(base + BIGPGSZ - sizeof(entryup->arg) - i));
 	memmove(p, oargb, i);
 
 	/*
@@ -636,7 +636,7 @@ bootargs(uintptr_t base)
 void
 userinit(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Proc *p;
 	Segment *s;
 	KMap *k;
@@ -663,7 +663,7 @@ userinit(void)
 	 * AMD64 stack must be quad-aligned.
 	 */
 	p->sched.pc = PTR2UINT(init0);
-	p->sched.sp = PTR2UINT(p->kstack+KSTACK-sizeof(m->externup->arg)-sizeof(uintptr_t));
+	p->sched.sp = PTR2UINT(p->kstack+KSTACK-sizeof(up->arg)-sizeof(uintptr_t));
 	p->sched.sp = STACKALIGN(p->sched.sp);
 
 	/*
@@ -727,13 +727,13 @@ confinit(void)
 static void
 shutdown(int ispanic)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int ms, once;
 
 	lock(&active);
 	if(ispanic)
 		active.ispanic = ispanic;
-	else if(m->machno == 0 && m->online == 0)
+	else if(machp()->machno == 0 && m->online == 0)
 		active.ispanic = 0;
 	once = m->online;
 	m->online = 0;
@@ -742,7 +742,7 @@ shutdown(int ispanic)
 	unlock(&active);
 
 	if(once)
-		iprint("cpu%d: exiting\n", m->machno);
+		iprint("cpu%d: exiting\n", machp()->machno);
 
 	spllo();
 	for(ms = 5*1000; ms > 0; ms -= TK2MS(2)){
@@ -751,7 +751,7 @@ shutdown(int ispanic)
 			break;
 	}
 
-	if(active.ispanic && m->machno == 0){
+	if(active.ispanic && machp()->machno == 0){
 		if(cpuserver)
 			delay(30000);
 		else

+ 1 - 1
sys/src/9/amd64pv/mem.h

@@ -1,4 +1,4 @@
-/* 
+/*
  * This file is part of the UCB release of Plan 9. It is subject to the license
  * terms in the LICENSE file found in the top-level directory of this
  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No

+ 72 - 72
sys/src/9/amd64pv/mmu.c

@@ -31,32 +31,32 @@
 void
 mmuflushtlb(uint64_t u)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 
 	m->tlbpurge++;
-	if(m->pml4->daddr){
-		memset(UINT2PTR(m->pml4->va), 0, m->pml4->daddr*sizeof(PTE));
-		m->pml4->daddr = 0;
+	if(machp()->pml4->daddr){
+		memset(UINT2PTR(machp()->pml4->va), 0, machp()->pml4->daddr*sizeof(PTE));
+		machp()->pml4->daddr = 0;
 	}
-	cr3put(m->pml4->pa);
+	cr3put(machp()->pml4->pa);
 }
 
 void
 mmuflush(void)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Mpl pl;
 
 	pl = splhi();
-	m->externup->newtlb = 1;
-	mmuswitch(m->externup);
+	up->newtlb = 1;
+	mmuswitch(up);
 	splx(pl);
 }
 
 static void
 mmuptpfree(Proc* proc, int clear)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int l;
 	PTE *pte;
 	Page **last, *page;
@@ -78,7 +78,7 @@ mmuptpfree(Proc* proc, int clear)
 		proc->mmuptp[l] = nil;
 	}
 
-	m->pml4->daddr = 0;
+	machp()->pml4->daddr = 0;
 }
 
 static void
@@ -117,7 +117,7 @@ dumpptepg(int lvl, uintptr_t pa)
 void
 dumpmmu(Proc *p)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int i;
 	Page *pg;
 
@@ -129,26 +129,26 @@ dumpmmu(Proc *p)
 				" daddr %#ulx next %#p prev %#p\n",
 				pg, pg->va, pg->pa, pg->daddr, pg->next, pg->prev);
 	}
-	print("pml4 %#ullx\n", m->pml4->pa);
-	if(0)dumpptepg(4, m->pml4->pa);
+	print("pml4 %#ullx\n", machp()->pml4->pa);
+	if(0)dumpptepg(4, machp()->pml4->pa);
 }
 
 void
 dumpmmuwalk(uint64_t addr)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int l;
 	PTE *pte, *pml4;
 
-	pml4 = UINT2PTR(m->pml4->va);
+	pml4 = UINT2PTR(machp()->pml4->va);
 	if((l = mmuwalk(pml4, addr, 3, &pte, nil)) >= 0)
-		print("cpu%d: mmu l%d pte %#p = %llux\n", m->machno, l, pte, *pte);
+		print("cpu%d: mmu l%d pte %#p = %llux\n", machp()->machno, l, pte, *pte);
 	if((l = mmuwalk(pml4, addr, 2, &pte, nil)) >= 0)
-		print("cpu%d: mmu l%d pte %#p = %llux\n", m->machno, l, pte, *pte);
+		print("cpu%d: mmu l%d pte %#p = %llux\n", machp()->machno, l, pte, *pte);
 	if((l = mmuwalk(pml4, addr, 1, &pte, nil)) >= 0)
-		print("cpu%d: mmu l%d pte %#p = %llux\n", m->machno, l, pte, *pte);
+		print("cpu%d: mmu l%d pte %#p = %llux\n", machp()->machno, l, pte, *pte);
 	if((l = mmuwalk(pml4, addr, 0, &pte, nil)) >= 0)
-		print("cpu%d: mmu l%d pte %#p = %llux\n", m->machno, l, pte, *pte);
+		print("cpu%d: mmu l%d pte %#p = %llux\n", machp()->machno, l, pte, *pte);
 }
 
 static Page mmuptpfreelist;
@@ -206,7 +206,7 @@ mmuptpalloc(void)
 void
 mmuswitch(Proc* proc)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	PTE *pte;
 	Page *page;
 	Mpl pl;
@@ -222,28 +222,28 @@ mmuswitch(Proc* proc)
 		proc->newtlb = 0;
 	}
 
-	if(m->pml4->daddr){
-		memset(UINT2PTR(m->pml4->va), 0, m->pml4->daddr*sizeof(PTE));
-		m->pml4->daddr = 0;
+	if(machp()->pml4->daddr){
+		memset(UINT2PTR(machp()->pml4->va), 0, machp()->pml4->daddr*sizeof(PTE));
+		machp()->pml4->daddr = 0;
 	}
 
-	pte = UINT2PTR(m->pml4->va);
+	pte = UINT2PTR(machp()->pml4->va);
 	for(page = proc->mmuptp[3]; page != nil; page = page->next){
 		pte[page->daddr] = PPN(page->pa)|PteU|PteRW|PteP;
-		if(page->daddr >= m->pml4->daddr)
-			m->pml4->daddr = page->daddr+1;
-		page->prev = m->pml4;
+		if(page->daddr >= machp()->pml4->daddr)
+			machp()->pml4->daddr = page->daddr+1;
+		page->prev = machp()->pml4;
 	}
 
 	tssrsp0(machp(), STACKALIGN(PTR2UINT(proc->kstack+KSTACK)));
-	cr3put(m->pml4->pa);
+	cr3put(machp()->pml4->pa);
 	splx(pl);
 }
 
 void
 mmurelease(Proc* proc)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	Page *page, *next;
 
 	mmuptpfree(proc, 0);
@@ -264,20 +264,20 @@ mmurelease(Proc* proc)
 	proc->mmuptp[0] = nil;
 
 	tssrsp0(m, STACKALIGN(m->stack+MACHSTKSZ));
-	cr3put(m->pml4->pa);
+	cr3put(machp()->pml4->pa);
 }
 
 static void
 checkpte(uintmem ppn, void *a)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int l;
 	PTE *pte, *pml4;
 	uint64_t addr;
 	char buf[240], *s;
 
 	addr = PTR2UINT(a);
-	pml4 = UINT2PTR(m->pml4->va);
+	pml4 = UINT2PTR(machp()->pml4->va);
 	pte = 0;
 	s = buf;
 	*s = 0;
@@ -300,7 +300,7 @@ checkpte(uintmem ppn, void *a)
 		l, pte, pte?*pte:~0);
 	return;
 Panic:
-	
+
 	seprint(s, buf+sizeof buf,
 		"checkpte: l%d addr %#p ppn %#ullx kaddr %#p pte %#p = %llux",
 		l, a, ppn, KADDR(ppn), pte, pte?*pte:~0);
@@ -315,14 +315,14 @@ Panic:
 static void
 mmuptpcheck(Proc *proc)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int lvl, npgs, i;
 	Page *lp, *p, *pgs[16], *fp;
 	uint idx[16];
 
 	if(proc == nil)
 		return;
-	lp = m->pml4;
+	lp = machp()->pml4;
 	for(lvl = 3; lvl >= 2; lvl--){
 		npgs = 0;
 		for(p = proc->mmuptp[lvl]; p != nil; p = p->next){
@@ -350,7 +350,7 @@ mmuptpcheck(Proc *proc)
 				panic("ptpcheck: wrong prev");
 			}
 		}
-		
+
 	}
 	npgs = 0;
 	for(fp = proc->mmuptp[0]; fp != nil; fp = fp->next){
@@ -381,7 +381,7 @@ pteflags(uint attr)
 }
 
 /*
- * pg->pgszi indicates the page size in m->pgsz[] used for the mapping.
+ * pg->pgszi indicates the page size in machp()->pgsz[] used for the mapping.
  * For the user, it can be either 2*MiB or 1*GiB pages.
  * For 2*MiB pages, we use three levels, not four.
  * For 1*GiB pages, we use two levels.
@@ -389,7 +389,7 @@ pteflags(uint attr)
 void
 mmuput(uintptr_t va, Page *pg, uint attr)
 {
-	Mach *m = machp();
+	Proc *up = machp()->externup;
 	int lvl, user, x, pgsz;
 	PTE *pte;
 	Page *page, *prev;
@@ -403,25 +403,25 @@ mmuput(uintptr_t va, Page *pg, uint attr)
 		panic("mmuput: zero pa");
 
 	if(DBGFLG){
-		snprint(buf, sizeof buf, "cpu%d: up %#p mmuput %#p %#P %#ux\n", 
-			m->machno, m->externup, va, pa, attr);
+		snprint(buf, sizeof buf, "cpu%d: up %#p mmuput %#p %#P %#ux\n",
+			machp()->machno, up, va, pa, attr);
 		print("%s", buf);
 	}
 	assert(pg->pgszi >= 0);
-	pgsz = m->pgsz[pg->pgszi];
+	pgsz = machp()->pgsz[pg->pgszi];
 	if(pa & (pgsz-1))
 		panic("mmuput: pa offset non zero: %#ullx\n", pa);
 	pa |= pteflags(attr);
 
 	pl = splhi();
 	if(DBGFLG)
-		mmuptpcheck(m->externup);
+		mmuptpcheck(up);
 	user = (va < KZERO);
 	x = PTLX(va, 3);
 
-	pte = UINT2PTR(m->pml4->va);
+	pte = UINT2PTR(machp()->pml4->va);