Browse Source

Plan 9 from Bell Labs 2007-11-10

David du Colombier 12 years ago
parent
commit
234739457d

+ 9 - 10
dist/replica/_plan9.db

@@ -1,8 +1,8 @@
 386 - 20000000775 sys sys 1010957353 0
-386/9load - 775 sys sys 1194218336 337604
-386/9loaddebug - 775 sys sys 1194218345 451365
-386/9loadlite - 775 sys sys 1194218348 160884
-386/9loadlitedebug - 775 sys sys 1194218352 236888
+386/9load - 775 sys sys 1194656609 337588
+386/9loaddebug - 775 sys sys 1194656621 451256
+386/9loadlite - 775 sys sys 1194656625 161052
+386/9loadlitedebug - 775 sys sys 1194656629 237051
 386/9pc - 775 sys sys 1192646200 2054406
 386/9pc.gz - 664 sys sys 1192646200 873537
 386/9pccpu - 775 sys sys 1191889923 1749481
@@ -11,7 +11,7 @@
 386/9pcdisk.gz - 664 sys sys 1192741561 973813
 386/9pcf - 775 sys sys 1191889940 2874011
 386/9pcf.gz - 664 sys sys 1191889940 1230163
-386/9pxeload - 775 sys sys 1194218358 337612
+386/9pxeload - 775 sys sys 1194656635 337592
 386/bin - 20000000775 sys sys 1018897690 0
 386/bin/8a - 775 sys sys 1168402260 116604
 386/bin/8c - 775 sys sys 1190520740 367214
@@ -8106,7 +8106,6 @@ sys/src/9/pc/etherm10g2k.i - 664 sys sys 1174590360 957485
 sys/src/9/pc/etherm10g4k.i - 664 sys sys 1174590362 926959
 sys/src/9/pc/ethermii.c - 664 sys sys 1181160689 4668
 sys/src/9/pc/ethermii.h - 664 sys sys 1086873891 3258
-sys/src/9/pc/etherrhine.c - 664 sys sys 1081706478 13799
 sys/src/9/pc/ethersink.c - 664 sys sys 1048644103 1076
 sys/src/9/pc/ethersmc.c - 664 sys sys 1162951986 15116
 sys/src/9/pc/ethervgbe.c - 664 sys sys 1160066496 26838
@@ -9142,7 +9141,7 @@ sys/src/boot/pc/apm.c - 664 sys sys 1015007947 289
 sys/src/boot/pc/bcom.c - 664 sys sys 1194380248 6462
 sys/src/boot/pc/boot.c - 664 sys sys 1130887226 8421
 sys/src/boot/pc/bootld.c - 664 sys sys 1015007948 1801
-sys/src/boot/pc/bootp.c - 664 sys sys 1168307225 12478
+sys/src/boot/pc/bootp.c - 664 sys sys 1194650469 12624
 sys/src/boot/pc/cga.c - 664 sys sys 1015007948 1362
 sys/src/boot/pc/cis.c - 664 sys sys 1144961189 9232
 sys/src/boot/pc/clock.c - 664 sys sys 1194556585 6622
@@ -9184,7 +9183,7 @@ sys/src/boot/pc/etherif.h - 664 sys sys 1174077279 1338
 sys/src/boot/pc/etherigbe.c - 664 sys sys 1191446222 41284
 sys/src/boot/pc/ethermii.c - 664 sys sys 1103641771 4413
 sys/src/boot/pc/ethermii.h - 664 sys sys 1071175087 3259
-sys/src/boot/pc/etherrhine.c - 664 sys sys 1194556608 12640
+sys/src/boot/pc/etherrhine.c - 664 sys sys 1194655423 12729
 sys/src/boot/pc/fns.h - 664 sys sys 1193171343 4880
 sys/src/boot/pc/fs.c - 664 sys sys 1094674483 1509
 sys/src/boot/pc/fs.h - 664 sys sys 1094674488 653
@@ -9197,7 +9196,7 @@ sys/src/boot/pc/kfs.h - 664 sys sys 1032215924 861
 sys/src/boot/pc/kfsboot.c - 664 sys sys 1032215914 4788
 sys/src/boot/pc/l.s - 664 sys sys 1193167045 18213
 sys/src/boot/pc/lib.h - 664 sys sys 1190921452 2847
-sys/src/boot/pc/load.c - 664 sys sys 1194295338 10407
+sys/src/boot/pc/load.c - 664 sys sys 1194649778 10526
 sys/src/boot/pc/mbr.s - 664 sys sys 1015007953 6234
 sys/src/boot/pc/mem.h - 664 sys sys 1190921475 3437
 sys/src/boot/pc/memory.c - 664 sys sys 1019533021 10272
@@ -15235,7 +15234,7 @@ sys/src/libhttpd - 20000000775 sys sys 1045502928 0
 sys/src/libhttpd/alloc.c - 664 sys sys 1014930783 600
 sys/src/libhttpd/checkcontent.c - 664 sys sys 1014930783 771
 sys/src/libhttpd/date.c - 664 sys sys 1045502928 3507
-sys/src/libhttpd/escape.h - 664 sys sys 1014930784 2728
+sys/src/libhttpd/escape.h - 664 sys sys 1194635555 2800
 sys/src/libhttpd/fail.c - 664 sys sys 1014930784 2794
 sys/src/libhttpd/gethead.c - 664 sys sys 1127766499 737
 sys/src/libhttpd/hio.c - 664 sys sys 1177184789 7540

+ 9 - 10
dist/replica/plan9.db

@@ -1,8 +1,8 @@
 386 - 20000000775 sys sys 1010957353 0
-386/9load - 775 sys sys 1194218336 337604
-386/9loaddebug - 775 sys sys 1194218345 451365
-386/9loadlite - 775 sys sys 1194218348 160884
-386/9loadlitedebug - 775 sys sys 1194218352 236888
+386/9load - 775 sys sys 1194656609 337588
+386/9loaddebug - 775 sys sys 1194656621 451256
+386/9loadlite - 775 sys sys 1194656625 161052
+386/9loadlitedebug - 775 sys sys 1194656629 237051
 386/9pc - 775 sys sys 1192646200 2054406
 386/9pc.gz - 664 sys sys 1192646200 873537
 386/9pccpu - 775 sys sys 1191889923 1749481
@@ -11,7 +11,7 @@
 386/9pcdisk.gz - 664 sys sys 1192741561 973813
 386/9pcf - 775 sys sys 1191889940 2874011
 386/9pcf.gz - 664 sys sys 1191889940 1230163
-386/9pxeload - 775 sys sys 1194218358 337612
+386/9pxeload - 775 sys sys 1194656635 337592
 386/bin - 20000000775 sys sys 1018897690 0
 386/bin/8a - 775 sys sys 1168402260 116604
 386/bin/8c - 775 sys sys 1190520740 367214
@@ -8106,7 +8106,6 @@ sys/src/9/pc/etherm10g2k.i - 664 sys sys 1174590360 957485
 sys/src/9/pc/etherm10g4k.i - 664 sys sys 1174590362 926959
 sys/src/9/pc/ethermii.c - 664 sys sys 1181160689 4668
 sys/src/9/pc/ethermii.h - 664 sys sys 1086873891 3258
-sys/src/9/pc/etherrhine.c - 664 sys sys 1081706478 13799
 sys/src/9/pc/ethersink.c - 664 sys sys 1048644103 1076
 sys/src/9/pc/ethersmc.c - 664 sys sys 1162951986 15116
 sys/src/9/pc/ethervgbe.c - 664 sys sys 1160066496 26838
@@ -9142,7 +9141,7 @@ sys/src/boot/pc/apm.c - 664 sys sys 1015007947 289
 sys/src/boot/pc/bcom.c - 664 sys sys 1194380248 6462
 sys/src/boot/pc/boot.c - 664 sys sys 1130887226 8421
 sys/src/boot/pc/bootld.c - 664 sys sys 1015007948 1801
-sys/src/boot/pc/bootp.c - 664 sys sys 1168307225 12478
+sys/src/boot/pc/bootp.c - 664 sys sys 1194650469 12624
 sys/src/boot/pc/cga.c - 664 sys sys 1015007948 1362
 sys/src/boot/pc/cis.c - 664 sys sys 1144961189 9232
 sys/src/boot/pc/clock.c - 664 sys sys 1194556585 6622
@@ -9184,7 +9183,7 @@ sys/src/boot/pc/etherif.h - 664 sys sys 1174077279 1338
 sys/src/boot/pc/etherigbe.c - 664 sys sys 1191446222 41284
 sys/src/boot/pc/ethermii.c - 664 sys sys 1103641771 4413
 sys/src/boot/pc/ethermii.h - 664 sys sys 1071175087 3259
-sys/src/boot/pc/etherrhine.c - 664 sys sys 1194556608 12640
+sys/src/boot/pc/etherrhine.c - 664 sys sys 1194655423 12729
 sys/src/boot/pc/fns.h - 664 sys sys 1193171343 4880
 sys/src/boot/pc/fs.c - 664 sys sys 1094674483 1509
 sys/src/boot/pc/fs.h - 664 sys sys 1094674488 653
@@ -9197,7 +9196,7 @@ sys/src/boot/pc/kfs.h - 664 sys sys 1032215924 861
 sys/src/boot/pc/kfsboot.c - 664 sys sys 1032215914 4788
 sys/src/boot/pc/l.s - 664 sys sys 1193167045 18213
 sys/src/boot/pc/lib.h - 664 sys sys 1190921452 2847
-sys/src/boot/pc/load.c - 664 sys sys 1194295338 10407
+sys/src/boot/pc/load.c - 664 sys sys 1194649778 10526
 sys/src/boot/pc/mbr.s - 664 sys sys 1015007953 6234
 sys/src/boot/pc/mem.h - 664 sys sys 1190921475 3437
 sys/src/boot/pc/memory.c - 664 sys sys 1019533021 10272
@@ -15235,7 +15234,7 @@ sys/src/libhttpd - 20000000775 sys sys 1045502928 0
 sys/src/libhttpd/alloc.c - 664 sys sys 1014930783 600
 sys/src/libhttpd/checkcontent.c - 664 sys sys 1014930783 771
 sys/src/libhttpd/date.c - 664 sys sys 1045502928 3507
-sys/src/libhttpd/escape.h - 664 sys sys 1014930784 2728
+sys/src/libhttpd/escape.h - 664 sys sys 1194635555 2800
 sys/src/libhttpd/fail.c - 664 sys sys 1014930784 2794
 sys/src/libhttpd/gethead.c - 664 sys sys 1127766499 737
 sys/src/libhttpd/hio.c - 664 sys sys 1177184789 7540

+ 12 - 0
dist/replica/plan9.log

@@ -53336,3 +53336,15 @@
 1194557404 2 c sys/src/boot/pc/clock.c - 664 sys sys 1194556585 6622
 1194557404 3 c sys/src/boot/pc/etherrhine.c - 664 sys sys 1194556608 12640
 1194557404 4 c sys/src/boot/pc/io.h - 664 sys sys 1194556593 8134
+1194636605 0 c sys/src/libhttpd/escape.h - 664 sys sys 1194635555 2800
+1194649204 0 c sys/src/boot/pc/etherrhine.c - 664 sys sys 1194647888 12784
+1194651005 0 c sys/src/boot/pc/bootp.c - 664 sys sys 1194650469 12624
+1194651005 1 c sys/src/boot/pc/load.c - 664 sys sys 1194649778 10526
+1194654604 0 c sys/src/boot/pc/etherrhine.c - 664 sys sys 1194654213 14587
+1194656405 0 c sys/src/boot/pc/etherrhine.c - 664 sys sys 1194655423 12729
+1194658204 0 c 386/9load - 775 sys sys 1194656609 337588
+1194658204 1 c 386/9loaddebug - 775 sys sys 1194656621 451256
+1194658204 2 c 386/9loadlite - 775 sys sys 1194656625 161052
+1194658204 3 c 386/9loadlitedebug - 775 sys sys 1194656629 237051
+1194658204 4 c 386/9pxeload - 775 sys sys 1194656635 337592
+1194658204 5 d sys/src/9/pc/etherrhine.c - 664 sys sys 1081706478 0

+ 0 - 734
sys/src/9/pc/etherrhine.c

@@ -1,734 +0,0 @@
- /*
-	Via Rhine driver, written for VT6102.
-	Uses the ethermii to control PHY.
-
-	Currently always copies on both, tx and rx.
-	rx side could be copy-free, and tx-side might be made
-	(almost) copy-free by using (possibly) two descriptors (if it allows
-	arbitrary tx lengths, which it should..): first for alignment and
-	second for rest of the frame. Rx-part should be worth doing.
-*/
-
-#include "u.h"
-#include "../port/lib.h"
-#include "mem.h"
-#include "dat.h"
-#include "fns.h"
-#include "io.h"
-#include "../port/error.h"
-#include "../port/netif.h"
-#include "etherif.h"
-
-#include "ethermii.h"
-
-typedef struct Desc Desc;
-typedef struct Ctlr Ctlr;
-
-enum {
-	Ntxd = 16,
-	Nrxd = 64,
-	Nwait = 50,
-	Ntxstats = 9,
-	Nrxstats = 8,
-	BIGSTR = 8192,
-};
-
-struct Desc {
-	ulong stat;
-	ulong size;
-	ulong addr;
-	ulong next;
-	char *buf;
-	ulong pad[3];
-};
-
-struct Ctlr {
-	Pcidev *pci;
-	int attached;
-	int txused;
-	int txhead;
-	int txtail;
-	int rxtail;
-	ulong port;
-
-	Mii mii;
-
-	ulong txstats[Ntxstats];
-	ulong rxstats[Nrxstats];
-
-	Desc *txd;	/* wants to be aligned on 16-byte boundary */
-	Desc *rxd;
-
-	QLock attachlck;
-	Lock lock;
-};
-
-#define ior8(c, r)	(inb((c)->port+(r)))
-#define ior16(c, r)	(ins((c)->port+(r)))
-#define ior32(c, r)	(inl((c)->port+(r)))
-#define iow8(c, r, b)	(outb((c)->port+(r), (int)(b)))
-#define iow16(c, r, w)	(outs((c)->port+(r), (ushort)(w)))
-#define iow32(c, r, l)	(outl((c)->port+(r), (ulong)(l)))
-
-enum Regs {
-	Eaddr = 0x0,
-	Rcr = 0x6,
-	Tcr = 0x7,
-	Cr = 0x8,
-	Isr = 0xc,
-	Imr = 0xe,
-	McastAddr = 0x10,
-	RxdAddr = 0x18,
-	TxdAddr = 0x1C,
-	Bcr = 0x6e,
-	RhineMiiPhy = 0x6C,
-	RhineMiiSr = 0x6D,
-	RhineMiiCr = 0x70,
-	RhineMiiAddr = 0x71,
-	RhineMiiData = 0x72,
-	Eecsr = 0x74,
-	ConfigB = 0x79,
-	ConfigD = 0x7B,
-	MiscCr = 0x80,
-	HwSticky = 0x83,
-	MiscIsr = 0x84,
-	MiscImr = 0x86,
-	WolCrSet = 0xA0,
-	WolCfgSet = 0xA1,
-	WolCgSet = 0xA3,
-	WolCrClr = 0xA4,
-	PwrCfgClr = 0xA5,
-	WolCgClr = 0xA7,
-};
-
-enum Rcrbits {
-	RxErrX = 1<<0,
-	RxSmall = 1<<1,
-	RxMcast = 1<<2,
-	RxBcast = 1<<3,
-	RxProm = 1<<4,
-	RxFifo64 = 0<<5, RxFifo32 = 1<<5, RxFifo128 = 2<<5, RxFifo256 = 3<<5,
-	RxFifo512 = 4<<5, RxFifo768 = 5<<5, RxFifo1024 = 6<<5,
-	RxFifoStoreForward = 7<<5,
-};
-
-enum Tcrbits {
-	TxLoopback0 = 1<<1,
-	TxLoopback1 = 1<<2,
-	TxBackoff = 1<<3,
-	TxFifo128 = 0<<5, TxFifo256 = 1<<5, TxFifo512 = 2<<5, TxFifo1024 = 3<<5,
-	TxFifoStoreForward = 7<<5,
-};
-
-enum Crbits {
-	Init = 1<<0,
-	Start = 1<<1,
-	Stop = 1<<2,
-	RxOn = 1<<3,
-	TxOn = 1<<4,
-	Tdmd = 1<<5,
-	Rdmd = 1<<6,
-	EarlyRx = 1<<8,
-	Reserved0 = 1<<9,
-	FullDuplex = 1<<10,
-	NoAutoPoll = 1<<11,
-	Reserved1 = 1<<12,
-	Tdmd1 = 1<<13,
-	Rdmd1 = 1<<14,
-	Reset = 1<<15,
-};
-
-enum Isrbits {
-	RxOk = 1<<0,
-	TxOk = 1<<1,
-	RxErr = 1<<2,
-	TxErr = 1<<3,
-	TxBufUdf = 1<<4,
-	RxBufLinkErr = 1<<5,
-	BusErr = 1<<6,
-	CrcOvf = 1<<7,
-	EarlyRxInt = 1<<8,
-	TxFifoUdf = 1<<9,
-	RxFifoOvf = 1<<10,
-	TxPktRace = 1<<11,
-	NoRxbuf = 1<<12,
-	TxCollision = 1<<13,
-	PortCh = 1<<14,
-	GPInt = 1<<15
-};
-
-enum Bcrbits {
-	Dma32 = 0<<0, Dma64 = 1<<0, Dma128 = 2<<0,
-	Dma256 = 3<<0, Dma512 = 4<<0, Dma1024 = 5<<0,
-	DmaStoreForward = 7<<0,
-	DupRxFifo0 = 1<<3, DupRxFifo1 = 1<<4, DupRxFifo2 = 1<<5,
-	ExtraLed = 1<<6,
-	MediumSelect = 1<<7,
-	PollTimer0 = 1<<8, PollTimer1 = 1<<9, PollTimer2 = 1<<10,
-	DupTxFifo0 = 1<<11, DupTxFifo1 = 1<<12, DupTxFifo2 = 1<<13,
-};
-
-enum Eecsrbits {
-	EeAutoLoad = 1<<5,
-};
-
-enum MiscCrbits {
-	Timer0Enable= 1<<0,
-	Timer0Suspend = 1<<1,
-	HalfDuplexFlowControl = 1<<2,
-	FullDuplexFlowControl = 1<<3,
-	Timer1Enable = 1<<8,
-	ForceSoftReset = 1<<14,
-};
-
-enum HwStickybits {
-	StickyDS0 = 1<<0,
-	StickyDS1 = 1<<1,
-	WOLEna = 1<<2,
-	WOLStat = 1<<3,
-};
-
-enum WolCgbits {
-	PmeOvr = 1<<7,
-};
-
-enum Descbits {
-	OwnNic = 1<<31,		/* stat */
-	TxAbort = 1<<8,		/* stat */
-	TxError = 1<<15,		/* stat */
-	RxChainbuf = 1<<10,	/* stat */
-	RxChainStart = 1<<9,	/* stat */
-	RxChainEnd = 1<<8,		/* stat */
-	Chainbuf = 1<<15,		/* size rx & tx*/
-	TxDisableCrc = 1<<16,	/* size */
-	TxChainStart = 1<<21,	/* size */
-	TxChainEnd = 1<<22,	/* size */
-	TxInt = 1<<23,			/* size */
-};
-
-enum ConfigDbits {
-	BackoffOptional = 1<<0,
-	BackoffAMD = 1<<1,
-	BackoffDEC = 1<<2,
-	BackoffRandom = 1<<3,
-	PmccTestMode = 1<<4,
-	PciReadlineCap = 1<<5,
-	DiagMode = 1<<6,
-	MmioEnable = 1<<7,
-};
-
-enum ConfigBbits {
-	LatencyTimer = 1<<0,
-	WriteWaitState = 1<<1,
-	ReadWaitState = 1<<2,
-	RxArbit = 1<<3,
-	TxArbit = 1<<4,
-	NoMemReadline = 1<<5,
-	NoParity = 1<<6,
-	NoTxQueuing = 1<<7,
-};
-
-enum RhineMiiCrbits {
-	Mdc = 1<<0,
-	Mdi = 1<<1,
-	Mdo = 1<<2,
-	Mdout = 1<<3,
-	Mdpm = 1<<4,
-	Wcmd = 1<<5,
-	Rcmd = 1<<6,
-	Mauto = 1<<7,
-};
-
-enum RhineMiiSrbits {
-	Speed10M = 1<<0,
-	LinkFail = 1<<1,
-	PhyError = 1<<3,
-	DefaultPhy = 1<<4,
-	ResetPhy = 1<<7,
-};
-
-enum RhineMiiAddrbits {
-	Mdone = 1<<5,
-	Msrcen = 1<<6,
-	Midle = 1<<7,
-};
-
-static char *
-txstatnames[Ntxstats] = {
-	"aborts (excess collisions)",
-	"out of window collisions",
-	"carrier sense losses",
-	"fifo underflows",
-	"invalid descriptor format or underflows",
-	"system errors",
-	"reserved",
-	"transmit errors",
-	"collisions",
-};
-
-static char *
-rxstatnames[Nrxstats] = {
-	"receiver errors",
-	"crc errors",
-	"frame alignment errors",
-	"fifo overflows",
-	"long packets",
-	"run packets",
-	"system errors",
-	"buffer underflows",
-};
-
-static void
-attach(Ether *edev)
-{
-	Ctlr *ctlr;
-	Desc *txd, *rxd, *td, *rd;
-	Mii *mi;
-	MiiPhy *phy;
-	int i, s;
-	
-	ctlr = edev->ctlr;
-	qlock(&ctlr->attachlck);
-	if (ctlr->attached == 0) {
-		txd = ctlr->txd;
-		rxd = ctlr->rxd;
-		for (i = 0; i < Ntxd; ++i) {
-			td = &txd[i];
-			td->next = PCIWADDR(&txd[(i+1) % Ntxd]);
-			td->buf = xspanalloc(sizeof(Etherpkt)+4, 4, 0);
-			td->addr = PCIWADDR(td->buf);
-			td->size = 0;
-			coherence();
-			td->stat = 0;
-		}
-		for (i = 0; i < Nrxd; ++i) {
-			rd = &rxd[i];
-			rd->next = PCIWADDR(&rxd[(i+1) % Nrxd]);
-			rd->buf = xspanalloc(sizeof(Etherpkt)+4, 4, 0);
-			rd->addr = PCIWADDR(rd->buf);
-			rd->size = sizeof(Etherpkt)+4;
-			coherence();
-			rd->stat = OwnNic;
-		}
-
-		ctlr->txhead = ctlr->txtail = ctlr->rxtail = 0;
-		mi = &ctlr->mii;
-		miistatus(mi);
-		phy = mi->curphy;
-		s = splhi();
-		iow32(ctlr, TxdAddr, PCIWADDR(&txd[0]));
-		iow32(ctlr, RxdAddr, PCIWADDR(&rxd[0]));
-		iow16(ctlr, Cr, (phy->fd ? FullDuplex : 0) | NoAutoPoll | TxOn | RxOn | Start | Rdmd);
-		iow16(ctlr, Isr, 0xFFFF);
-		iow16(ctlr, Imr, 0xFFFF);
-		iow8(ctlr, MiscIsr, 0xFF);
-		iow8(ctlr, MiscImr, ~(3<<5));
-		splx(s);
-	}
-	ctlr->attached++;
-	qunlock(&ctlr->attachlck);
-}
-
-static void
-txstart(Ether *edev)
-{
-	Ctlr *ctlr;
-	Desc *txd, *td;
-	Block *b;
-	int i, txused, n;
-	ulong size;
-
-	ctlr = edev->ctlr;
-
-	txd = ctlr->txd;
-	i = ctlr->txhead;
-	txused = ctlr->txused;
-	n = 0;
-	while (txused < Ntxd) {
-		if ((b = qget(edev->oq)) == nil)
-			break;
-
-		td = &txd[i];
-
-		size = BLEN(b);
-		memmove(td->buf, b->rp, size);
-		freeb(b);
-		td->size = size | TxChainStart | TxChainEnd | TxInt; /* could reduce number of ints here */
-		coherence();
-		td->stat = OwnNic;
-		i = (i + 1) % Ntxd;
-		txused++;
-		n++;
-	}
-	if (n)
-		iow16(ctlr, Cr, ior16(ctlr, Cr) | Tdmd);
-
-	ctlr->txhead = i;
-	ctlr->txused = txused;
-}
-
-static void
-transmit(Ether *edev)
-{
-	Ctlr *ctlr;
-	ctlr = edev->ctlr;
-	ilock(&ctlr->lock);
-	txstart(edev);
-	iunlock(&ctlr->lock);
-}
-
-static void
-txcomplete(Ether *edev)
-{
-	Ctlr *ctlr;
-	Desc *txd, *td;
-	int i, txused, j;
-	ulong stat;
-
-	ctlr = edev->ctlr;
- 	txd = ctlr->txd;
-	txused = ctlr->txused;
-	i = ctlr->txtail;
-	while (txused > 0) {
-		td = &txd[i];
-		stat = td->stat;
-
-		if (stat & OwnNic)
-			break;
-
-		ctlr->txstats[Ntxstats-1] += stat & 0xF;
-		for (j = 0; j < Ntxstats-1; ++j)
-			if (stat & (1<<(j+8)))
-				ctlr->txstats[j]++;
-
-		i = (i + 1) % Ntxd;
-		txused--;
-	}
-	ctlr->txused = txused;
-	ctlr->txtail = i;
-
-	if (txused <= Ntxd/2)
-		txstart(edev);
-}
-
-static void
-interrupt(Ureg *, void *arg)
-{
-	Ether *edev;
-	Ctlr *ctlr;
-	ushort  isr, misr;
-	ulong stat;
-	Desc *rxd, *rd;
-	int i, n, j;
-
-	edev = (Ether*)arg;
-	ctlr = edev->ctlr;
-	iow16(ctlr, Imr, 0);
-	isr = ior16(ctlr, Isr);
-	iow16(ctlr, Isr, 0xFFFF);
-	misr = ior16(ctlr, MiscIsr) & ~(3<<5); /* don't care about used defined ints */
-
-	if (isr & RxOk) {
-		Block *b;
-		int size;
-		rxd = ctlr->rxd;
-		i = ctlr->rxtail;
-
-		n = 0;
-		while ((rxd[i].stat & OwnNic) == 0) {
-			rd = &rxd[i];
-			stat = rd->stat;
-			for (j = 0; j < Nrxstats; ++j)
-				if (stat & (1<<j))
-					ctlr->rxstats[j]++;
-
-			if (stat & 0xFF)
-				iprint("rx: %lux\n", stat & 0xFF);
-
-			size = ((rd->stat>>16) & 2047) - 4;
-			b = iallocb(sizeof(Etherpkt));
-			memmove(b->wp, rd->buf, size);
-			b->wp += size;
-			etheriq(edev, b, 1);
-			rd->size = sizeof(Etherpkt)+4;
-			coherence();
-			rd->stat = OwnNic;
-			i = (i + 1) % Nrxd;
-			n++;
-		}
-		if (n)
-			iow16(ctlr, Cr, ior16(ctlr, Cr) | Rdmd);
-		ctlr->rxtail = i;
-		isr &= ~RxOk;
-	}
-	if (isr & TxOk) {
-		txcomplete(edev);
-		isr &= ~TxOk;
-	}
-	if (isr | misr)
-		iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n", isr, misr);
-
-	iow16(ctlr, Imr, 0xFFFF);
-}
-
-static void
-promiscuous(void *arg, int enable)
-{
-	Ether *edev;
-	Ctlr *ctlr;
-
-	edev = arg;
-	ctlr = edev->ctlr;
-	ilock(&ctlr->lock);
-	iow8(ctlr, Rcr, (ior8(ctlr, Rcr) & ~(RxProm|RxBcast)) |
-		(enable ? RxProm : RxBcast));
-	iunlock(&ctlr->lock);
-}
-
-static int
-miiread(Mii *mii, int phy, int reg)
-{
-	Ctlr *ctlr;
-	int n;
-
-	ctlr = mii->ctlr;
-	
-	n = Nwait;
-	while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
-		microdelay(1);
-	if (n == Nwait)
-		iprint("etherrhine: miiread: timeout\n");
-
-	iow8(ctlr, RhineMiiCr, 0);
-	iow8(ctlr, RhineMiiPhy, phy);
-	iow8(ctlr, RhineMiiAddr, reg);
-	iow8(ctlr, RhineMiiCr, Rcmd);
-
-	n = Nwait;
-	while (n-- && ior8(ctlr, RhineMiiCr) & Rcmd)
-		microdelay(1);
-	if (n == Nwait)
-		iprint("etherrhine: miiread: timeout\n");
-
-	n = ior16(ctlr, RhineMiiData);
-
-	return n;
-}
-
-static int
-miiwrite(Mii *mii, int phy, int reg, int data)
-{
-	int n;
-	Ctlr *ctlr;
-
-	ctlr = mii->ctlr;
-
-	n = Nwait;
-	while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
-		microdelay(1);
-	if (n == Nwait)
-		iprint("etherrhine: miiwrite: timeout\n");
-
-	iow8(ctlr, RhineMiiCr, 0);
-	iow8(ctlr, RhineMiiPhy, phy);
-	iow8(ctlr, RhineMiiAddr, reg);
-	iow16(ctlr, RhineMiiData, data);
-	iow8(ctlr, RhineMiiCr, Wcmd);
-
-	n = Nwait;
-	while (n-- && ior8(ctlr, RhineMiiCr) & Wcmd)
-		microdelay(1);
-	if (n == Nwait)
-		iprint("etherrhine: miiwrite: timeout\n");
-
-	return 0;
-}
-
-/* multicast already on, don't need to do anything */
-static void
-multicast(void*, uchar*, int)
-{
-}
-
-static void
-shutdown(Ether *edev)
-{
-	int i;
-	Ctlr *ctlr = edev->ctlr;
-
-	ilock(&ctlr->lock);
-	pcisetbme(ctlr->pci);
-
-	iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
-	iow16(ctlr, Cr, ior16(ctlr, Cr) | Reset);
-
-	for (i = 0; i < Nwait; ++i) {
-		if ((ior16(ctlr, Cr) & Reset) == 0)
-			break;
-		delay(5);
-	}
-	if (i == Nwait)
-		iprint("etherrhine: reset timeout\n");
-	iunlock(&ctlr->lock);
-}
-
-static void
-init(Ether *edev)
-{
-	Ctlr *ctlr;
-	MiiPhy *phy;
-	int i;
-
-	shutdown(edev);
-
-	ctlr = edev->ctlr;
-	ilock(&ctlr->lock);
-	iow8(ctlr, Eecsr, ior8(ctlr, Eecsr) | EeAutoLoad);
-	for (i = 0; i < Nwait; ++i) {
-		if ((ior8(ctlr, Eecsr) & EeAutoLoad) == 0)
-			break;
-		delay(5);
-	}
-	if (i == Nwait)
-		iprint("etherrhine: eeprom autoload timeout\n");
-
-	for (i = 0; i < Eaddrlen; ++i)
-		edev->ea[i] = ior8(ctlr, Eaddr + i);
-
-	ctlr->mii.mir = miiread;
-	ctlr->mii.miw = miiwrite;
-	ctlr->mii.ctlr = ctlr;
-
-	if(mii(&ctlr->mii, ~0) == 0 || ctlr->mii.curphy == nil){
-		iprint("etherrhine: init mii failure\n");
-		return;
-	}
-	for (i = 0; i < NMiiPhy; ++i)
-		if (ctlr->mii.phy[i])
-			if (ctlr->mii.phy[i]->oui != 0xFFFFF)
-				ctlr->mii.curphy = ctlr->mii.phy[i];
-
-	miistatus(&ctlr->mii);
-	phy = ctlr->mii.curphy;
-	edev->mbps = phy->speed;
-
-	iow16(ctlr, Imr, 0);
-	iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
-	iow8(ctlr, Rcr, ior8(ctlr, Rcr) | RxMcast);
-
-	iunlock(&ctlr->lock);
-}
-
-static Pcidev *
-rhinematch(ulong)
-{
-	static int nrhines = 0;
-	int nfound = 0;
-	Pcidev *p = nil;
-
-	while (p = pcimatch(p, 0x1106, 0))
-		if (p->did == 0x3065)
-			if (++nfound > nrhines) {
-				nrhines++;
-				break;
-			}
-	return p;
-}
-static long
-ifstat(Ether* edev, void* a, long n, ulong offset)
-{
-	int l = 0, i;
-	char *p;
-	Ctlr *ctlr;
-	ctlr = edev->ctlr;
-	p = malloc(BIGSTR);
-
-	for (i = 0; i < Ntxstats; ++i)
-		if (txstatnames[i])
-			l += snprint(p+l, BIGSTR - l, "tx: %s: %lud\n", txstatnames[i], ctlr->txstats[i]);
-
-	for (i = 0; i < Nrxstats; ++i)
-		if (rxstatnames[i])
-			l += snprint(p+l, BIGSTR - l, "rx: %s: %lud\n", rxstatnames[i], ctlr->rxstats[i]);
-
-/*
-	for (i = 0; i < NMiiPhyr; ++i) {
-		if ((i % 8) == 0)
-			l += snprint(p + l, BIGSTR - l, "\nmii 0x%02x:", i);
-		reg=miimir(&ctlr->mii, i);
-		reg=miimir(&ctlr->mii, i);
-		l += snprint(p + l, BIGSTR - l, " %4ux", reg);
-	}
-
-	for (i = 0; i < 0x100; i+=1) {
-		if ((i % 16) == 0)
-			l += snprint(p + l, BIGSTR - l, "\nreg 0x%02x:", i);
-		else if ((i % 2) == 0)
-			l += snprint(p + l, BIGSTR - l, " ");
-		reg=ior8(ctlr, i);
-		l += snprint(p + l, BIGSTR - l, "%02x", reg);
-	}
-	l += snprint(p + l, BIGSTR - l, " \n");
-*/
-
-
-	n = readstr(offset, a, n, p);
-	free(p);
-
-	return n;
-}
-
-static int
-pnp(Ether *edev)
-{
-	Pcidev *p;
-	Ctlr *ctlr;
-	ulong port;
-	ulong size;
-
-	p = rhinematch(edev->port);
-	if (p == nil)
-		return -1;
-
-	port = p->mem[0].bar & ~1;
-	size = p->mem[0].size;
-	if (ioalloc(port, size, 0, "rhine") < 0) {
-		print("etherrhine: couldn't allocate port %lud\n", port);
-		return -1;
-	}
-
-	if ((ctlr = malloc(sizeof(Ctlr))) == nil) {
-		print("etherrhine: couldn't allocate memory for ctlr\n");
-		return -1;
-	}
-	memset(ctlr, 0, sizeof(Ctlr));
-	ctlr->txd = xspanalloc(sizeof(Desc) * Ntxd, 16, 0);
-	ctlr->rxd = xspanalloc(sizeof(Desc) * Nrxd, 16, 0);
-		
-	ctlr->pci = p;
-	ctlr->port = port;
-
-	edev->ctlr = ctlr;
-	edev->port = ctlr->port;
-	edev->irq = p->intl;
-	edev->tbdf = p->tbdf;
-
-	init(edev);
-
-	edev->interrupt = interrupt;
-	edev->arg = edev;
-
-	edev->attach = attach;
-	edev->transmit = transmit;
-	edev->ifstat = ifstat;
-	edev->promiscuous = promiscuous;
-	edev->multicast = multicast;
-	edev->shutdown = shutdown;
-	return 0;
-}
-
-void
-etherrhinelink(void)
-{
-	addethercard("rhine", pnp);
-}

+ 6 - 0
sys/src/boot/pc/bootp.c

@@ -7,6 +7,8 @@
 
 #include "ip.h"
 
+extern int debugload;
+
 uchar broadcast[Eaddrlen] = {
 	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 };
@@ -441,6 +443,8 @@ bootpopen(int ctlrno, char *file, Bootp *rep, int dotftpopen)
 	uchar *ea;
 	char name[128], *filename, *sysname;
 
+	if (debugload)
+		print("bootpopen: ether%d!%s...", ctlrno, file);
 	if((ea = etheraddr(ctlrno)) == 0){
 		print("invalid ctlrno %d\n", ctlrno);
 		return -1;
@@ -638,6 +642,8 @@ pxegetfspart(int ctlrno, char* part, int)
 		return nil;
 	if(ctlrno >= MaxEther)
 		return nil;
+	if(iniread && getconf("*pxeini") != nil)
+		return nil;
 
 	pxether[ctlrno].fs.dev = ctlrno;
 	pxether[ctlrno].fs.diskread = pxediskread;

+ 244 - 273
sys/src/boot/pc/etherrhine.c

@@ -1,4 +1,4 @@
- /*
+/*
 	Via Rhine driver, written for VT6102.
 	Uses the ethermii to control PHY.
 
@@ -7,7 +7,7 @@
 	(almost) copy-free by using (possibly) two descriptors (if it allows
 	arbitrary tx lengths, which it should..): first for alignment and
 	second for rest of the frame. Rx-part should be worth doing.
-*/
+ */
 #include "u.h"
 #include "lib.h"
 #include "mem.h"
@@ -23,261 +23,223 @@ typedef struct QLock { int r; } QLock;
 #include "etherif.h"
 #include "ethermii.h"
 
-typedef struct Desc Desc;
-typedef struct Ctlr Ctlr;
-
 enum {
 	Ntxd = 4,
 	Nrxd = 4,
 	Nwait = 50,
-	Ntxstats = 9,
-	Nrxstats = 8,
 	BIGSTR = 8192,
 };
 
+typedef struct Desc Desc;
+typedef struct Ctlr Ctlr;
+
 struct Desc {
-	ulong stat;
-	ulong size;
-	ulong addr;
-	ulong next;
-	char *buf;
-	ulong pad[3];
+	ulong	stat;
+	ulong	size;
+	ulong	addr;
+	ulong	next;
+	char	*buf;
+	ulong	pad[3];
 };
 
 struct Ctlr {
-	Pcidev *pci;
-	int attached;
-	int txused;
-	int txhead;
-	int txtail;
-	int rxtail;
-	ulong port;
-
-	Mii mii;
+	Pcidev	*pci;
+	int	attached;
+	int	txused;
+	int	txhead;
+	int	txtail;
+	int	rxtail;
+	ulong	port;
 
-	ulong txstats[Ntxstats];
-	ulong rxstats[Nrxstats];
+	Mii	mii;
 
-	Desc *txd;	/* wants to be aligned on 16-byte boundary */
-	Desc *rxd;
+	Desc	*txd;		/* wants to be aligned on 16-byte boundary */
+	Desc	*rxd;
 
-	QLock attachlck;
-	Lock tlock;
+	QLock	attachlck;
+	Lock	tlock;
 };
 
 #define ior8(c, r)	(inb((c)->port+(r)))
+#define iow8(c, r, b)	(outb((c)->port+(r), (int)(b)))
 #define ior16(c, r)	(ins((c)->port+(r)))
 #define ior32(c, r)	(inl((c)->port+(r)))
-#define iow8(c, r, b)	(outb((c)->port+(r), (int)(b)))
 #define iow16(c, r, w)	(outs((c)->port+(r), (ushort)(w)))
 #define iow32(c, r, l)	(outl((c)->port+(r), (ulong)(l)))
 
+/* names used everywhere else */
+#define csr8r ior8
+#define csr8w iow8
+#define csr16r ior16
+#define csr16w iow16
+#define csr32r ior32
+#define csr32w iow32
+
 enum Regs {
-	Eaddr = 0x0,
-	Rcr = 0x6,
-	Tcr = 0x7,
-	Cr = 0x8,
-	Isr = 0xc,
-	Imr = 0xe,
-	McastAddr = 0x10,
-	RxdAddr = 0x18,
-	TxdAddr = 0x1C,
-	Bcr = 0x6e,
-	RhineMiiPhy = 0x6C,
-	RhineMiiSr = 0x6D,
-	RhineMiiCr = 0x70,
-	RhineMiiAddr = 0x71,
-	RhineMiiData = 0x72,
-	Eecsr = 0x74,
-	ConfigB = 0x79,
-	ConfigD = 0x7B,
-	MiscCr = 0x80,
-	HwSticky = 0x83,
-	MiscIsr = 0x84,
-	MiscImr = 0x86,
-	WolCrSet = 0xA0,
-	WolCfgSet = 0xA1,
-	WolCgSet = 0xA3,
-	WolCrClr = 0xA4,
-	PwrCfgClr = 0xA5,
-	WolCgClr = 0xA7,
+	Eaddr		= 0x0,
+	Rcr		= 0x6,
+	Tcr		= 0x7,
+	Cr		= 0x8,
+	Isr		= 0xc,
+	Imr		= 0xe,
+	McastAddr	= 0x10,
+	RxdAddr		= 0x18,
+	TxdAddr		= 0x1C,
+	Bcr0		= 0x6E,		/* Bus Control */
+	Bcr1		= 0x6F,
+	RhineMiiPhy	= 0x6C,
+	RhineMiiSr	= 0x6D,
+	RhineMiiCr	= 0x70,
+	RhineMiiAddr	= 0x71,
+	RhineMiiData	= 0x72,
+	Eecsr		= 0x74,
+	ConfigB		= 0x79,
+	ConfigD		= 0x7B,
+	MiscCr		= 0x80,
+	HwSticky	= 0x83,
+	MiscIsr		= 0x84,
+	MiscImr		= 0x86,
+	WolCrSet	= 0xA0,
+	WolCfgSet	= 0xA1,
+	WolCgSet	= 0xA3,
+	WolCrClr	= 0xA4,
+	PwrCfgClr	= 0xA5,
+	WolCgClr	= 0xA7,
 };
 
-enum Rcrbits {
-	RxErrX = 1<<0,
-	RxSmall = 1<<1,
-	RxMcast = 1<<2,
-	RxBcast = 1<<3,
-	RxProm = 1<<4,
-	RxFifo64 = 0<<5, RxFifo32 = 1<<5, RxFifo128 = 2<<5, RxFifo256 = 3<<5,
-	RxFifo512 = 4<<5, RxFifo768 = 5<<5, RxFifo1024 = 6<<5,
-	RxFifoStoreForward = 7<<5,
+enum {					/* Rcr */
+	Sep		= 0x01,		/* Accept Error Packets */
+	Ar		= 0x02,		/* Accept Small Packets */
+	Am		= 0x04,		/* Accept Multicast */
+	Ab		= 0x08,		/* Accept Broadcast */
+	RxBcast		= Ab,
+	Prom		= 0x10,		/* Accept Physical Address Packets */
+	RxProm		= Prom,
+	RrftMASK	= 0xE0,		/* Receive FIFO Threshold */
+	RrftSHIFT	= 5,
+	Rrft64		= 0<<RrftSHIFT,
+	Rrft32		= 1<<RrftSHIFT,
+	Rrft128		= 2<<RrftSHIFT,
+	Rrft256		= 3<<RrftSHIFT,
+	Rrft512		= 4<<RrftSHIFT,
+	Rrft768		= 5<<RrftSHIFT,
+	Rrft1024	= 6<<RrftSHIFT,
+	RrftSAF		= 7<<RrftSHIFT,
 };
 
-enum Tcrbits {
-	TxLoopback0 = 1<<1,
-	TxLoopback1 = 1<<2,
-	TxBackoff = 1<<3,
-	TxFifo128 = 0<<5, TxFifo256 = 1<<5, TxFifo512 = 2<<5, TxFifo1024 = 3<<5,
-	TxFifoStoreForward = 7<<5,
+enum {					/* Tcr */
+	Lb0		= 0x02,		/* Loopback Mode */
+	Lb1		= 0x04,
+	Ofset		= 0x08,		/* Back-off Priority Selection */
+	RtsfMASK	= 0xE0,		/* Transmit FIFO Threshold */
+	RtsfSHIFT	= 5,
+	Rtsf128		= 0<<RtsfSHIFT,
+	Rtsf256		= 1<<RtsfSHIFT,
+	Rtsf512		= 2<<RtsfSHIFT,
+	Rtsf1024	= 3<<RtsfSHIFT,
+	RtsfSAF		= 7<<RtsfSHIFT,
 };
 
 enum Crbits {
-	Init = 1<<0,
-	Start = 1<<1,
-	Stop = 1<<2,
-	RxOn = 1<<3,
-	TxOn = 1<<4,
-	Tdmd = 1<<5,
-	Rdmd = 1<<6,
-	EarlyRx = 1<<8,
-	Reserved0 = 1<<9,
-	FullDuplex = 1<<10,
-	NoAutoPoll = 1<<11,
-	Reserved1 = 1<<12,
-	Tdmd1 = 1<<13,
-	Rdmd1 = 1<<14,
-	Reset = 1<<15,
+	Init		= 1<<0,
+	Start		= 1<<1,
+	Stop		= 1<<2,
+	RxOn		= 1<<3,
+	TxOn		= 1<<4,
+	Tdmd		= 1<<5,
+	Rdmd		= 1<<6,
+	EarlyRx		= 1<<8,
+	Reserved0	= 1<<9,
+	FullDuplex	= 1<<10,
+	NoAutoPoll	= 1<<11,
+	Reserved1	= 1<<12,
+	Tdmd1		= 1<<13,
+	Rdmd1		= 1<<14,
+	Reset		= 1<<15,
 };
 
 enum Isrbits {
-	RxOk = 1<<0,
-	TxOk = 1<<1,
-	RxErr = 1<<2,
-	TxErr = 1<<3,
-	TxBufUdf = 1<<4,
-	RxBufLinkErr = 1<<5,
-	BusErr = 1<<6,
-	CrcOvf = 1<<7,
-	EarlyRxInt = 1<<8,
-	TxFifoUdf = 1<<9,
-	RxFifoOvf = 1<<10,
-	TxPktRace = 1<<11,
-	NoRxbuf = 1<<12,
-	TxCollision = 1<<13,
-	PortCh = 1<<14,
-	GPInt = 1<<15
+	RxOk		= 1<<0,
+	TxOk		= 1<<1,
+	RxErr		= 1<<2,
+	TxErr		= 1<<3,
+	TxBufUdf	= 1<<4,
+	RxBufLinkErr	= 1<<5,
+	BusErr		= 1<<6,
+	CrcOvf		= 1<<7,
+	EarlyRxInt	= 1<<8,
+	TxFifoUdf	= 1<<9,
+	RxFifoOvf	= 1<<10,
+	TxPktRace	= 1<<11,
+	NoRxbuf		= 1<<12,
+	TxCollision	= 1<<13,
+	PortCh		= 1<<14,
+	GPInt		= 1<<15,
 };
 
-enum Bcrbits {
-	Dma32 = 0<<0, Dma64 = 1<<0, Dma128 = 2<<0,
-	Dma256 = 3<<0, Dma512 = 4<<0, Dma1024 = 5<<0,
-	DmaStoreForward = 7<<0,
-	DupRxFifo0 = 1<<3, DupRxFifo1 = 1<<4, DupRxFifo2 = 1<<5,
-	ExtraLed = 1<<6,
-	MediumSelect = 1<<7,
-	PollTimer0 = 1<<8, PollTimer1 = 1<<9, PollTimer2 = 1<<10,
-	DupTxFifo0 = 1<<11, DupTxFifo1 = 1<<12, DupTxFifo2 = 1<<13,
+enum {					/* Bcr0 */
+	DmaMASK		= 0x07,		/* DMA Length */
+	DmaSHIFT	= 0,
+	Dma32		= 0<<DmaSHIFT,
+	Dma64		= 1<<DmaSHIFT,
+	Dma128		= 2<<DmaSHIFT,
+	Dma256		= 3<<DmaSHIFT,
+	Dma512		= 4<<DmaSHIFT,
+	Dma1024		= 5<<DmaSHIFT,
+	DmaSAF		= 7<<DmaSHIFT,
+	CrftMASK	= 0x38,		/* Rx FIFO Threshold */
+	CrftSHIFT	= 3,
+	Crft64		= 1<<CrftSHIFT,
+	Crft128		= 2<<CrftSHIFT,
+	Crft256		= 3<<CrftSHIFT,
+	Crft512		= 4<<CrftSHIFT,
+	Crft1024	= 5<<CrftSHIFT,
+	CrftSAF		= 7<<CrftSHIFT,
+	Extled		= 0x40,		/* Extra LED Support Control */
+	Med2		= 0x80,		/* Medium Select Control */
 };
 
-enum Eecsrbits {
-	EeAutoLoad = 1<<5,
+enum {					/* Bcr1 */
+	PotMASK		= 0x07,		/* Polling Timer Interval */
+	PotSHIFT	= 0,
+	CtftMASK	= 0x38,		/* Tx FIFO Threshold */
+	CtftSHIFT	= 3,
+	Ctft64		= 1<<CtftSHIFT,
+	Ctft128		= 2<<CtftSHIFT,
+	Ctft256		= 3<<CtftSHIFT,
+	Ctft512		= 4<<CtftSHIFT,
+	Ctft1024	= 5<<CtftSHIFT,
+	CtftSAF		= 7<<CtftSHIFT,
 };
 
-enum MiscCrbits {
-	Timer0Enable= 1<<0,
-	Timer0Suspend = 1<<1,
-	HalfDuplexFlowControl = 1<<2,
-	FullDuplexFlowControl = 1<<3,
-	Timer1Enable = 1<<8,
-	ForceSoftReset = 1<<14,
-};
 
-enum HwStickybits {
-	StickyDS0 = 1<<0,
-	StickyDS1 = 1<<1,
-	WOLEna = 1<<2,
-	WOLStat = 1<<3,
-};
-
-enum WolCgbits {
-	PmeOvr = 1<<7,
+enum Eecsrbits {
+	EeAutoLoad	= 1<<5,
 };
 
 enum Descbits {
-	OwnNic = 1<<31,		/* stat */
-	TxAbort = 1<<8,		/* stat */
-	TxError = 1<<15,		/* stat */
-	RxChainbuf = 1<<10,	/* stat */
-	RxChainStart = 1<<9,	/* stat */
-	RxChainEnd = 1<<8,		/* stat */
-	Chainbuf = 1<<15,		/* size rx & tx*/
-	TxDisableCrc = 1<<16,	/* size */
-	TxChainStart = 1<<21,	/* size */
-	TxChainEnd = 1<<22,	/* size */
-	TxInt = 1<<23,			/* size */
-};
-
-enum ConfigDbits {
-	BackoffOptional = 1<<0,
-	BackoffAMD = 1<<1,
-	BackoffDEC = 1<<2,
-	BackoffRandom = 1<<3,
-	PmccTestMode = 1<<4,
-	PciReadlineCap = 1<<5,
-	DiagMode = 1<<6,
-	MmioEnable = 1<<7,
-};
-
-enum ConfigBbits {
-	LatencyTimer = 1<<0,
-	WriteWaitState = 1<<1,
-	ReadWaitState = 1<<2,
-	RxArbit = 1<<3,
-	TxArbit = 1<<4,
-	NoMemReadline = 1<<5,
-	NoParity = 1<<6,
-	NoTxQueuing = 1<<7,
+	OwnNic		= 1<<31,	/* stat */
+	TxAbort		= 1<<8,		/* stat */
+	TxError		= 1<<15,	/* stat */
+	RxChainbuf	= 1<<10,	/* stat */
+	RxChainStart	= 1<<9,		/* stat */
+	RxChainEnd	= 1<<8,		/* stat */
+	Chainbuf	= 1<<15,	/* size rx & tx*/
+	TxDisableCrc	= 1<<16,	/* size */
+	TxChainStart	= 1<<21,	/* size */
+	TxChainEnd	= 1<<22,	/* size */
+	TxInt		= 1<<23,	/* size */
 };
 
 enum RhineMiiCrbits {
-	Mdc = 1<<0,
-	Mdi = 1<<1,
-	Mdo = 1<<2,
-	Mdout = 1<<3,
-	Mdpm = 1<<4,
-	Wcmd = 1<<5,
-	Rcmd = 1<<6,
-	Mauto = 1<<7,
-};
-
-enum RhineMiiSrbits {
-	Speed10M = 1<<0,
-	LinkFail = 1<<1,
-	PhyError = 1<<3,
-	DefaultPhy = 1<<4,
-	ResetPhy = 1<<7,
-};
-
-enum RhineMiiAddrbits {
-	Mdone = 1<<5,
-	Msrcen = 1<<6,
-	Midle = 1<<7,
-};
-
-static char *
-txstatnames[Ntxstats] = {
-	"aborts (excess collisions)",
-	"out of window collisions",
-	"carrier sense losses",
-	"fifo underflows",
-	"invalid descriptor format or underflows",
-	"system errors",
-	"reserved",
-	"transmit errors",
-	"collisions",
-};
-
-static char *
-rxstatnames[Nrxstats] = {
-	"receiver errors",
-	"crc errors",
-	"frame alignment errors",
-	"fifo overflows",
-	"long packets",
-	"run packets",
-	"system errors",
-	"buffer underflows",
+	Mdc	= 1<<0,
+	Mdi	= 1<<1,
+	Mdo	= 1<<2,
+	Mdout	= 1<<3,
+	Mdpm	= 1<<4,
+	Wcmd	= 1<<5,
+	Rcmd	= 1<<6,
+	Mauto	= 1<<7,
 };
 
 static void
@@ -288,7 +250,7 @@ attach(Ether *edev)
 	Mii *mi;
 	MiiPhy *phy;
 	int i, s;
-	
+
 	ctlr = edev->ctlr;
 	qlock(&ctlr->attachlck);
 	if (ctlr->attached == 0) {
@@ -320,14 +282,15 @@ attach(Ether *edev)
 		s = splhi();
 		iow32(ctlr, TxdAddr, PCIWADDR(&txd[0]));
 		iow32(ctlr, RxdAddr, PCIWADDR(&rxd[0]));
-		iow16(ctlr, Cr, (phy->fd ? FullDuplex : 0) | NoAutoPoll | TxOn | RxOn | Start | Rdmd);
+		iow16(ctlr, Cr, (phy->fd? FullDuplex: 0) | NoAutoPoll | TxOn |
+			RxOn | Start | Rdmd);
 		iow16(ctlr, Isr, 0xFFFF);
 		iow16(ctlr, Imr, 0xFFFF);
 		iow8(ctlr, MiscIsr, 0xFF);
 		iow8(ctlr, MiscImr, ~(3<<5));
 		splx(s);
+		ctlr->attached = 1;
 	}
-	ctlr->attached++;
 	qunlock(&ctlr->attachlck);
 }
 
@@ -340,23 +303,21 @@ txstart(Ether *edev)
 	RingBuf *tb;
 
 	ctlr = edev->ctlr;
-
 	txd = ctlr->txd;
 	i = ctlr->txhead;
-	txused = ctlr->txused;
 	n = 0;
-	while (txused < Ntxd) {
+	for (txused = ctlr->txused; txused < Ntxd; txused++) {
 		tb = &edev->tb[edev->ti];
 		if(tb->owner != Interface)
 			break;
 
 		td = &txd[i];
 		memmove(td->buf, tb->pkt, tb->len);
-		td->size = tb->len | TxChainStart | TxChainEnd | TxInt; /* could reduce number of ints here */
+		/* could reduce number of intrs here */
+		td->size = tb->len | TxChainStart | TxChainEnd | TxInt;
 		coherence();
 		td->stat = OwnNic;
 		i = (i + 1) % Ntxd;
-		txused++;
 		n++;
 
 		tb->owner = Host;
@@ -373,6 +334,7 @@ static void
 transmit(Ether *edev)
 {
 	Ctlr *ctlr;
+
 	ctlr = edev->ctlr;
 	ilock(&ctlr->tlock);
 	txstart(edev);
@@ -384,27 +346,18 @@ txcomplete(Ether *edev)
 {
 	Ctlr *ctlr;
 	Desc *txd, *td;
-	int i, txused, j;
+	int i, txused;
 	ulong stat;
 
 	ctlr = edev->ctlr;
  	txd = ctlr->txd;
-	txused = ctlr->txused;
 	i = ctlr->txtail;
-	while (txused > 0) {
+	for (txused = ctlr->txused; txused > 0; txused--) {
 		td = &txd[i];
 		stat = td->stat;
-
 		if (stat & OwnNic)
 			break;
-
-		ctlr->txstats[Ntxstats-1] += stat & 0xF;
-		for (j = 0; j < Ntxstats-1; ++j)
-			if (stat & (1<<(j+8)))
-				ctlr->txstats[j]++;
-
 		i = (i + 1) % Ntxd;
-		txused--;
 	}
 	ctlr->txused = txused;
 	ctlr->txtail = i;
@@ -422,14 +375,15 @@ interrupt(Ureg *, void *arg)
 	ushort  isr, misr;
 	ulong stat;
 	Desc *rxd, *rd;
-	int i, n, j, size;
+	int i, n, size;
 
 	edev = (Ether*)arg;
 	ctlr = edev->ctlr;
 	iow16(ctlr, Imr, 0);
 	isr = ior16(ctlr, Isr);
 	iow16(ctlr, Isr, 0xFFFF);
-	misr = ior16(ctlr, MiscIsr) & ~(3<<5); /* don't care about used defined ints */
+	/* don't care about used defined intrs */
+	misr = ior16(ctlr, MiscIsr) & ~(3<<5);
 
 	if (isr & RxOk) {
 		rxd = ctlr->rxd;
@@ -439,14 +393,9 @@ interrupt(Ureg *, void *arg)
 		while ((rxd[i].stat & OwnNic) == 0) {
 			rd = &rxd[i];
 			stat = rd->stat;
-			for (j = 0; j < Nrxstats; ++j)
-				if (stat & (1<<j))
-					ctlr->rxstats[j]++;
-
 			if (stat & 0xFF)
 				iprint("rx: %lux\n", stat & 0xFF);
-
-			size = ((rd->stat>>16) & 2047) - 4;
+			size = ((rd->stat>>16) & (2048-1)) - 4;
 
 			rb = &edev->rb[edev->ri];
 			if(rb->owner == Interface){
@@ -472,24 +421,11 @@ interrupt(Ureg *, void *arg)
 		isr &= ~TxOk;
 	}
 	if (isr | misr)
-		iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n", isr, misr);
-
+		iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n",
+			isr, misr);
 	iow16(ctlr, Imr, 0xFFFF);
 }
 
-static void
-promiscuous(void *arg, int enable)
-{
-	Ether *edev;
-	Ctlr *ctlr;
-
-	edev = arg;
-	ctlr = edev->ctlr;
-	ilock(&ctlr->tlock);
-	iow8(ctlr, Rcr, ior8(ctlr, Rcr) | (enable ? RxProm : RxBcast));
-	iunlock(&ctlr->tlock);
-}
-
 static int
 miiread(Mii *mii, int phy, int reg)
 {
@@ -497,7 +433,7 @@ miiread(Mii *mii, int phy, int reg)
 	int n;
 
 	ctlr = mii->ctlr;
-	
+
 	n = Nwait;
 	while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
 		microdelay(1);
@@ -515,9 +451,7 @@ miiread(Mii *mii, int phy, int reg)
 	if (n == Nwait)
 		iprint("etherrhine: miiread: timeout\n");
 
-	n = ior16(ctlr, RhineMiiData);
-
-	return n;
+	return ior16(ctlr, RhineMiiData);
 }
 
 static int
@@ -552,17 +486,49 @@ miiwrite(Mii *mii, int phy, int reg, int data)
 static void
 reset(Ctlr* ctlr)
 {
-	int i;
-
-	iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
-	iow16(ctlr, Cr, ior16(ctlr, Cr) | Reset);
+	int r, timeo;
+
+	/*
+	 * Soft reset the controller.
+	 */
+	csr16w(ctlr, Cr, Reset);
+	for(timeo = 0; timeo < 10000; timeo++){
+		if(!(csr16r(ctlr, Cr) & Reset))
+			break;
+		microdelay(1);
+	}
+	if(timeo >= 1000)
+		return;
 
-	for (i = 0; i < Nwait; ++i) {
-		if ((ior16(ctlr, Cr) & Reset) == 0)
-			return;
-		delay(5);
+	/*
+	 * Load the MAC address into the PAR[01]
+	 * registers.
+	 */
+	r = csr8r(ctlr, Eecsr);
+	csr8w(ctlr, Eecsr, EeAutoLoad|r);
+	for(timeo = 0; timeo < 100; timeo++){
+		if(!(csr8r(ctlr, Cr) & EeAutoLoad))
+			break;
+		microdelay(1);
 	}
-	iprint("etherrhine: reset timeout\n");
+	if(timeo >= 100)
+		return;
+
+	/*
+	 * Configure DMA and Rx/Tx thresholds.
+	 * If the Rx/Tx threshold bits in Bcr[01] are 0 then
+	 * the thresholds are determined by Rcr/Tcr.
+	 */
+	r = csr8r(ctlr, Bcr0) & ~(CrftMASK|DmaMASK);
+	csr8w(ctlr, Bcr0, r|Crft64|Dma64);
+	r = csr8r(ctlr, Bcr1) & ~CtftMASK;
+	csr8w(ctlr, Bcr1, r|Ctft64);
+
+	r = csr8r(ctlr, Rcr) & ~(RrftMASK|Prom|Ar|Sep);
+	csr8w(ctlr, Rcr, r|Ab|Am);
+
+	r = csr8r(ctlr, Tcr) & ~(RtsfMASK|Ofset|Lb1|Lb0);
+	csr8w(ctlr, Tcr, r);
 }
 
 static void
@@ -578,11 +544,9 @@ init(Ether *edev)
 	int i;
 
 	ctlr = edev->ctlr;
-
 	ilock(&ctlr->tlock);
 
 	pcisetbme(ctlr->pci);
-
 	reset(ctlr);
 
 	iow8(ctlr, Eecsr, ior8(ctlr, Eecsr) | EeAutoLoad);
@@ -591,7 +555,7 @@ init(Ether *edev)
 			break;
 		delay(5);
 	}
-	if (i == Nwait)
+	if (i >= Nwait)
 		iprint("etherrhine: eeprom autoload timeout\n");
 
 	for (i = 0; i < Eaddrlen; ++i)
@@ -602,6 +566,7 @@ init(Ether *edev)
 	ctlr->mii.ctlr = ctlr;
 
 	if(mii(&ctlr->mii, ~0) == 0 || ctlr->mii.curphy == nil){
+		iunlock(&ctlr->tlock);
 		iprint("etherrhine: init mii failure\n");
 		return;
 	}
@@ -609,7 +574,6 @@ init(Ether *edev)
 		if (ctlr->mii.phy[i])
 			if (ctlr->mii.phy[i]->oui != 0xFFFFF)
 				ctlr->mii.curphy = ctlr->mii.phy[i];
-
 	miistatus(&ctlr->mii);
 
 	iow16(ctlr, Imr, 0);
@@ -631,7 +595,7 @@ rhinematch(ulong)
 		switch((p->did<<16)|p->vid){
 		default:
 			continue;
-		case (0x3053<<16)|0x1106:	/* Rhine III in Soekris */
+		case (0x3053<<16)|0x1106:	/* Rhine III vt6105m (Soekris) */
 		case (0x3065<<16)|0x1106:	/* Rhine II */
 		case (0x3106<<16)|0x1106:	/* Rhine III */
 			if (++nfound > nrhines) {
@@ -651,6 +615,8 @@ rhinepnp(Ether *edev)
 	Ctlr *ctlr;
 	ulong port;
 
+	if (edev->attach)
+		return 0;
 	p = rhinematch(edev->port);
 	if (p == nil)
 		return -1;
@@ -664,7 +630,7 @@ rhinepnp(Ether *edev)
 	memset(ctlr, 0, sizeof(Ctlr));
 	ctlr->txd = xspanalloc(sizeof(Desc) * Ntxd, 16, 0);
 	ctlr->rxd = xspanalloc(sizeof(Desc) * Nrxd, 16, 0);
-		
+
 	ctlr->pci = p;
 	ctlr->port = port;
 
@@ -675,7 +641,6 @@ rhinepnp(Ether *edev)
 
 	init(edev);
 
-
 	edev->attach = attach;
 	edev->transmit = transmit;
 	edev->interrupt = interrupt;
@@ -683,3 +648,9 @@ rhinepnp(Ether *edev)
 
 	return 0;
 }
+
+int
+vt6102pnp(Ether *edev)
+{
+	return rhinepnp(edev);
+}

+ 8 - 3
sys/src/boot/pc/load.c

@@ -7,6 +7,10 @@
 #include "sd.h"
 #include "fs.h"
 
+#ifndef VERBOSE
+#define VERBOSE 0
+#endif
+
 /*
  * "cache" must be in this list so that 9load will pass the definition of
  * the cache partition into the kernel so that the disk named by the `cfs'
@@ -180,7 +184,7 @@ int scsi0port;
 char *defaultpartition;
 int iniread;
 
-static int debugload;
+int debugload;
 
 static Medium*
 parse(char *line, char **file)
@@ -323,8 +327,8 @@ main(void)
 	alarminit();
 	meminit(0);
 	spllo();
+	consinit("0", "9600");
 	kbdinit();
-
 	if((ulong)&end > (KZERO|(640*1024)))
 		panic("i'm too big\n");
 
@@ -335,6 +339,8 @@ main(void)
 		/* skip bios until we have read plan9.ini */
 		if(!pxe && tp->type == Tether || tp->type == Tbios)
 			continue;
+		if (VERBOSE)
+			print("probing %s...", typename(tp->type));
 		if((mp = probe(tp->type, Fini, Dany)) && (mp->flag & Fini)){
 			print("using %s!%s!%s\n", mp->name, mp->part, mp->ini);
 			iniread = !dotini(mp->inifs);
@@ -605,7 +611,6 @@ warp9(ulong entry)
 		floppydetach();
 	if(sddetach)
 		sddetach();
-
 	consdrain();
 
 	splhi();

+ 1 - 0
sys/src/libhttpd/escape.h

@@ -98,6 +98,7 @@ Htmlesc htmlesc[] =
 	{ "&yuml;",	L'ÿ', },
 
 	{ "&quot;",	L'"', },
+	{ "&#39;",	L'\'', }, /* Note &apos; is valid XML but not valid HTML */
 	{ "&amp;",	L'&', },
 	{ "&lt;",	L'<', },
 	{ "&gt;",	L'>', },