|
@@ -1,4 +1,4 @@
|
|
|
- /*
|
|
|
+/*
|
|
|
Via Rhine driver, written for VT6102.
|
|
|
Uses the ethermii to control PHY.
|
|
|
|
|
@@ -7,7 +7,7 @@
|
|
|
(almost) copy-free by using (possibly) two descriptors (if it allows
|
|
|
arbitrary tx lengths, which it should..): first for alignment and
|
|
|
second for rest of the frame. Rx-part should be worth doing.
|
|
|
-*/
|
|
|
+ */
|
|
|
#include "u.h"
|
|
|
#include "lib.h"
|
|
|
#include "mem.h"
|
|
@@ -23,261 +23,223 @@ typedef struct QLock { int r; } QLock;
|
|
|
#include "etherif.h"
|
|
|
#include "ethermii.h"
|
|
|
|
|
|
-typedef struct Desc Desc;
|
|
|
-typedef struct Ctlr Ctlr;
|
|
|
-
|
|
|
enum {
|
|
|
Ntxd = 4,
|
|
|
Nrxd = 4,
|
|
|
Nwait = 50,
|
|
|
- Ntxstats = 9,
|
|
|
- Nrxstats = 8,
|
|
|
BIGSTR = 8192,
|
|
|
};
|
|
|
|
|
|
+typedef struct Desc Desc;
|
|
|
+typedef struct Ctlr Ctlr;
|
|
|
+
|
|
|
struct Desc {
|
|
|
- ulong stat;
|
|
|
- ulong size;
|
|
|
- ulong addr;
|
|
|
- ulong next;
|
|
|
- char *buf;
|
|
|
- ulong pad[3];
|
|
|
+ ulong stat;
|
|
|
+ ulong size;
|
|
|
+ ulong addr;
|
|
|
+ ulong next;
|
|
|
+ char *buf;
|
|
|
+ ulong pad[3];
|
|
|
};
|
|
|
|
|
|
struct Ctlr {
|
|
|
- Pcidev *pci;
|
|
|
- int attached;
|
|
|
- int txused;
|
|
|
- int txhead;
|
|
|
- int txtail;
|
|
|
- int rxtail;
|
|
|
- ulong port;
|
|
|
-
|
|
|
- Mii mii;
|
|
|
+ Pcidev *pci;
|
|
|
+ int attached;
|
|
|
+ int txused;
|
|
|
+ int txhead;
|
|
|
+ int txtail;
|
|
|
+ int rxtail;
|
|
|
+ ulong port;
|
|
|
|
|
|
- ulong txstats[Ntxstats];
|
|
|
- ulong rxstats[Nrxstats];
|
|
|
+ Mii mii;
|
|
|
|
|
|
- Desc *txd; /* wants to be aligned on 16-byte boundary */
|
|
|
- Desc *rxd;
|
|
|
+ Desc *txd; /* wants to be aligned on 16-byte boundary */
|
|
|
+ Desc *rxd;
|
|
|
|
|
|
- QLock attachlck;
|
|
|
- Lock tlock;
|
|
|
+ QLock attachlck;
|
|
|
+ Lock tlock;
|
|
|
};
|
|
|
|
|
|
#define ior8(c, r) (inb((c)->port+(r)))
|
|
|
+#define iow8(c, r, b) (outb((c)->port+(r), (int)(b)))
|
|
|
#define ior16(c, r) (ins((c)->port+(r)))
|
|
|
#define ior32(c, r) (inl((c)->port+(r)))
|
|
|
-#define iow8(c, r, b) (outb((c)->port+(r), (int)(b)))
|
|
|
#define iow16(c, r, w) (outs((c)->port+(r), (ushort)(w)))
|
|
|
#define iow32(c, r, l) (outl((c)->port+(r), (ulong)(l)))
|
|
|
|
|
|
+/* names used everywhere else */
|
|
|
+#define csr8r ior8
|
|
|
+#define csr8w iow8
|
|
|
+#define csr16r ior16
|
|
|
+#define csr16w iow16
|
|
|
+#define csr32r ior32
|
|
|
+#define csr32w iow32
|
|
|
+
|
|
|
enum Regs {
|
|
|
- Eaddr = 0x0,
|
|
|
- Rcr = 0x6,
|
|
|
- Tcr = 0x7,
|
|
|
- Cr = 0x8,
|
|
|
- Isr = 0xc,
|
|
|
- Imr = 0xe,
|
|
|
- McastAddr = 0x10,
|
|
|
- RxdAddr = 0x18,
|
|
|
- TxdAddr = 0x1C,
|
|
|
- Bcr = 0x6e,
|
|
|
- RhineMiiPhy = 0x6C,
|
|
|
- RhineMiiSr = 0x6D,
|
|
|
- RhineMiiCr = 0x70,
|
|
|
- RhineMiiAddr = 0x71,
|
|
|
- RhineMiiData = 0x72,
|
|
|
- Eecsr = 0x74,
|
|
|
- ConfigB = 0x79,
|
|
|
- ConfigD = 0x7B,
|
|
|
- MiscCr = 0x80,
|
|
|
- HwSticky = 0x83,
|
|
|
- MiscIsr = 0x84,
|
|
|
- MiscImr = 0x86,
|
|
|
- WolCrSet = 0xA0,
|
|
|
- WolCfgSet = 0xA1,
|
|
|
- WolCgSet = 0xA3,
|
|
|
- WolCrClr = 0xA4,
|
|
|
- PwrCfgClr = 0xA5,
|
|
|
- WolCgClr = 0xA7,
|
|
|
+ Eaddr = 0x0,
|
|
|
+ Rcr = 0x6,
|
|
|
+ Tcr = 0x7,
|
|
|
+ Cr = 0x8,
|
|
|
+ Isr = 0xc,
|
|
|
+ Imr = 0xe,
|
|
|
+ McastAddr = 0x10,
|
|
|
+ RxdAddr = 0x18,
|
|
|
+ TxdAddr = 0x1C,
|
|
|
+ Bcr0 = 0x6E, /* Bus Control */
|
|
|
+ Bcr1 = 0x6F,
|
|
|
+ RhineMiiPhy = 0x6C,
|
|
|
+ RhineMiiSr = 0x6D,
|
|
|
+ RhineMiiCr = 0x70,
|
|
|
+ RhineMiiAddr = 0x71,
|
|
|
+ RhineMiiData = 0x72,
|
|
|
+ Eecsr = 0x74,
|
|
|
+ ConfigB = 0x79,
|
|
|
+ ConfigD = 0x7B,
|
|
|
+ MiscCr = 0x80,
|
|
|
+ HwSticky = 0x83,
|
|
|
+ MiscIsr = 0x84,
|
|
|
+ MiscImr = 0x86,
|
|
|
+ WolCrSet = 0xA0,
|
|
|
+ WolCfgSet = 0xA1,
|
|
|
+ WolCgSet = 0xA3,
|
|
|
+ WolCrClr = 0xA4,
|
|
|
+ PwrCfgClr = 0xA5,
|
|
|
+ WolCgClr = 0xA7,
|
|
|
};
|
|
|
|
|
|
-enum Rcrbits {
|
|
|
- RxErrX = 1<<0,
|
|
|
- RxSmall = 1<<1,
|
|
|
- RxMcast = 1<<2,
|
|
|
- RxBcast = 1<<3,
|
|
|
- RxProm = 1<<4,
|
|
|
- RxFifo64 = 0<<5, RxFifo32 = 1<<5, RxFifo128 = 2<<5, RxFifo256 = 3<<5,
|
|
|
- RxFifo512 = 4<<5, RxFifo768 = 5<<5, RxFifo1024 = 6<<5,
|
|
|
- RxFifoStoreForward = 7<<5,
|
|
|
+enum { /* Rcr */
|
|
|
+ Sep = 0x01, /* Accept Error Packets */
|
|
|
+ Ar = 0x02, /* Accept Small Packets */
|
|
|
+ Am = 0x04, /* Accept Multicast */
|
|
|
+ Ab = 0x08, /* Accept Broadcast */
|
|
|
+ RxBcast = Ab,
|
|
|
+ Prom = 0x10, /* Accept Physical Address Packets */
|
|
|
+ RxProm = Prom,
|
|
|
+ RrftMASK = 0xE0, /* Receive FIFO Threshold */
|
|
|
+ RrftSHIFT = 5,
|
|
|
+ Rrft64 = 0<<RrftSHIFT,
|
|
|
+ Rrft32 = 1<<RrftSHIFT,
|
|
|
+ Rrft128 = 2<<RrftSHIFT,
|
|
|
+ Rrft256 = 3<<RrftSHIFT,
|
|
|
+ Rrft512 = 4<<RrftSHIFT,
|
|
|
+ Rrft768 = 5<<RrftSHIFT,
|
|
|
+ Rrft1024 = 6<<RrftSHIFT,
|
|
|
+ RrftSAF = 7<<RrftSHIFT,
|
|
|
};
|
|
|
|
|
|
-enum Tcrbits {
|
|
|
- TxLoopback0 = 1<<1,
|
|
|
- TxLoopback1 = 1<<2,
|
|
|
- TxBackoff = 1<<3,
|
|
|
- TxFifo128 = 0<<5, TxFifo256 = 1<<5, TxFifo512 = 2<<5, TxFifo1024 = 3<<5,
|
|
|
- TxFifoStoreForward = 7<<5,
|
|
|
+enum { /* Tcr */
|
|
|
+ Lb0 = 0x02, /* Loopback Mode */
|
|
|
+ Lb1 = 0x04,
|
|
|
+ Ofset = 0x08, /* Back-off Priority Selection */
|
|
|
+ RtsfMASK = 0xE0, /* Transmit FIFO Threshold */
|
|
|
+ RtsfSHIFT = 5,
|
|
|
+ Rtsf128 = 0<<RtsfSHIFT,
|
|
|
+ Rtsf256 = 1<<RtsfSHIFT,
|
|
|
+ Rtsf512 = 2<<RtsfSHIFT,
|
|
|
+ Rtsf1024 = 3<<RtsfSHIFT,
|
|
|
+ RtsfSAF = 7<<RtsfSHIFT,
|
|
|
};
|
|
|
|
|
|
enum Crbits {
|
|
|
- Init = 1<<0,
|
|
|
- Start = 1<<1,
|
|
|
- Stop = 1<<2,
|
|
|
- RxOn = 1<<3,
|
|
|
- TxOn = 1<<4,
|
|
|
- Tdmd = 1<<5,
|
|
|
- Rdmd = 1<<6,
|
|
|
- EarlyRx = 1<<8,
|
|
|
- Reserved0 = 1<<9,
|
|
|
- FullDuplex = 1<<10,
|
|
|
- NoAutoPoll = 1<<11,
|
|
|
- Reserved1 = 1<<12,
|
|
|
- Tdmd1 = 1<<13,
|
|
|
- Rdmd1 = 1<<14,
|
|
|
- Reset = 1<<15,
|
|
|
+ Init = 1<<0,
|
|
|
+ Start = 1<<1,
|
|
|
+ Stop = 1<<2,
|
|
|
+ RxOn = 1<<3,
|
|
|
+ TxOn = 1<<4,
|
|
|
+ Tdmd = 1<<5,
|
|
|
+ Rdmd = 1<<6,
|
|
|
+ EarlyRx = 1<<8,
|
|
|
+ Reserved0 = 1<<9,
|
|
|
+ FullDuplex = 1<<10,
|
|
|
+ NoAutoPoll = 1<<11,
|
|
|
+ Reserved1 = 1<<12,
|
|
|
+ Tdmd1 = 1<<13,
|
|
|
+ Rdmd1 = 1<<14,
|
|
|
+ Reset = 1<<15,
|
|
|
};
|
|
|
|
|
|
enum Isrbits {
|
|
|
- RxOk = 1<<0,
|
|
|
- TxOk = 1<<1,
|
|
|
- RxErr = 1<<2,
|
|
|
- TxErr = 1<<3,
|
|
|
- TxBufUdf = 1<<4,
|
|
|
- RxBufLinkErr = 1<<5,
|
|
|
- BusErr = 1<<6,
|
|
|
- CrcOvf = 1<<7,
|
|
|
- EarlyRxInt = 1<<8,
|
|
|
- TxFifoUdf = 1<<9,
|
|
|
- RxFifoOvf = 1<<10,
|
|
|
- TxPktRace = 1<<11,
|
|
|
- NoRxbuf = 1<<12,
|
|
|
- TxCollision = 1<<13,
|
|
|
- PortCh = 1<<14,
|
|
|
- GPInt = 1<<15
|
|
|
+ RxOk = 1<<0,
|
|
|
+ TxOk = 1<<1,
|
|
|
+ RxErr = 1<<2,
|
|
|
+ TxErr = 1<<3,
|
|
|
+ TxBufUdf = 1<<4,
|
|
|
+ RxBufLinkErr = 1<<5,
|
|
|
+ BusErr = 1<<6,
|
|
|
+ CrcOvf = 1<<7,
|
|
|
+ EarlyRxInt = 1<<8,
|
|
|
+ TxFifoUdf = 1<<9,
|
|
|
+ RxFifoOvf = 1<<10,
|
|
|
+ TxPktRace = 1<<11,
|
|
|
+ NoRxbuf = 1<<12,
|
|
|
+ TxCollision = 1<<13,
|
|
|
+ PortCh = 1<<14,
|
|
|
+ GPInt = 1<<15,
|
|
|
};
|
|
|
|
|
|
-enum Bcrbits {
|
|
|
- Dma32 = 0<<0, Dma64 = 1<<0, Dma128 = 2<<0,
|
|
|
- Dma256 = 3<<0, Dma512 = 4<<0, Dma1024 = 5<<0,
|
|
|
- DmaStoreForward = 7<<0,
|
|
|
- DupRxFifo0 = 1<<3, DupRxFifo1 = 1<<4, DupRxFifo2 = 1<<5,
|
|
|
- ExtraLed = 1<<6,
|
|
|
- MediumSelect = 1<<7,
|
|
|
- PollTimer0 = 1<<8, PollTimer1 = 1<<9, PollTimer2 = 1<<10,
|
|
|
- DupTxFifo0 = 1<<11, DupTxFifo1 = 1<<12, DupTxFifo2 = 1<<13,
|
|
|
+enum { /* Bcr0 */
|
|
|
+ DmaMASK = 0x07, /* DMA Length */
|
|
|
+ DmaSHIFT = 0,
|
|
|
+ Dma32 = 0<<DmaSHIFT,
|
|
|
+ Dma64 = 1<<DmaSHIFT,
|
|
|
+ Dma128 = 2<<DmaSHIFT,
|
|
|
+ Dma256 = 3<<DmaSHIFT,
|
|
|
+ Dma512 = 4<<DmaSHIFT,
|
|
|
+ Dma1024 = 5<<DmaSHIFT,
|
|
|
+ DmaSAF = 7<<DmaSHIFT,
|
|
|
+ CrftMASK = 0x38, /* Rx FIFO Threshold */
|
|
|
+ CrftSHIFT = 3,
|
|
|
+ Crft64 = 1<<CrftSHIFT,
|
|
|
+ Crft128 = 2<<CrftSHIFT,
|
|
|
+ Crft256 = 3<<CrftSHIFT,
|
|
|
+ Crft512 = 4<<CrftSHIFT,
|
|
|
+ Crft1024 = 5<<CrftSHIFT,
|
|
|
+ CrftSAF = 7<<CrftSHIFT,
|
|
|
+ Extled = 0x40, /* Extra LED Support Control */
|
|
|
+ Med2 = 0x80, /* Medium Select Control */
|
|
|
};
|
|
|
|
|
|
-enum Eecsrbits {
|
|
|
- EeAutoLoad = 1<<5,
|
|
|
+enum { /* Bcr1 */
|
|
|
+ PotMASK = 0x07, /* Polling Timer Interval */
|
|
|
+ PotSHIFT = 0,
|
|
|
+ CtftMASK = 0x38, /* Tx FIFO Threshold */
|
|
|
+ CtftSHIFT = 3,
|
|
|
+ Ctft64 = 1<<CtftSHIFT,
|
|
|
+ Ctft128 = 2<<CtftSHIFT,
|
|
|
+ Ctft256 = 3<<CtftSHIFT,
|
|
|
+ Ctft512 = 4<<CtftSHIFT,
|
|
|
+ Ctft1024 = 5<<CtftSHIFT,
|
|
|
+ CtftSAF = 7<<CtftSHIFT,
|
|
|
};
|
|
|
|
|
|
-enum MiscCrbits {
|
|
|
- Timer0Enable= 1<<0,
|
|
|
- Timer0Suspend = 1<<1,
|
|
|
- HalfDuplexFlowControl = 1<<2,
|
|
|
- FullDuplexFlowControl = 1<<3,
|
|
|
- Timer1Enable = 1<<8,
|
|
|
- ForceSoftReset = 1<<14,
|
|
|
-};
|
|
|
|
|
|
-enum HwStickybits {
|
|
|
- StickyDS0 = 1<<0,
|
|
|
- StickyDS1 = 1<<1,
|
|
|
- WOLEna = 1<<2,
|
|
|
- WOLStat = 1<<3,
|
|
|
-};
|
|
|
-
|
|
|
-enum WolCgbits {
|
|
|
- PmeOvr = 1<<7,
|
|
|
+enum Eecsrbits {
|
|
|
+ EeAutoLoad = 1<<5,
|
|
|
};
|
|
|
|
|
|
enum Descbits {
|
|
|
- OwnNic = 1<<31, /* stat */
|
|
|
- TxAbort = 1<<8, /* stat */
|
|
|
- TxError = 1<<15, /* stat */
|
|
|
- RxChainbuf = 1<<10, /* stat */
|
|
|
- RxChainStart = 1<<9, /* stat */
|
|
|
- RxChainEnd = 1<<8, /* stat */
|
|
|
- Chainbuf = 1<<15, /* size rx & tx*/
|
|
|
- TxDisableCrc = 1<<16, /* size */
|
|
|
- TxChainStart = 1<<21, /* size */
|
|
|
- TxChainEnd = 1<<22, /* size */
|
|
|
- TxInt = 1<<23, /* size */
|
|
|
-};
|
|
|
-
|
|
|
-enum ConfigDbits {
|
|
|
- BackoffOptional = 1<<0,
|
|
|
- BackoffAMD = 1<<1,
|
|
|
- BackoffDEC = 1<<2,
|
|
|
- BackoffRandom = 1<<3,
|
|
|
- PmccTestMode = 1<<4,
|
|
|
- PciReadlineCap = 1<<5,
|
|
|
- DiagMode = 1<<6,
|
|
|
- MmioEnable = 1<<7,
|
|
|
-};
|
|
|
-
|
|
|
-enum ConfigBbits {
|
|
|
- LatencyTimer = 1<<0,
|
|
|
- WriteWaitState = 1<<1,
|
|
|
- ReadWaitState = 1<<2,
|
|
|
- RxArbit = 1<<3,
|
|
|
- TxArbit = 1<<4,
|
|
|
- NoMemReadline = 1<<5,
|
|
|
- NoParity = 1<<6,
|
|
|
- NoTxQueuing = 1<<7,
|
|
|
+ OwnNic = 1<<31, /* stat */
|
|
|
+ TxAbort = 1<<8, /* stat */
|
|
|
+ TxError = 1<<15, /* stat */
|
|
|
+ RxChainbuf = 1<<10, /* stat */
|
|
|
+ RxChainStart = 1<<9, /* stat */
|
|
|
+ RxChainEnd = 1<<8, /* stat */
|
|
|
+ Chainbuf = 1<<15, /* size rx & tx*/
|
|
|
+ TxDisableCrc = 1<<16, /* size */
|
|
|
+ TxChainStart = 1<<21, /* size */
|
|
|
+ TxChainEnd = 1<<22, /* size */
|
|
|
+ TxInt = 1<<23, /* size */
|
|
|
};
|
|
|
|
|
|
enum RhineMiiCrbits {
|
|
|
- Mdc = 1<<0,
|
|
|
- Mdi = 1<<1,
|
|
|
- Mdo = 1<<2,
|
|
|
- Mdout = 1<<3,
|
|
|
- Mdpm = 1<<4,
|
|
|
- Wcmd = 1<<5,
|
|
|
- Rcmd = 1<<6,
|
|
|
- Mauto = 1<<7,
|
|
|
-};
|
|
|
-
|
|
|
-enum RhineMiiSrbits {
|
|
|
- Speed10M = 1<<0,
|
|
|
- LinkFail = 1<<1,
|
|
|
- PhyError = 1<<3,
|
|
|
- DefaultPhy = 1<<4,
|
|
|
- ResetPhy = 1<<7,
|
|
|
-};
|
|
|
-
|
|
|
-enum RhineMiiAddrbits {
|
|
|
- Mdone = 1<<5,
|
|
|
- Msrcen = 1<<6,
|
|
|
- Midle = 1<<7,
|
|
|
-};
|
|
|
-
|
|
|
-static char *
|
|
|
-txstatnames[Ntxstats] = {
|
|
|
- "aborts (excess collisions)",
|
|
|
- "out of window collisions",
|
|
|
- "carrier sense losses",
|
|
|
- "fifo underflows",
|
|
|
- "invalid descriptor format or underflows",
|
|
|
- "system errors",
|
|
|
- "reserved",
|
|
|
- "transmit errors",
|
|
|
- "collisions",
|
|
|
-};
|
|
|
-
|
|
|
-static char *
|
|
|
-rxstatnames[Nrxstats] = {
|
|
|
- "receiver errors",
|
|
|
- "crc errors",
|
|
|
- "frame alignment errors",
|
|
|
- "fifo overflows",
|
|
|
- "long packets",
|
|
|
- "run packets",
|
|
|
- "system errors",
|
|
|
- "buffer underflows",
|
|
|
+ Mdc = 1<<0,
|
|
|
+ Mdi = 1<<1,
|
|
|
+ Mdo = 1<<2,
|
|
|
+ Mdout = 1<<3,
|
|
|
+ Mdpm = 1<<4,
|
|
|
+ Wcmd = 1<<5,
|
|
|
+ Rcmd = 1<<6,
|
|
|
+ Mauto = 1<<7,
|
|
|
};
|
|
|
|
|
|
static void
|
|
@@ -288,7 +250,7 @@ attach(Ether *edev)
|
|
|
Mii *mi;
|
|
|
MiiPhy *phy;
|
|
|
int i, s;
|
|
|
-
|
|
|
+
|
|
|
ctlr = edev->ctlr;
|
|
|
qlock(&ctlr->attachlck);
|
|
|
if (ctlr->attached == 0) {
|
|
@@ -320,14 +282,15 @@ attach(Ether *edev)
|
|
|
s = splhi();
|
|
|
iow32(ctlr, TxdAddr, PCIWADDR(&txd[0]));
|
|
|
iow32(ctlr, RxdAddr, PCIWADDR(&rxd[0]));
|
|
|
- iow16(ctlr, Cr, (phy->fd ? FullDuplex : 0) | NoAutoPoll | TxOn | RxOn | Start | Rdmd);
|
|
|
+ iow16(ctlr, Cr, (phy->fd? FullDuplex: 0) | NoAutoPoll | TxOn |
|
|
|
+ RxOn | Start | Rdmd);
|
|
|
iow16(ctlr, Isr, 0xFFFF);
|
|
|
iow16(ctlr, Imr, 0xFFFF);
|
|
|
iow8(ctlr, MiscIsr, 0xFF);
|
|
|
iow8(ctlr, MiscImr, ~(3<<5));
|
|
|
splx(s);
|
|
|
+ ctlr->attached = 1;
|
|
|
}
|
|
|
- ctlr->attached++;
|
|
|
qunlock(&ctlr->attachlck);
|
|
|
}
|
|
|
|
|
@@ -340,23 +303,21 @@ txstart(Ether *edev)
|
|
|
RingBuf *tb;
|
|
|
|
|
|
ctlr = edev->ctlr;
|
|
|
-
|
|
|
txd = ctlr->txd;
|
|
|
i = ctlr->txhead;
|
|
|
- txused = ctlr->txused;
|
|
|
n = 0;
|
|
|
- while (txused < Ntxd) {
|
|
|
+ for (txused = ctlr->txused; txused < Ntxd; txused++) {
|
|
|
tb = &edev->tb[edev->ti];
|
|
|
if(tb->owner != Interface)
|
|
|
break;
|
|
|
|
|
|
td = &txd[i];
|
|
|
memmove(td->buf, tb->pkt, tb->len);
|
|
|
- td->size = tb->len | TxChainStart | TxChainEnd | TxInt; /* could reduce number of ints here */
|
|
|
+ /* could reduce number of intrs here */
|
|
|
+ td->size = tb->len | TxChainStart | TxChainEnd | TxInt;
|
|
|
coherence();
|
|
|
td->stat = OwnNic;
|
|
|
i = (i + 1) % Ntxd;
|
|
|
- txused++;
|
|
|
n++;
|
|
|
|
|
|
tb->owner = Host;
|
|
@@ -373,6 +334,7 @@ static void
|
|
|
transmit(Ether *edev)
|
|
|
{
|
|
|
Ctlr *ctlr;
|
|
|
+
|
|
|
ctlr = edev->ctlr;
|
|
|
ilock(&ctlr->tlock);
|
|
|
txstart(edev);
|
|
@@ -384,27 +346,18 @@ txcomplete(Ether *edev)
|
|
|
{
|
|
|
Ctlr *ctlr;
|
|
|
Desc *txd, *td;
|
|
|
- int i, txused, j;
|
|
|
+ int i, txused;
|
|
|
ulong stat;
|
|
|
|
|
|
ctlr = edev->ctlr;
|
|
|
txd = ctlr->txd;
|
|
|
- txused = ctlr->txused;
|
|
|
i = ctlr->txtail;
|
|
|
- while (txused > 0) {
|
|
|
+ for (txused = ctlr->txused; txused > 0; txused--) {
|
|
|
td = &txd[i];
|
|
|
stat = td->stat;
|
|
|
-
|
|
|
if (stat & OwnNic)
|
|
|
break;
|
|
|
-
|
|
|
- ctlr->txstats[Ntxstats-1] += stat & 0xF;
|
|
|
- for (j = 0; j < Ntxstats-1; ++j)
|
|
|
- if (stat & (1<<(j+8)))
|
|
|
- ctlr->txstats[j]++;
|
|
|
-
|
|
|
i = (i + 1) % Ntxd;
|
|
|
- txused--;
|
|
|
}
|
|
|
ctlr->txused = txused;
|
|
|
ctlr->txtail = i;
|
|
@@ -422,14 +375,15 @@ interrupt(Ureg *, void *arg)
|
|
|
ushort isr, misr;
|
|
|
ulong stat;
|
|
|
Desc *rxd, *rd;
|
|
|
- int i, n, j, size;
|
|
|
+ int i, n, size;
|
|
|
|
|
|
edev = (Ether*)arg;
|
|
|
ctlr = edev->ctlr;
|
|
|
iow16(ctlr, Imr, 0);
|
|
|
isr = ior16(ctlr, Isr);
|
|
|
iow16(ctlr, Isr, 0xFFFF);
|
|
|
- misr = ior16(ctlr, MiscIsr) & ~(3<<5); /* don't care about used defined ints */
|
|
|
+ /* don't care about used defined intrs */
|
|
|
+ misr = ior16(ctlr, MiscIsr) & ~(3<<5);
|
|
|
|
|
|
if (isr & RxOk) {
|
|
|
rxd = ctlr->rxd;
|
|
@@ -439,14 +393,9 @@ interrupt(Ureg *, void *arg)
|
|
|
while ((rxd[i].stat & OwnNic) == 0) {
|
|
|
rd = &rxd[i];
|
|
|
stat = rd->stat;
|
|
|
- for (j = 0; j < Nrxstats; ++j)
|
|
|
- if (stat & (1<<j))
|
|
|
- ctlr->rxstats[j]++;
|
|
|
-
|
|
|
if (stat & 0xFF)
|
|
|
iprint("rx: %lux\n", stat & 0xFF);
|
|
|
-
|
|
|
- size = ((rd->stat>>16) & 2047) - 4;
|
|
|
+ size = ((rd->stat>>16) & (2048-1)) - 4;
|
|
|
|
|
|
rb = &edev->rb[edev->ri];
|
|
|
if(rb->owner == Interface){
|
|
@@ -472,24 +421,11 @@ interrupt(Ureg *, void *arg)
|
|
|
isr &= ~TxOk;
|
|
|
}
|
|
|
if (isr | misr)
|
|
|
- iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n", isr, misr);
|
|
|
-
|
|
|
+ iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n",
|
|
|
+ isr, misr);
|
|
|
iow16(ctlr, Imr, 0xFFFF);
|
|
|
}
|
|
|
|
|
|
-static void
|
|
|
-promiscuous(void *arg, int enable)
|
|
|
-{
|
|
|
- Ether *edev;
|
|
|
- Ctlr *ctlr;
|
|
|
-
|
|
|
- edev = arg;
|
|
|
- ctlr = edev->ctlr;
|
|
|
- ilock(&ctlr->tlock);
|
|
|
- iow8(ctlr, Rcr, ior8(ctlr, Rcr) | (enable ? RxProm : RxBcast));
|
|
|
- iunlock(&ctlr->tlock);
|
|
|
-}
|
|
|
-
|
|
|
static int
|
|
|
miiread(Mii *mii, int phy, int reg)
|
|
|
{
|
|
@@ -497,7 +433,7 @@ miiread(Mii *mii, int phy, int reg)
|
|
|
int n;
|
|
|
|
|
|
ctlr = mii->ctlr;
|
|
|
-
|
|
|
+
|
|
|
n = Nwait;
|
|
|
while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
|
|
|
microdelay(1);
|
|
@@ -515,9 +451,7 @@ miiread(Mii *mii, int phy, int reg)
|
|
|
if (n == Nwait)
|
|
|
iprint("etherrhine: miiread: timeout\n");
|
|
|
|
|
|
- n = ior16(ctlr, RhineMiiData);
|
|
|
-
|
|
|
- return n;
|
|
|
+ return ior16(ctlr, RhineMiiData);
|
|
|
}
|
|
|
|
|
|
static int
|
|
@@ -552,17 +486,49 @@ miiwrite(Mii *mii, int phy, int reg, int data)
|
|
|
static void
|
|
|
reset(Ctlr* ctlr)
|
|
|
{
|
|
|
- int i;
|
|
|
-
|
|
|
- iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
|
|
|
- iow16(ctlr, Cr, ior16(ctlr, Cr) | Reset);
|
|
|
+ int r, timeo;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Soft reset the controller.
|
|
|
+ */
|
|
|
+ csr16w(ctlr, Cr, Reset);
|
|
|
+ for(timeo = 0; timeo < 10000; timeo++){
|
|
|
+ if(!(csr16r(ctlr, Cr) & Reset))
|
|
|
+ break;
|
|
|
+ microdelay(1);
|
|
|
+ }
|
|
|
+ if(timeo >= 1000)
|
|
|
+ return;
|
|
|
|
|
|
- for (i = 0; i < Nwait; ++i) {
|
|
|
- if ((ior16(ctlr, Cr) & Reset) == 0)
|
|
|
- return;
|
|
|
- delay(5);
|
|
|
+ /*
|
|
|
+ * Load the MAC address into the PAR[01]
|
|
|
+ * registers.
|
|
|
+ */
|
|
|
+ r = csr8r(ctlr, Eecsr);
|
|
|
+ csr8w(ctlr, Eecsr, EeAutoLoad|r);
|
|
|
+ for(timeo = 0; timeo < 100; timeo++){
|
|
|
+ if(!(csr8r(ctlr, Cr) & EeAutoLoad))
|
|
|
+ break;
|
|
|
+ microdelay(1);
|
|
|
}
|
|
|
- iprint("etherrhine: reset timeout\n");
|
|
|
+ if(timeo >= 100)
|
|
|
+ return;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Configure DMA and Rx/Tx thresholds.
|
|
|
+ * If the Rx/Tx threshold bits in Bcr[01] are 0 then
|
|
|
+ * the thresholds are determined by Rcr/Tcr.
|
|
|
+ */
|
|
|
+ r = csr8r(ctlr, Bcr0) & ~(CrftMASK|DmaMASK);
|
|
|
+ csr8w(ctlr, Bcr0, r|Crft64|Dma64);
|
|
|
+ r = csr8r(ctlr, Bcr1) & ~CtftMASK;
|
|
|
+ csr8w(ctlr, Bcr1, r|Ctft64);
|
|
|
+
|
|
|
+ r = csr8r(ctlr, Rcr) & ~(RrftMASK|Prom|Ar|Sep);
|
|
|
+ csr8w(ctlr, Rcr, r|Ab|Am);
|
|
|
+
|
|
|
+ r = csr8r(ctlr, Tcr) & ~(RtsfMASK|Ofset|Lb1|Lb0);
|
|
|
+ csr8w(ctlr, Tcr, r);
|
|
|
}
|
|
|
|
|
|
static void
|
|
@@ -578,11 +544,9 @@ init(Ether *edev)
|
|
|
int i;
|
|
|
|
|
|
ctlr = edev->ctlr;
|
|
|
-
|
|
|
ilock(&ctlr->tlock);
|
|
|
|
|
|
pcisetbme(ctlr->pci);
|
|
|
-
|
|
|
reset(ctlr);
|
|
|
|
|
|
iow8(ctlr, Eecsr, ior8(ctlr, Eecsr) | EeAutoLoad);
|
|
@@ -591,7 +555,7 @@ init(Ether *edev)
|
|
|
break;
|
|
|
delay(5);
|
|
|
}
|
|
|
- if (i == Nwait)
|
|
|
+ if (i >= Nwait)
|
|
|
iprint("etherrhine: eeprom autoload timeout\n");
|
|
|
|
|
|
for (i = 0; i < Eaddrlen; ++i)
|
|
@@ -602,6 +566,7 @@ init(Ether *edev)
|
|
|
ctlr->mii.ctlr = ctlr;
|
|
|
|
|
|
if(mii(&ctlr->mii, ~0) == 0 || ctlr->mii.curphy == nil){
|
|
|
+ iunlock(&ctlr->tlock);
|
|
|
iprint("etherrhine: init mii failure\n");
|
|
|
return;
|
|
|
}
|
|
@@ -609,7 +574,6 @@ init(Ether *edev)
|
|
|
if (ctlr->mii.phy[i])
|
|
|
if (ctlr->mii.phy[i]->oui != 0xFFFFF)
|
|
|
ctlr->mii.curphy = ctlr->mii.phy[i];
|
|
|
-
|
|
|
miistatus(&ctlr->mii);
|
|
|
|
|
|
iow16(ctlr, Imr, 0);
|
|
@@ -631,7 +595,7 @@ rhinematch(ulong)
|
|
|
switch((p->did<<16)|p->vid){
|
|
|
default:
|
|
|
continue;
|
|
|
- case (0x3053<<16)|0x1106: /* Rhine III in Soekris */
|
|
|
+ case (0x3053<<16)|0x1106: /* Rhine III vt6105m (Soekris) */
|
|
|
case (0x3065<<16)|0x1106: /* Rhine II */
|
|
|
case (0x3106<<16)|0x1106: /* Rhine III */
|
|
|
if (++nfound > nrhines) {
|
|
@@ -651,6 +615,8 @@ rhinepnp(Ether *edev)
|
|
|
Ctlr *ctlr;
|
|
|
ulong port;
|
|
|
|
|
|
+ if (edev->attach)
|
|
|
+ return 0;
|
|
|
p = rhinematch(edev->port);
|
|
|
if (p == nil)
|
|
|
return -1;
|
|
@@ -664,7 +630,7 @@ rhinepnp(Ether *edev)
|
|
|
memset(ctlr, 0, sizeof(Ctlr));
|
|
|
ctlr->txd = xspanalloc(sizeof(Desc) * Ntxd, 16, 0);
|
|
|
ctlr->rxd = xspanalloc(sizeof(Desc) * Nrxd, 16, 0);
|
|
|
-
|
|
|
+
|
|
|
ctlr->pci = p;
|
|
|
ctlr->port = port;
|
|
|
|
|
@@ -675,7 +641,6 @@ rhinepnp(Ether *edev)
|
|
|
|
|
|
init(edev);
|
|
|
|
|
|
-
|
|
|
edev->attach = attach;
|
|
|
edev->transmit = transmit;
|
|
|
edev->interrupt = interrupt;
|
|
@@ -683,3 +648,9 @@ rhinepnp(Ether *edev)
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
+
|
|
|
+int
|
|
|
+vt6102pnp(Ether *edev)
|
|
|
+{
|
|
|
+ return rhinepnp(edev);
|
|
|
+}
|