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riscv: make the kernel loadable by spike

This is catching up to changes in spike in the last long while.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Ronald G. Minnich 7 years ago
parent
commit
4a76ec5ed6
3 changed files with 57 additions and 4 deletions
  1. 53 0
      riscv/include/u.h
  2. 1 1
      sys/src/9/riscv/core.json
  3. 3 3
      sys/src/9/riscv/kernel.ld

+ 53 - 0
riscv/include/u.h

@@ -0,0 +1,53 @@
+/*
+ * This file is part of the UCB release of Plan 9. It is subject to the license
+ * terms in the LICENSE file found in the top-level directory of this
+ * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
+ * part of the UCB release of Plan 9, including this file, may be copied,
+ * modified, propagated, or distributed except according to the terms contained
+ * in the LICENSE file.
+ */
+
+#define nil		((void*)0)
+typedef	unsigned char	uint8_t;
+typedef signed char	int8_t;
+typedef	unsigned short	uint16_t;
+typedef	signed short	int16_t;
+typedef unsigned int	uint32_t;
+typedef unsigned int	uint;
+typedef signed int	int32_t;
+typedef	unsigned long long uint64_t;
+typedef	long long	int64_t;
+typedef int64_t intptr_t;
+typedef uint64_t uintptr;
+typedef uint64_t uintptr_t;
+typedef uint32_t	usize;
+typedef int64_t size_t;
+typedef	uint32_t		Rune;
+typedef union FPdbleword FPdbleword;
+// This is a guess! Assumes float!
+typedef uintptr		jmp_buf[28]; // for registers.
+
+#define	JMPBUFSP	13
+#define	JMPBUFPC	0
+#define	JMPBUFARG1	1
+#define	JMPBUFARG2	2
+
+#define	JMPBUFDPC	0 // What? 
+typedef unsigned int	mpdigit;	/* for /sys/include/mp.h */
+
+union FPdbleword
+{
+	double	x;
+	struct {	/* little endian */
+		uint lo;
+		uint hi;
+	};
+};
+
+typedef __builtin_va_list va_list;
+
+#define va_start(v,l)	__builtin_va_start(v,l)
+#define va_end(v)	__builtin_va_end(v)
+#define va_arg(v,l)	__builtin_va_arg(v,l)
+#define va_copy(v,l)	__builtin_va_copy(v,l)
+

+ 1 - 1
sys/src/9/riscv/core.json

@@ -57,7 +57,7 @@
 		"SourceFiles": [
 			"ctype.c",
 			"main.c",
-			"spike_util.c"
+			"uart.c"
 		]
 	}
 }

+ 3 - 3
sys/src/9/riscv/kernel.ld

@@ -8,12 +8,12 @@
 OUTPUT_ARCH("riscv")
 /*OUTPUT_FORMAT("elf64-littleriscv", "elf64-x86-64", "elf64-x86-64") */
 ENTRY(main)
-KERN_LOAD_ADDR = 0xffffffff80000000;
+KERN_LOAD_ADDR = 0xffffffff00000000;
 
 SECTIONS
 {
-	/* Entry Linked and loaded at 0x00810000 */
-	. = 0x00810000;
+	/* Entry Linked and loaded at 0x80810000 */
+	. = 0x80810000;
 
 	.bootstrap : {
 		*(.boottext .bootdata)