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@@ -107,7 +107,7 @@ tbdffmt(Fmt* fmt)
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if((p = malloc(READSTR)) == nil)
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if((p = malloc(READSTR)) == nil)
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return fmtstrcpy(fmt, "(tbdfconv)");
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return fmtstrcpy(fmt, "(tbdfconv)");
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-
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+
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switch(fmt->r){
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switch(fmt->r){
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case 'T':
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case 'T':
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tbdf = va_arg(fmt->args, int);
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tbdf = va_arg(fmt->args, int);
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@@ -188,7 +188,7 @@ pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
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ioa = *pioa;
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ioa = *pioa;
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mema = *pmema;
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mema = *pmema;
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- DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
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+ DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
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wrreg, root->tbdf, mema, ioa);
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wrreg, root->tbdf, mema, ioa);
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ntb = 0;
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ntb = 0;
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@@ -513,7 +513,7 @@ pciscan(int bno, Pcidev **list)
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return ubn;
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return ubn;
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}
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}
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-static uchar
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+static uchar
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pIIxget(Pcidev *router, uchar link)
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pIIxget(Pcidev *router, uchar link)
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{
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{
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uchar pirq;
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uchar pirq;
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@@ -523,13 +523,13 @@ pIIxget(Pcidev *router, uchar link)
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return (pirq < 16)? pirq: 0;
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return (pirq < 16)? pirq: 0;
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}
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}
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-static void
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+static void
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pIIxset(Pcidev *router, uchar link, uchar irq)
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pIIxset(Pcidev *router, uchar link, uchar irq)
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{
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{
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pcicfgw8(router, link, irq);
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pcicfgw8(router, link, irq);
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}
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}
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-static uchar
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+static uchar
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viaget(Pcidev *router, uchar link)
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viaget(Pcidev *router, uchar link)
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{
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{
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uchar pirq;
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uchar pirq;
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@@ -540,7 +540,7 @@ viaget(Pcidev *router, uchar link)
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return (link & 1)? (pirq >> 4): (pirq & 15);
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return (link & 1)? (pirq >> 4): (pirq & 15);
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}
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}
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-static void
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+static void
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viaset(Pcidev *router, uchar link, uchar irq)
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viaset(Pcidev *router, uchar link, uchar irq)
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{
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{
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uchar pirq;
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uchar pirq;
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@@ -551,7 +551,7 @@ viaset(Pcidev *router, uchar link, uchar irq)
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pcicfgw8(router, 0x55 + (link>>1), pirq);
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pcicfgw8(router, 0x55 + (link>>1), pirq);
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}
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}
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-static uchar
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+static uchar
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optiget(Pcidev *router, uchar link)
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optiget(Pcidev *router, uchar link)
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{
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{
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uchar pirq = 0;
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uchar pirq = 0;
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@@ -562,7 +562,7 @@ optiget(Pcidev *router, uchar link)
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return (link & 0x10)? (pirq >> 4): (pirq & 15);
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return (link & 0x10)? (pirq >> 4): (pirq & 15);
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}
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}
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-static void
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+static void
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optiset(Pcidev *router, uchar link, uchar irq)
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optiset(Pcidev *router, uchar link, uchar irq)
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{
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{
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uchar pirq;
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uchar pirq;
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@@ -573,7 +573,7 @@ optiset(Pcidev *router, uchar link, uchar irq)
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pcicfgw8(router, 0xb8 + (link >> 5), pirq);
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pcicfgw8(router, 0xb8 + (link >> 5), pirq);
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}
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}
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-static uchar
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+static uchar
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aliget(Pcidev *router, uchar link)
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aliget(Pcidev *router, uchar link)
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{
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{
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/* No, you're not dreaming */
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/* No, you're not dreaming */
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@@ -585,7 +585,7 @@ aliget(Pcidev *router, uchar link)
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return (link & 1)? map[pirq&15]: map[pirq>>4];
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return (link & 1)? map[pirq&15]: map[pirq>>4];
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}
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}
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-static void
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+static void
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aliset(Pcidev *router, uchar link, uchar irq)
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aliset(Pcidev *router, uchar link, uchar irq)
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{
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{
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/* Inverse of map in aliget */
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/* Inverse of map in aliget */
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@@ -598,7 +598,7 @@ aliset(Pcidev *router, uchar link, uchar irq)
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pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
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pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
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}
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}
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-static uchar
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+static uchar
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cyrixget(Pcidev *router, uchar link)
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cyrixget(Pcidev *router, uchar link)
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{
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{
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uchar pirq;
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uchar pirq;
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@@ -608,7 +608,7 @@ cyrixget(Pcidev *router, uchar link)
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return ((link & 1)? pirq >> 4: pirq & 15);
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return ((link & 1)? pirq >> 4: pirq & 15);
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}
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}
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-static void
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+static void
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cyrixset(Pcidev *router, uchar link, uchar irq)
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cyrixset(Pcidev *router, uchar link, uchar irq)
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{
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{
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uchar pirq;
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uchar pirq;
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@@ -625,69 +625,69 @@ struct Bridge
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ushort vid;
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ushort vid;
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ushort did;
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ushort did;
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uchar (*get)(Pcidev *, uchar);
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uchar (*get)(Pcidev *, uchar);
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- void (*set)(Pcidev *, uchar, uchar);
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+ void (*set)(Pcidev *, uchar, uchar);
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};
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};
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static Bridge southbridges[] = {
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static Bridge southbridges[] = {
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- { 0x8086, 0x122e, pIIxget, pIIxset }, // Intel 82371FB
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- { 0x8086, 0x1234, pIIxget, pIIxset }, // Intel 82371MX
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- { 0x8086, 0x7000, pIIxget, pIIxset }, // Intel 82371SB
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- { 0x8086, 0x7110, pIIxget, pIIxset }, // Intel 82371AB
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- { 0x8086, 0x7198, pIIxget, pIIxset }, // Intel 82443MX (fn 1)
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- { 0x8086, 0x2410, pIIxget, pIIxset }, // Intel 82801AA
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- { 0x8086, 0x2420, pIIxget, pIIxset }, // Intel 82801AB
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- { 0x8086, 0x2440, pIIxget, pIIxset }, // Intel 82801BA
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- { 0x8086, 0x244c, pIIxget, pIIxset }, // Intel 82801BAM
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- { 0x8086, 0x2480, pIIxget, pIIxset }, // Intel 82801CA
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- { 0x8086, 0x248c, pIIxget, pIIxset }, // Intel 82801CAM
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- { 0x8086, 0x24c0, pIIxget, pIIxset }, // Intel 82801DBL
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- { 0x8086, 0x24cc, pIIxget, pIIxset }, // Intel 82801DBM
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- { 0x8086, 0x24d0, pIIxget, pIIxset }, // Intel 82801EB
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- { 0x8086, 0x2640, pIIxget, pIIxset }, // Intel 82801FB
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- { 0x8086, 0x27b8, pIIxget, pIIxset }, // Intel 82801GB
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- { 0x8086, 0x27b9, pIIxget, pIIxset }, // Intel 82801GBM
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- { 0x1106, 0x0586, viaget, viaset }, // Viatech 82C586
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- { 0x1106, 0x0596, viaget, viaset }, // Viatech 82C596
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- { 0x1106, 0x0686, viaget, viaset }, // Viatech 82C686
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- { 0x1106, 0x3227, viaget, viaset }, // Viatech VT8237
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- { 0x1045, 0xc700, optiget, optiset }, // Opti 82C700
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- { 0x10b9, 0x1533, aliget, aliset }, // Al M1533
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- { 0x1039, 0x0008, pIIxget, pIIxset }, // SI 503
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- { 0x1039, 0x0496, pIIxget, pIIxset }, // SI 496
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- { 0x1078, 0x0100, cyrixget, cyrixset }, // Cyrix 5530 Legacy
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-
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- { 0x1022, 0x746B, nil, nil }, // AMD 8111
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- { 0x10DE, 0x00D1, nil, nil }, // NVIDIA nForce 3
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- { 0x1166, 0x0200, nil, nil }, // ServerWorks ServerSet III LE
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- { 0x1002, 0x4377, nil, nil }, // ATI Radeon Xpress 200M
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- { 0x1002, 0x4372, nil, nil }, // ATI SB400
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+ { 0x8086, 0x122e, pIIxget, pIIxset }, /* Intel 82371FB */
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+ { 0x8086, 0x1234, pIIxget, pIIxset }, /* Intel 82371MX */
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+ { 0x8086, 0x7000, pIIxget, pIIxset }, /* Intel 82371SB */
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+ { 0x8086, 0x7110, pIIxget, pIIxset }, /* Intel 82371AB */
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+ { 0x8086, 0x7198, pIIxget, pIIxset }, /* Intel 82443MX (fn 1) */
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+ { 0x8086, 0x2410, pIIxget, pIIxset }, /* Intel 82801AA */
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+ { 0x8086, 0x2420, pIIxget, pIIxset }, /* Intel 82801AB */
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+ { 0x8086, 0x2440, pIIxget, pIIxset }, /* Intel 82801BA */
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+ { 0x8086, 0x244c, pIIxget, pIIxset }, /* Intel 82801BAM */
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+ { 0x8086, 0x2480, pIIxget, pIIxset }, /* Intel 82801CA */
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+ { 0x8086, 0x248c, pIIxget, pIIxset }, /* Intel 82801CAM */
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+ { 0x8086, 0x24c0, pIIxget, pIIxset }, /* Intel 82801DBL */
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+ { 0x8086, 0x24cc, pIIxget, pIIxset }, /* Intel 82801DBM */
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+ { 0x8086, 0x24d0, pIIxget, pIIxset }, /* Intel 82801EB */
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+ { 0x8086, 0x2640, pIIxget, pIIxset }, /* Intel 82801FB */
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+ { 0x8086, 0x27b8, pIIxget, pIIxset }, /* Intel 82801GB */
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+ { 0x8086, 0x27b9, pIIxget, pIIxset }, /* Intel 82801GBM */
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+ { 0x1106, 0x0586, viaget, viaset }, /* Viatech 82C586 */
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+ { 0x1106, 0x0596, viaget, viaset }, /* Viatech 82C596 */
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+ { 0x1106, 0x0686, viaget, viaset }, /* Viatech 82C686 */
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+ { 0x1106, 0x3227, viaget, viaset }, /* Viatech VT8237 */
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+ { 0x1045, 0xc700, optiget, optiset }, /* Opti 82C700 */
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+ { 0x10b9, 0x1533, aliget, aliset }, /* Al M1533 */
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+ { 0x1039, 0x0008, pIIxget, pIIxset }, /* SI 503 */
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+ { 0x1039, 0x0496, pIIxget, pIIxset }, /* SI 496 */
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+ { 0x1078, 0x0100, cyrixget, cyrixset }, /* Cyrix 5530 Legacy */
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+
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+ { 0x1022, 0x746B, nil, nil }, /* AMD 8111 */
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+ { 0x10DE, 0x00D1, nil, nil }, /* NVIDIA nForce 3 */
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+ { 0x1166, 0x0200, nil, nil }, /* ServerWorks ServerSet III LE */
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+ { 0x1002, 0x4377, nil, nil }, /* ATI Radeon Xpress 200M */
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+ { 0x1002, 0x4372, nil, nil }, /* ATI SB400 */
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};
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};
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typedef struct Slot Slot;
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typedef struct Slot Slot;
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struct Slot {
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struct Slot {
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- uchar bus; // Pci bus number
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- uchar dev; // Pci device number
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- uchar maps[12]; // Avoid structs! Link and mask.
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- uchar slot; // Add-in/built-in slot
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+ uchar bus; /* Pci bus number */
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+ uchar dev; /* Pci device number */
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+ uchar maps[12]; /* Avoid structs! Link and mask. */
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+ uchar slot; /* Add-in/built-in slot */
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uchar reserved;
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uchar reserved;
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};
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};
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typedef struct Router Router;
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typedef struct Router Router;
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struct Router {
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struct Router {
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- uchar signature[4]; // Routing table signature
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- uchar version[2]; // Version number
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- uchar size[2]; // Total table size
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- uchar bus; // Interrupt router bus number
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- uchar devfn; // Router's devfunc
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- uchar pciirqs[2]; // Exclusive PCI irqs
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- uchar compat[4]; // Compatible PCI interrupt router
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- uchar miniport[4]; // Miniport data
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+ uchar signature[4]; /* Routing table signature */
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+ uchar version[2]; /* Version number */
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+ uchar size[2]; /* Total table size */
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+ uchar bus; /* Interrupt router bus number */
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+ uchar devfn; /* Router's devfunc */
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+ uchar pciirqs[2]; /* Exclusive PCI irqs */
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+ uchar compat[4]; /* Compatible PCI interrupt router */
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+ uchar miniport[4]; /* Miniport data */
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uchar reserved[11];
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uchar reserved[11];
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uchar checksum;
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uchar checksum;
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};
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};
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-static ushort pciirqs; // Exclusive PCI irqs
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-static Bridge *southbridge; // Which southbridge to use.
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+static ushort pciirqs; /* Exclusive PCI irqs */
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+static Bridge *southbridge; /* Which southbridge to use. */
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static void
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static void
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pcirouting(void)
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pcirouting(void)
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@@ -698,7 +698,7 @@ pcirouting(void)
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Pcidev *sbpci, *pci;
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Pcidev *sbpci, *pci;
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uchar *p, pin, irq, link, *map;
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uchar *p, pin, irq, link, *map;
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- // Search for PCI interrupt routing table in BIOS
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+ /* Search for PCI interrupt routing table in BIOS */
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for(p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
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for(p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
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if(p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
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if(p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
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break;
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break;
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@@ -709,7 +709,7 @@ pcirouting(void)
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r = (Router *)p;
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r = (Router *)p;
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// print("PCI interrupt routing table version %d.%d at %.6uX\n",
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// print("PCI interrupt routing table version %d.%d at %.6uX\n",
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- // r->version[0], r->version[1], (ulong)r & 0xfffff);
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+ // r->version[0], r->version[1], (ulong)r & 0xfffff);
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tbdf = (BusPCI << 24)|(r->bus << 16)|(r->devfn << 8);
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tbdf = (BusPCI << 24)|(r->bus << 16)|(r->devfn << 8);
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sbpci = pcimatchtbdf(tbdf);
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sbpci = pcimatchtbdf(tbdf);
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@@ -734,21 +734,22 @@ pcirouting(void)
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size = (r->size[1] << 8)|r->size[0];
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size = (r->size[1] << 8)|r->size[0];
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for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
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for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
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- // print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
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- // for (i = 0; i != 4; i++) {
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- // uchar *m = &e->maps[i * 3];
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- // print("[%d] %.2uX %.4uX ",
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- // i, m[0], (m[2] << 8)|m[1]);
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- // }
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- // print("\n");
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-
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+ if (0) {
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+ print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
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+ for (i = 0; i != 4; i++) {
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+ uchar *m = &e->maps[i * 3];
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+ print("[%d] %.2uX %.4uX ",
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+ i, m[0], (m[2] << 8)|m[1]);
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+ }
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+ print("\n");
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+ }
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for(fn = 0; fn != 8; fn++) {
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for(fn = 0; fn != 8; fn++) {
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tbdf = (BusPCI << 24)|(e->bus << 16)|((e->dev | fn) << 8);
|
|
tbdf = (BusPCI << 24)|(e->bus << 16)|((e->dev | fn) << 8);
|
|
pci = pcimatchtbdf(tbdf);
|
|
pci = pcimatchtbdf(tbdf);
|
|
if(pci == nil)
|
|
if(pci == nil)
|
|
continue;
|
|
continue;
|
|
pin = pcicfgr8(pci, PciINTP);
|
|
pin = pcicfgr8(pci, PciINTP);
|
|
- if(pin == 0 || pin == 0xff)
|
|
|
|
|
|
+ if(pin == 0 || pin == 0xff)
|
|
continue;
|
|
continue;
|
|
|
|
|
|
map = &e->maps[(pin - 1) * 3];
|
|
map = &e->maps[(pin - 1) * 3];
|
|
@@ -940,7 +941,7 @@ pcicfginit(void)
|
|
outb(PciCSE, n);
|
|
outb(PciCSE, n);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
if(pcicfgmode < 0 || pcibios) {
|
|
if(pcicfgmode < 0 || pcibios) {
|
|
if((pcibiossi = pcibiosinit()) == nil)
|
|
if((pcibiossi = pcibiosinit()) == nil)
|
|
goto out;
|
|
goto out;
|
|
@@ -976,7 +977,7 @@ pcicfginit(void)
|
|
|
|
|
|
/*
|
|
/*
|
|
* If we have found a PCI-to-Cardbus bridge, make sure
|
|
* If we have found a PCI-to-Cardbus bridge, make sure
|
|
- * it has no valid mappings anymore.
|
|
|
|
|
|
+ * it has no valid mappings anymore.
|
|
*/
|
|
*/
|
|
for(pci = pciroot; pci != nil; pci = pci->link){
|
|
for(pci = pciroot; pci != nil; pci = pci->link){
|
|
if (pci->ccrb == 6 && pci->ccru == 7) {
|
|
if (pci->ccrb == 6 && pci->ccru == 7) {
|
|
@@ -999,7 +1000,7 @@ pcicfginit(void)
|
|
* Work out how big the top bus is
|
|
* Work out how big the top bus is
|
|
*/
|
|
*/
|
|
pcibussize(pciroot, &mema, &ioa);
|
|
pcibussize(pciroot, &mema, &ioa);
|
|
-
|
|
|
|
|
|
+
|
|
/*
|
|
/*
|
|
* Align the windows and map it
|
|
* Align the windows and map it
|
|
*/
|
|
*/
|
|
@@ -1010,7 +1011,7 @@ pcicfginit(void)
|
|
|
|
|
|
pcibusmap(pciroot, &mema, &ioa, 1);
|
|
pcibusmap(pciroot, &mema, &ioa, 1);
|
|
DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
|
|
DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
|
|
-
|
|
|
|
|
|
+
|
|
unlock(&pcicfginitlock);
|
|
unlock(&pcicfginitlock);
|
|
return;
|
|
return;
|
|
}
|
|
}
|
|
@@ -1031,7 +1032,7 @@ pcireservemem(void)
|
|
{
|
|
{
|
|
int i;
|
|
int i;
|
|
Pcidev *p;
|
|
Pcidev *p;
|
|
-
|
|
|
|
|
|
+
|
|
/*
|
|
/*
|
|
* mark all the physical address space claimed by pci devices
|
|
* mark all the physical address space claimed by pci devices
|
|
* as in use, so that upaalloc doesn't give it out.
|
|
* as in use, so that upaalloc doesn't give it out.
|
|
@@ -1301,7 +1302,7 @@ pcilhinv(Pcidev* p)
|
|
if(p->bridge != nil)
|
|
if(p->bridge != nil)
|
|
pcilhinv(p->bridge);
|
|
pcilhinv(p->bridge);
|
|
p = p->link;
|
|
p = p->link;
|
|
- }
|
|
|
|
|
|
+ }
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
void
|