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+/*
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+ * Realtek RTL8110S/8169S.
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+ * Mostly there. There are some magic register values used
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+ * which are not described in any datasheet or driver but seem
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+ * to be necessary.
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+ * No tuning has been done. Only tested on an RTL8110S, there
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+ * are slight differences between the chips in the series so some
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+ * tweaks may be needed.
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+ */
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+#include "etherdat.h"
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+#include "etherif.h"
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+#include "ethermii.h"
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+#include "compat.h"
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+
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+#define dprint(...) print("ether 8169: " __VA_ARGS__);
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+
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+enum { /* registers */
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+ Idr0 = 0x00, /* MAC address */
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+ Mar0 = 0x08, /* Multicast address */
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+ Dtccr = 0x10, /* Dump Tally Counter Command */
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+ Tnpds = 0x20, /* Transmit Normal Priority Descriptors */
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+ Thpds = 0x28, /* Transmit High Priority Descriptors */
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+ Flash = 0x30, /* Flash Memory Read/Write */
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+ Erbcr = 0x34, /* Early Receive Byte Count */
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+ Ersr = 0x36, /* Early Receive Status */
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+ Cr = 0x37, /* Command Register */
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+ Tppoll = 0x38, /* Transmit Priority Polling */
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+ Imr = 0x3C, /* Interrupt Mask */
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+ Isr = 0x3E, /* Interrupt Status */
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+ Tcr = 0x40, /* Transmit Configuration */
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+ Rcr = 0x44, /* Receive Configuration */
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+ Tctr = 0x48, /* Timer Count */
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+ Mpc = 0x4C, /* Missed Packet Counter */
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+ Cr9346 = 0x50, /* 9346 Command Register */
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+ Config0 = 0x51, /* Configuration Register 0 */
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+ Config1 = 0x52, /* Configuration Register 1 */
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+ Config2 = 0x53, /* Configuration Register 2 */
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+ Config3 = 0x54, /* Configuration Register 3 */
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+ Config4 = 0x55, /* Configuration Register 4 */
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+ Config5 = 0x56, /* Configuration Register 5 */
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+ Timerint = 0x58, /* Timer Interrupt */
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+ Mulint = 0x5C, /* Multiple Interrupt Select */
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+ Phyar = 0x60, /* PHY Access */
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+ Tbicsr0 = 0x64, /* TBI Control and Status */
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+ Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
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+ Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
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+ Phystatus = 0x6C, /* PHY Status */
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+
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+ Rms = 0xDA, /* Receive Packet Maximum Size */
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+ Cplusc = 0xE0, /* C+ Command */
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+ Rdsar = 0xE4, /* Receive Descriptor Start Address */
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+ Mtps = 0xEC, /* Max. Transmit Packet Size */
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+};
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+
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+enum { /* Dtccr */
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+ Cmd = 0x00000008, /* Command */
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+};
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+
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+enum { /* Cr */
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+ Te = 0x04, /* Transmitter Enable */
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+ Re = 0x08, /* Receiver Enable */
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+ Rst = 0x10, /* Software Reset */
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+};
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+
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+enum { /* Tppoll */
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+ Fswint = 0x01, /* Forced Software Interrupt */
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+ Npq = 0x40, /* Normal Priority Queue polling */
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+ Hpq = 0x80, /* High Priority Queue polling */
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+};
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+
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+enum { /* Imr/Isr */
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+ Rok = 0x0001, /* Receive OK */
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+ Rer = 0x0002, /* Receive Error */
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+ Tok = 0x0004, /* Transmit OK */
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+ Ter = 0x0008, /* Transmit Error */
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+ Rdu = 0x0010, /* Receive Descriptor Unavailable */
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+ Punlc = 0x0020, /* Packet Underrun or Link Change */
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+ Fovw = 0x0040, /* Receive FIFO Overflow */
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+ Tdu = 0x0080, /* Transmit Descriptor Unavailable */
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+ Swint = 0x0100, /* Software Interrupt */
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+ Timeout = 0x4000, /* Timer */
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+ Serr = 0x8000, /* System Error */
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+};
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+
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+enum { /* Tcr */
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+ MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
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+ MtxdmaMASK = 0x00000700,
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+ Mtxdmaunlimited = 0x00000700,
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+ Acrc = 0x00010000, /* Append CRC (not) */
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+ Lbk0 = 0x00020000, /* Loopback Test 0 */
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+ Lbk1 = 0x00040000, /* Loopback Test 1 */
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+ Ifg2 = 0x00080000, /* Interframe Gap 2 */
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+ HwveridSHIFT = 23, /* Hardware Version ID */
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+ HwveridMASK = 0x7C800000,
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+ Macv01 = 0x00000000, /* RTL8169 */
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+ Macv02 = 0x00800000, /* RTL8169S/8110S */
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+ Macv03 = 0x04000000, /* RTL8169S/8110S */
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+ Macv04 = 0x10000000, /* RTL8169SB/8110SB */
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+ Macv05 = 0x18000000, /* RTL8169SC/8110SC */
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+ Macv11 = 0x30000000, /* RTL8168B/8111B */
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+ Macv12 = 0x38000000, /* RTL8169B/8111B */
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+ Macv13 = 0x34000000, /* RTL8101E */
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+ Macv14 = 0x30800000, /* RTL8100E */
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+ Macv15 = 0x38800000, /* RTL8100E */
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+ Ifg0 = 0x01000000, /* Interframe Gap 0 */
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+ Ifg1 = 0x02000000, /* Interframe Gap 1 */
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+};
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+
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+enum { /* Rcr */
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+ Aap = 0x00000001, /* Accept All Packets */
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+ Apm = 0x00000002, /* Accept Physical Match */
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+ Am = 0x00000004, /* Accept Multicast */
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+ Ab = 0x00000008, /* Accept Broadcast */
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+ Ar = 0x00000010, /* Accept Runt */
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+ Aer = 0x00000020, /* Accept Error */
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+ Sel9356 = 0x00000040, /* 9356 EEPROM used */
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+ MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
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+ MrxdmaMASK = 0x00000700,
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+ Mrxdmaunlimited = 0x00000700,
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+ RxfthSHIFT = 13, /* Receive Buffer Length */
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+ RxfthMASK = 0x0000E000,
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+ Rxfth256 = 0x00008000,
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+ Rxfthnone = 0x0000E000,
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+ Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
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+ MulERINT = 0x01000000, /* Multiple Early Interrupt Select */
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+};
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+
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+enum { /* Cr9346 */
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+ Eedo = 0x01, /* */
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+ Eedi = 0x02, /* */
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+ Eesk = 0x04, /* */
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+ Eecs = 0x08, /* */
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+ Eem0 = 0x40, /* Operating Mode */
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+ Eem1 = 0x80,
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+};
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+
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+enum { /* Phyar */
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+ DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */
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+ DataSHIFT = 0,
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+ RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */
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+ RegaddrSHIFT = 16,
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+ PhyFlag = 0x80000000, /* */
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+};
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+
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+enum { /* Phystatus */
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+ Fd = 0x01, /* Full Duplex */
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+ Linksts = 0x02, /* Link Status */
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+ Speed10 = 0x04, /* */
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+ Speed100 = 0x08, /* */
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+ Speed1000 = 0x10, /* */
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+ Rxflow = 0x20, /* */
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+ Txflow = 0x40, /* */
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+ Entbi = 0x80, /* */
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+};
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+
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+enum { /* Cplusc */
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+ Mulrw = 0x0008, /* PCI Multiple R/W Enable */
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+ Dac = 0x0010, /* PCI Dual Address Cycle Enable */
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+ Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
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+ Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */
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+ Endian = 0x0200, /* Endian Mode */
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+};
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+
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+typedef struct D D; /* Transmit/Receive Descriptor */
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+struct D {
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+ u32int control;
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+ u32int vlan;
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+ u32int addrlo;
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+ u32int addrhi;
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+};
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+
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+enum { /* Transmit Descriptor control */
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+ TxflMASK = 0x0000FFFF, /* Transmit Frame Length */
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+ TxflSHIFT = 0,
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+ Tcps = 0x00010000, /* TCP Checksum Offload */
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+ Udpcs = 0x00020000, /* UDP Checksum Offload */
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+ Ipcs = 0x00040000, /* IP Checksum Offload */
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+ Lgsen = 0x08000000, /* Large Send */
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+};
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+
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+enum { /* Receive Descriptor control */
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+ RxflMASK = 0x00003FFF, /* Receive Frame Length */
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+ RxflSHIFT = 0,
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+ Tcpf = 0x00004000, /* TCP Checksum Failure */
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+ Udpf = 0x00008000, /* UDP Checksum Failure */
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+ Ipf = 0x00010000, /* IP Checksum Failure */
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+ Pid0 = 0x00020000, /* Protocol ID0 */
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+ Pid1 = 0x00040000, /* Protocol ID1 */
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+ Crce = 0x00080000, /* CRC Error */
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+ Runt = 0x00100000, /* Runt Packet */
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+ Res = 0x00200000, /* Receive Error Summary */
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+ Rwt = 0x00400000, /* Receive Watchdog Timer Expired */
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+ Fovf = 0x00800000, /* FIFO Overflow */
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+ Bovf = 0x01000000, /* Buffer Overflow */
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+ Bar = 0x02000000, /* Broadcast Address Received */
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+ Pam = 0x04000000, /* Physical Address Matched */
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+ Mar = 0x08000000, /* Multicast Address Received */
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+};
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+
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+enum { /* General Descriptor control */
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+ Ls = 0x10000000, /* Last Segment Descriptor */
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+ Fs = 0x20000000, /* First Segment Descriptor */
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+ Eor = 0x40000000, /* End of Descriptor Ring */
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+ Own = 0x80000000, /* Ownership */
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+};
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+
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+/*
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+ */
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+enum { /* Ring sizes (<= 1024) */
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+ Ntd = 32, /* Transmit Ring */
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+ Nrd = 128, /* Receive Ring */
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+
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+ Mps = ROUNDUP(ETHERMAXTU+4, 128),
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+};
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+
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+typedef struct Dtcc Dtcc;
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+struct Dtcc {
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+ u64int txok;
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+ u64int rxok;
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+ u64int txer;
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+ u32int rxer;
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+ u16int misspkt;
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+ u16int fae;
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+ u32int tx1col;
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+ u32int txmcol;
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+ u64int rxokph;
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+ u64int rxokbrd;
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+ u32int rxokmu;
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+ u16int txabt;
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+ u16int txundrn;
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+};
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+
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+enum { /* Variants */
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+ Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E ? */
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+ Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */
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+ Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */
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+ Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B */
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+ Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */
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+};
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+
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+typedef struct Ctlr Ctlr;
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+typedef struct Ctlr {
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+ int port;
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+ Pcidev* pcidev;
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+ Ctlr* next;
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+ int active;
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+
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+ QLock alock; /* attach */
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+ Lock ilock; /* init */
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+ int init; /* */
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+
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+ int pciv; /* */
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+ int macv; /* MAC version */
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+ int phyv; /* PHY version */
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+
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+ Mii* mii;
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+
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+ Lock tlock; /* transmit */
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+ D* td; /* descriptor ring */
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+ Block** tb; /* transmit buffers */
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+ int ntd;
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+
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+ int tdh; /* head - producer index (host) */
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+ int tdt; /* tail - consumer index (NIC) */
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+ int ntdfree;
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+ int ntq;
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+
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+ int mtps; /* Max. Transmit Packet Size */
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+
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+ Lock rlock; /* receive */
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+ D* rd; /* descriptor ring */
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+ Block** rb; /* receive buffers */
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+ int nrd;
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+
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+ int rdh; /* head - producer index (NIC) */
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+ int rdt; /* tail - consumer index (host) */
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+ int nrdfree;
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+
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+ int tcr; /* transmit configuration register */
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+ int rcr; /* receive configuration register */
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+ int imr;
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+
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+ QLock slock; /* statistics */
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+ Dtcc* dtcc;
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+ uint txdu;
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+ uint tcpf;
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+ uint udpf;
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+ uint ipf;
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+ uint fovf;
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+ uint ierrs;
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+ uint rer;
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+ uint rdu;
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+ uint punlc;
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+ uint fovw;
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+} Ctlr;
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+
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+static Ctlr* rtl8169ctlrhead;
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+static Ctlr* rtl8169ctlrtail;
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+
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+#define csr8r(c, r) (inb((c)->port+(r)))
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+#define csr16r(c, r) (ins((c)->port+(r)))
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+#define csr32r(c, r) (inl((c)->port+(r)))
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+#define csr8w(c, r, b) (outb((c)->port+(r), (u8int)(b)))
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+#define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
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+#define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
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+
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+static int
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+rtl8169miimir(Mii* mii, int pa, int ra)
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+{
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+ uint r;
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+ int timeo;
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+ Ctlr *ctlr;
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+
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+ if(pa != 1)
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+ return -1;
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+ ctlr = mii->ctlr;
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+
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+ r = (ra<<16) & RegaddrMASK;
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+ csr32w(ctlr, Phyar, r);
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+ delay(1);
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+ for(timeo = 0; timeo < 2000; timeo++){
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+ if((r = csr32r(ctlr, Phyar)) & PhyFlag)
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+ break;
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+ microdelay(100);
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+ }
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+ if(!(r & PhyFlag))
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+ return -1;
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+
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+ return (r & DataMASK)>>DataSHIFT;
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+}
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+
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+static int
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+rtl8169miimiw(Mii* mii, int pa, int ra, int data)
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+{
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+ uint r;
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+ int timeo;
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+ Ctlr *ctlr;
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+
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+ if(pa != 1)
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+ return -1;
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+ ctlr = mii->ctlr;
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+
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+ r = PhyFlag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
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+ csr32w(ctlr, Phyar, r);
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+ delay(1);
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+ for(timeo = 0; timeo < 2000; timeo++){
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+ if(!((r = csr32r(ctlr, Phyar)) & PhyFlag))
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+ break;
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+ microdelay(100);
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+ }
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+ if(r & PhyFlag)
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+ return -1;
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+
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+ return 0;
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+}
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+
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+static int
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+rtl8169mii(Ctlr* ctlr)
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+{
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+ MiiPhy *phy;
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+
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+ /*
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+ * Link management.
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+ */
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+ if((ctlr->mii = malloc(sizeof(Mii))) == nil)
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+ return -1;
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+ ctlr->mii->mir = rtl8169miimir;
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+ ctlr->mii->miw = rtl8169miimiw;
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+ ctlr->mii->ctlr = ctlr;
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+
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+ /*
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+ * Get rev number out of Phyidr2 so can config properly.
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+ * There's probably more special stuff for Macv0[234] needed here.
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+ */
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+ ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
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+ if(ctlr->macv == Macv02){
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+ csr8w(ctlr, 0x82, 1); /* magic */
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+ rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
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+ }
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+
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+ if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
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+ free(ctlr->mii);
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+ ctlr->mii = nil;
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+ return -1;
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+ }
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+ print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
|
|
|
+ phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
|
|
|
+
|
|
|
+ miiane(ctlr->mii, ~0, ~0, ~0);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void
|
|
|
+rtl8169promiscuous(void* arg, int on)
|
|
|
+{
|
|
|
+ Ether *edev;
|
|
|
+ Ctlr * ctlr;
|
|
|
+
|
|
|
+ edev = arg;
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ ilock(&ctlr->ilock);
|
|
|
+
|
|
|
+ if(on)
|
|
|
+ ctlr->rcr |= Aap;
|
|
|
+ else
|
|
|
+ ctlr->rcr &= ~Aap;
|
|
|
+ csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
+ iunlock(&ctlr->ilock);
|
|
|
+}
|
|
|
+
|
|
|
+#ifndef FS
|
|
|
+static long
|
|
|
+rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
|
|
|
+{
|
|
|
+ char *p;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ Dtcc *dtcc;
|
|
|
+ int i, l, r, timeo;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ qlock(&ctlr->slock);
|
|
|
+
|
|
|
+ p = nil;
|
|
|
+ if(waserror()){
|
|
|
+ qunlock(&ctlr->slock);
|
|
|
+ free(p);
|
|
|
+ nexterror();
|
|
|
+ }
|
|
|
+
|
|
|
+ csr32w(ctlr, Dtccr+4, 0);
|
|
|
+ csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
|
|
|
+ for(timeo = 0; timeo < 1000; timeo++){
|
|
|
+ if(!(csr32r(ctlr, Dtccr) & Cmd))
|
|
|
+ break;
|
|
|
+ delay(1);
|
|
|
+ }
|
|
|
+ if(csr32r(ctlr, Dtccr) & Cmd)
|
|
|
+ error(Eio);
|
|
|
+ dtcc = ctlr->dtcc;
|
|
|
+
|
|
|
+ edev->oerrs = dtcc->txer;
|
|
|
+ edev->crcs = dtcc->rxer;
|
|
|
+ edev->frames = dtcc->fae;
|
|
|
+ edev->buffs = dtcc->misspkt;
|
|
|
+ edev->overflows = ctlr->txdu+ctlr->rdu;
|
|
|
+
|
|
|
+ if(n == 0){
|
|
|
+ qunlock(&ctlr->slock);
|
|
|
+ poperror();
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ if((p = malloc(READSTR)) == nil)
|
|
|
+ error(Enomem);
|
|
|
+
|
|
|
+ l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
|
|
|
+ l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
|
|
|
+ l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
|
|
|
+ l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
|
|
|
+ l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
|
|
|
+ l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
|
|
|
+ l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
|
|
|
+ l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
|
|
|
+ l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
|
|
|
+ l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
|
|
|
+ l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
|
|
|
+ l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
|
|
|
+ l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
|
|
|
+
|
|
|
+ l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
|
|
|
+ l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
|
|
|
+ l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
|
|
|
+ l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
|
|
|
+ l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
|
|
|
+ l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
|
|
|
+ l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
|
|
|
+ l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
|
|
|
+ l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
|
|
|
+ l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
|
|
|
+
|
|
|
+ l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
|
|
|
+ l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
|
|
|
+
|
|
|
+ if(ctlr->mii != nil && ctlr->mii->curphy != nil){
|
|
|
+ l += snprint(p+l, READSTR, "phy: ");
|
|
|
+ for(i = 0; i < NMiiPhyr; i++){
|
|
|
+ if(i && ((i & 0x07) == 0))
|
|
|
+ l += snprint(p+l, READSTR-l, "\n ");
|
|
|
+ r = miimir(ctlr->mii, i);
|
|
|
+ l += snprint(p+l, READSTR-l, " %4.4ux", r);
|
|
|
+ }
|
|
|
+ snprint(p+l, READSTR-l, "\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ n = readstr(offset, a, n, p);
|
|
|
+
|
|
|
+ qunlock(&ctlr->slock);
|
|
|
+ poperror();
|
|
|
+ free(p);
|
|
|
+
|
|
|
+ return n;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169halt(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ csr8w(ctlr, Cr, 0);
|
|
|
+ csr16w(ctlr, Imr, 0);
|
|
|
+ csr16w(ctlr, Isr, ~0);
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+rtl8169reset(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ u32int r;
|
|
|
+ int timeo;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Soft reset the controller.
|
|
|
+ */
|
|
|
+ csr8w(ctlr, Cr, Rst);
|
|
|
+ for(r = timeo = 0; timeo < 1000; timeo++){
|
|
|
+ r = csr8r(ctlr, Cr);
|
|
|
+ if(!(r & Rst))
|
|
|
+ break;
|
|
|
+ delay(1);
|
|
|
+ }
|
|
|
+ rtl8169halt(ctlr);
|
|
|
+
|
|
|
+ if(r & Rst)
|
|
|
+ return -1;
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169replenish(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ D *d;
|
|
|
+ int rdt;
|
|
|
+ Block *bp;
|
|
|
+
|
|
|
+ rdt = ctlr->rdt;
|
|
|
+ while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
|
|
|
+ d = &ctlr->rd[rdt];
|
|
|
+ if(ctlr->rb[rdt] == nil){
|
|
|
+ /*
|
|
|
+ * Simple allocation for now.
|
|
|
+ * This better be aligned on 8.
|
|
|
+ */
|
|
|
+ bp = iallocb(Mps);
|
|
|
+ if(bp == nil){
|
|
|
+ iprint("no available buffers\n");
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ ctlr->rb[rdt] = bp;
|
|
|
+ d->addrlo = PCIWADDR(bp->rp);
|
|
|
+ d->addrhi = 0;
|
|
|
+ }
|
|
|
+ coherence();
|
|
|
+ d->control |= Own|Mps;
|
|
|
+ rdt = NEXT(rdt, ctlr->nrd);
|
|
|
+ ctlr->nrdfree++;
|
|
|
+ }
|
|
|
+ ctlr->rdt = rdt;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+rtl8169init(Ether* edev)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ u32int r;
|
|
|
+ Block *bp;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ u8int cplusc;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ ilock(&ctlr->ilock);
|
|
|
+
|
|
|
+ rtl8169halt(ctlr);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * MAC Address.
|
|
|
+ * Must put chip into config register write enable mode.
|
|
|
+ */
|
|
|
+ csr8w(ctlr, Cr9346, Eem1|Eem0);
|
|
|
+ r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
|
|
|
+ csr32w(ctlr, Idr0, r);
|
|
|
+ r = (edev->ea[5]<<8)|edev->ea[4];
|
|
|
+ csr32w(ctlr, Idr0+4, r);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Transmitter.
|
|
|
+ */
|
|
|
+ memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
|
|
|
+ ctlr->tdh = ctlr->tdt = 0;
|
|
|
+ ctlr->td[ctlr->ntd-1].control = Eor;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Receiver.
|
|
|
+ * Need to do something here about the multicast filter.
|
|
|
+ */
|
|
|
+ memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
|
|
|
+ ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
|
|
|
+ ctlr->rd[ctlr->nrd-1].control = Eor;
|
|
|
+
|
|
|
+ for(i = 0; i < ctlr->nrd; i++){
|
|
|
+ if((bp = ctlr->rb[i]) != nil){
|
|
|
+ ctlr->rb[i] = nil;
|
|
|
+ freeb(bp);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ rtl8169replenish(ctlr);
|
|
|
+ ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Apm;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Mtps is in units of 128 except for the RTL8169
|
|
|
+ * where is is 32. If using jumbo frames should be
|
|
|
+ * set to 0x3F.
|
|
|
+ * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
|
|
|
+ * settings in Tcr/Rcr; the (1<<14) is magic.
|
|
|
+ */
|
|
|
+ ctlr->mtps = HOWMANY(Mps, 128);
|
|
|
+ cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
|
|
|
+ cplusc |= /*Rxchksum|*/Mulrw;
|
|
|
+ dprint("mac = %.2ux\n", ctlr->macv);
|
|
|
+ switch(ctlr->macv){
|
|
|
+ default:
|
|
|
+ print("bad mac %.2ux\n", ctlr->macv);
|
|
|
+ return -1;
|
|
|
+ case Macv01:
|
|
|
+ ctlr->mtps = HOWMANY(Mps, 32);
|
|
|
+ break;
|
|
|
+ case Macv02:
|
|
|
+ case Macv03:
|
|
|
+ cplusc |= (1<<14); /* magic */
|
|
|
+ break;
|
|
|
+ case Macv05:
|
|
|
+ /*
|
|
|
+ * This is interpreted from clearly bogus code
|
|
|
+ * in the manufacturer-supplied driver, it could
|
|
|
+ * be wrong. Untested.
|
|
|
+ */
|
|
|
+ r = csr8r(ctlr, Config2) & 0x07;
|
|
|
+ if(r == 0x01) /* 66MHz PCI */
|
|
|
+ csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
|
|
|
+ else
|
|
|
+ csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
|
|
|
+ pciclrmwi(ctlr->pcidev);
|
|
|
+ break;
|
|
|
+ case Macv13:
|
|
|
+ /*
|
|
|
+ * This is interpreted from clearly bogus code
|
|
|
+ * in the manufacturer-supplied driver, it could
|
|
|
+ * be wrong. Untested.
|
|
|
+ */
|
|
|
+ pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */
|
|
|
+ pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */
|
|
|
+ break;
|
|
|
+ case Macv04:
|
|
|
+ case Macv11:
|
|
|
+ case Macv12:
|
|
|
+ case Macv14:
|
|
|
+ case Macv15:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Enable receiver/transmitter.
|
|
|
+ * Need to do this first or some of the settings below
|
|
|
+ * won't take.
|
|
|
+ */
|
|
|
+ switch(ctlr->pciv){
|
|
|
+ default:
|
|
|
+ csr8w(ctlr, Cr, Te|Re);
|
|
|
+ csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
|
|
|
+ csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
+ case Rtl8169sc:
|
|
|
+ case Rtl8168b:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Interrupts.
|
|
|
+ * Disable Tdu|Tok for now, the transmit routine will tidy.
|
|
|
+ * Tdu means the NIC ran out of descriptors to send, so it
|
|
|
+ * doesn't really need to ever be on.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Timerint, 0);
|
|
|
+ ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok;
|
|
|
+ csr16w(ctlr, Imr, ctlr->imr);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Clear missed-packet counter;
|
|
|
+ * initial early transmit threshold value;
|
|
|
+ * set the descriptor ring base addresses;
|
|
|
+ * set the maximum receive packet size;
|
|
|
+ * no early-receive interrupts.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Mpc, 0);
|
|
|
+ csr8w(ctlr, Mtps, ctlr->mtps);
|
|
|
+ csr32w(ctlr, Tnpds+4, 0);
|
|
|
+ csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
|
|
|
+ csr32w(ctlr, Rdsar+4, 0);
|
|
|
+ csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
|
|
|
+ csr16w(ctlr, Rms, Mps);
|
|
|
+ r = csr16r(ctlr, Mulint) & 0xF000;
|
|
|
+ csr16w(ctlr, Mulint, r);
|
|
|
+ csr16w(ctlr, Cplusc, cplusc);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set configuration.
|
|
|
+ */
|
|
|
+ switch(ctlr->pciv){
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ case Rtl8169sc:
|
|
|
+ csr16w(ctlr, 0xE2, 0); /* magic */
|
|
|
+ csr8w(ctlr, Cr, Te|Re);
|
|
|
+ csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
|
|
|
+ csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
+ break;
|
|
|
+ case Rtl8168b:
|
|
|
+ case Rtl8169c:
|
|
|
+ csr16w(ctlr, 0xE2, 0); /* magic */
|
|
|
+ csr16w(ctlr, Cplusc, 0x2000); /* magic */
|
|
|
+ csr8w(ctlr, Cr, Te|Re);
|
|
|
+ csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
|
|
|
+ csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
+ csr16w(ctlr, Rms, 0x0800);
|
|
|
+ csr8w(ctlr, Mtps, 0x3F);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ ctlr->tcr = csr32r(ctlr, Tcr);
|
|
|
+ csr8w(ctlr, Cr9346, 0);
|
|
|
+
|
|
|
+ iunlock(&ctlr->ilock);
|
|
|
+
|
|
|
+// rtl8169mii(ctlr);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169attach(Ether* edev)
|
|
|
+{
|
|
|
+ int timeo;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ qlock(&ctlr->alock);
|
|
|
+ if(ctlr->init == 0){
|
|
|
+ /*
|
|
|
+ * Handle allocation/init errors here.
|
|
|
+ */
|
|
|
+ ctlr->td = mallocalign(sizeof(D)*Ntd, 256, 0, 0);
|
|
|
+ ctlr->tb = malloc(Ntd*sizeof(Block*));
|
|
|
+ ctlr->ntd = Ntd;
|
|
|
+ ctlr->rd = mallocalign(sizeof(D)*Nrd, 256, 0, 0);
|
|
|
+ ctlr->rb = malloc(Nrd*sizeof(Block*));
|
|
|
+ ctlr->nrd = Nrd;
|
|
|
+ ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
|
|
|
+ rtl8169init(edev);
|
|
|
+ ctlr->init = 1;
|
|
|
+ }
|
|
|
+ qunlock(&ctlr->alock);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Wait for link to be ready.
|
|
|
+ */
|
|
|
+ for(timeo = 0; timeo < 3500; timeo++){
|
|
|
+ if(miistatus(ctlr->mii) == 0)
|
|
|
+ break;
|
|
|
+ delay(10);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169link(Ether* edev)
|
|
|
+{
|
|
|
+ uint r;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Maybe the link changed - do we care very much?
|
|
|
+ * Could stall transmits if no link, maybe?
|
|
|
+ */
|
|
|
+ if(!((r = csr8r(ctlr, Phystatus)) & Linksts))
|
|
|
+ return;
|
|
|
+
|
|
|
+ if(r & Speed10)
|
|
|
+ edev->mbps = 10;
|
|
|
+ else if(r & Speed100)
|
|
|
+ edev->mbps = 100;
|
|
|
+ else if(r & Speed1000)
|
|
|
+ edev->mbps = 1000;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169transmit(Ether* edev)
|
|
|
+{
|
|
|
+ D *d;
|
|
|
+ Block *bp;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int control, x;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ ilock(&ctlr->tlock);
|
|
|
+ for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
|
|
|
+ d = &ctlr->td[x];
|
|
|
+ if((control = d->control) & Own)
|
|
|
+ break;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Check errors and log here.
|
|
|
+ */
|
|
|
+ USED(control);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Free it up.
|
|
|
+ * Need to clean the descriptor here? Not really.
|
|
|
+ * Simple freeb for now (no chain and freeblist).
|
|
|
+ * Use ntq count for now.
|
|
|
+ */
|
|
|
+ freeb(ctlr->tb[x]);
|
|
|
+ ctlr->tb[x] = nil;
|
|
|
+ d->control &= Eor;
|
|
|
+
|
|
|
+ ctlr->ntq--;
|
|
|
+ }
|
|
|
+ ctlr->tdh = x;
|
|
|
+
|
|
|
+ x = ctlr->tdt;
|
|
|
+ while(ctlr->ntq < (ctlr->ntd-1)){
|
|
|
+ if((bp = etheroq(edev)) == nil)
|
|
|
+ break;
|
|
|
+
|
|
|
+ d = &ctlr->td[x];
|
|
|
+ d->addrlo = PCIWADDR(bp->rp);
|
|
|
+ d->addrhi = 0;
|
|
|
+ ctlr->tb[x] = bp;
|
|
|
+ coherence();
|
|
|
+ d->control |= Own|Fs|Ls|((BLEN(bp)<<TxflSHIFT) & TxflMASK);
|
|
|
+
|
|
|
+ x = NEXT(x, ctlr->ntd);
|
|
|
+ ctlr->ntq++;
|
|
|
+ }
|
|
|
+ if(x != ctlr->tdt){
|
|
|
+ ctlr->tdt = x;
|
|
|
+ csr8w(ctlr, Tppoll, Npq);
|
|
|
+ }
|
|
|
+ else if(ctlr->ntq >= (ctlr->ntd-1))
|
|
|
+ ctlr->txdu++;
|
|
|
+
|
|
|
+ iunlock(&ctlr->tlock);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169receive(Ether* edev)
|
|
|
+{
|
|
|
+ D *d;
|
|
|
+ int rdh;
|
|
|
+ Block *bp;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ u32int control;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ rdh = ctlr->rdh;
|
|
|
+ for(;;){
|
|
|
+ d = &ctlr->rd[rdh];
|
|
|
+
|
|
|
+ if(d->control & Own)
|
|
|
+ break;
|
|
|
+
|
|
|
+ control = d->control;
|
|
|
+ if((control & (Fs|Ls|Res)) == (Fs|Ls)){
|
|
|
+ bp = ctlr->rb[rdh];
|
|
|
+ ctlr->rb[rdh] = nil;
|
|
|
+ SETWPCNT(bp, ((control & RxflMASK)>>RxflSHIFT)-4);
|
|
|
+ bp->next = nil;
|
|
|
+
|
|
|
+#ifndef FS
|
|
|
+ if(control & Fovf)
|
|
|
+ ctlr->fovf++;
|
|
|
+#endif
|
|
|
+
|
|
|
+ switch(control & (Pid1|Pid0)){
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ case Pid0:
|
|
|
+ if(control & Tcpf){
|
|
|
+ ctlr->tcpf++;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+#ifndef FS
|
|
|
+ bp->flag |= Btcpck;
|
|
|
+#endif
|
|
|
+ break;
|
|
|
+ case Pid1:
|
|
|
+ if(control & Udpf){
|
|
|
+ ctlr->udpf++;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+#ifndef FS
|
|
|
+ bp->flag |= Budpck;
|
|
|
+#endif
|
|
|
+ break;
|
|
|
+ case Pid1|Pid0:
|
|
|
+ if(control & Ipf){
|
|
|
+ ctlr->ipf++;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+#ifndef FS
|
|
|
+ bp->flag |= Bipck;
|
|
|
+#endif
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ ETHERIQ(edev, bp, 1);
|
|
|
+ }
|
|
|
+ else{
|
|
|
+ /*
|
|
|
+ * Error stuff here.
|
|
|
+ print("control %#8.8ux\n", control);
|
|
|
+ */
|
|
|
+ }
|
|
|
+ d->control &= Eor;
|
|
|
+ ctlr->nrdfree--;
|
|
|
+ rdh = NEXT(rdh, ctlr->nrd);
|
|
|
+
|
|
|
+ if(ctlr->nrdfree < ctlr->nrd/2)
|
|
|
+ rtl8169replenish(ctlr);
|
|
|
+ }
|
|
|
+ ctlr->rdh = rdh;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169interrupt(Ureg*, void* arg)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+ Ether *edev;
|
|
|
+ u32int isr;
|
|
|
+
|
|
|
+ edev = arg;
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
|
|
|
+ csr16w(ctlr, Isr, isr);
|
|
|
+ if((isr & ctlr->imr) == 0)
|
|
|
+ break;
|
|
|
+ if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){
|
|
|
+ rtl8169receive(edev);
|
|
|
+ if(!(isr & (Punlc|Rok)))
|
|
|
+ ctlr->ierrs++;
|
|
|
+ if(isr & Rer)
|
|
|
+ ctlr->rer++;
|
|
|
+ if(isr & Rdu)
|
|
|
+ ctlr->rdu++;
|
|
|
+ if(isr & Punlc)
|
|
|
+ ctlr->punlc++;
|
|
|
+ if(isr & Fovw)
|
|
|
+ ctlr->fovw++;
|
|
|
+ isr &= ~(Fovw|Rdu|Rer|Rok);
|
|
|
+ }
|
|
|
+
|
|
|
+ if(isr & (Tdu|Ter|Tok)){
|
|
|
+ rtl8169transmit(edev);
|
|
|
+ isr &= ~(Tdu|Ter|Tok);
|
|
|
+ }
|
|
|
+
|
|
|
+ if(isr & Punlc){
|
|
|
+ rtl8169link(edev);
|
|
|
+ isr &= ~Punlc;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Some of the reserved bits get set sometimes...
|
|
|
+ */
|
|
|
+ if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
|
|
|
+ panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux\n",
|
|
|
+ csr16r(ctlr, Imr), isr);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169pci(void)
|
|
|
+{
|
|
|
+ Pcidev *p;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int i, port;
|
|
|
+
|
|
|
+ p = nil;
|
|
|
+ while(p = pcimatch(p, 0, 0)){
|
|
|
+#ifdef FS
|
|
|
+ if(p->ccru != ((0x02<<8)|0x00))
|
|
|
+#else
|
|
|
+ if(p->ccrb != 0x02 || p->ccru != 0)
|
|
|
+#endif
|
|
|
+ continue;
|
|
|
+
|
|
|
+ dprint(" pci: found vid %ux did %ux\n", p->vid, p->did);
|
|
|
+ switch(i = ((p->did<<16)|p->vid)){
|
|
|
+ default:
|
|
|
+ continue;
|
|
|
+ case Rtl8100e: /* RTL810[01]E ? */
|
|
|
+ case Rtl8169c: /* RTL8169C */
|
|
|
+ case Rtl8169sc: /* RTL8169SC */
|
|
|
+ case Rtl8168b: /* RTL8168B */
|
|
|
+ case Rtl8169: /* RTL8169 */
|
|
|
+ break;
|
|
|
+ case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */
|
|
|
+ i = Rtl8169;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ port = p->mem[0].bar & ~0x01;
|
|
|
+ if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
|
|
|
+ print("rtl8169: port %#ux in use\n", port);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ ctlr = malloc(sizeof(Ctlr));
|
|
|
+ ctlr->port = port;
|
|
|
+ ctlr->pcidev = p;
|
|
|
+ ctlr->pciv = i;
|
|
|
+
|
|
|
+#ifndef FS
|
|
|
+ if(pcigetpms(p) > 0){
|
|
|
+ pcisetpms(p, 0);
|
|
|
+
|
|
|
+ for(i = 0; i < 6; i++)
|
|
|
+ pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
|
|
|
+ pcicfgw8(p, PciINTL, p->intl);
|
|
|
+ pcicfgw8(p, PciLTR, p->ltr);
|
|
|
+ pcicfgw8(p, PciCLS, p->cls);
|
|
|
+ pcicfgw16(p, PciPCR, p->pcr);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ if(rtl8169reset(ctlr)){
|
|
|
+ iofree(port);
|
|
|
+ free(ctlr);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Extract the chip hardware version,
|
|
|
+ * needed to configure each properly.
|
|
|
+ */
|
|
|
+ ctlr->macv = csr32r(ctlr, Tcr) & HwveridMASK;
|
|
|
+
|
|
|
+ rtl8169mii(ctlr);
|
|
|
+
|
|
|
+ pcisetbme(p);
|
|
|
+
|
|
|
+ if(rtl8169ctlrhead != nil)
|
|
|
+ rtl8169ctlrtail->next = ctlr;
|
|
|
+ else
|
|
|
+ rtl8169ctlrhead = ctlr;
|
|
|
+ rtl8169ctlrtail = ctlr;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+rtl8169pnp(Ether* edev)
|
|
|
+{
|
|
|
+ u32int r;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ uchar ea[Eaddrlen];
|
|
|
+
|
|
|
+ if(rtl8169ctlrhead == nil)
|
|
|
+ rtl8169pci();
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Any adapter matches if no edev->port is supplied,
|
|
|
+ * otherwise the ports must match.
|
|
|
+ */
|
|
|
+ for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
|
+ if(ctlr->active)
|
|
|
+ continue;
|
|
|
+ if(edev->port == 0 || edev->port == ctlr->port){
|
|
|
+ ctlr->active = 1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ if(ctlr == nil)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ edev->ctlr = ctlr;
|
|
|
+ edev->port = ctlr->port;
|
|
|
+ edev->irq = ctlr->pcidev->intl;
|
|
|
+ edev->tbdf = ctlr->pcidev->tbdf;
|
|
|
+ edev->mbps = 100;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Check if the adapter's station address is to be overridden.
|
|
|
+ * If not, read it from the device and set in edev->ea.
|
|
|
+ */
|
|
|
+ memset(ea, 0, Eaddrlen);
|
|
|
+ if(memcmp(ea, edev->ea, Eaddrlen) == 0){
|
|
|
+ r = csr32r(ctlr, Idr0);
|
|
|
+ edev->ea[0] = r;
|
|
|
+ edev->ea[1] = r>>8;
|
|
|
+ edev->ea[2] = r>>16;
|
|
|
+ edev->ea[3] = r>>24;
|
|
|
+ r = csr32r(ctlr, Idr0+4);
|
|
|
+ edev->ea[4] = r;
|
|
|
+ edev->ea[5] = r>>8;
|
|
|
+ }
|
|
|
+
|
|
|
+ edev->attach = rtl8169attach;
|
|
|
+ edev->transmit = rtl8169transmit;
|
|
|
+ edev->interrupt = rtl8169interrupt;
|
|
|
+#ifndef FS
|
|
|
+ edev->ifstat = rtl8169ifstat;
|
|
|
+
|
|
|
+ edev->arg = edev;
|
|
|
+ edev->promiscuous = rtl8169promiscuous;
|
|
|
+#endif
|
|
|
+ rtl8169link(edev);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void
|
|
|
+ether8169link(void)
|
|
|
+{
|
|
|
+ addethercard("rtl8169", rtl8169pnp);
|
|
|
+}
|