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@@ -95,12 +95,12 @@ _endofheader:
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/*
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* Make the basic page tables for CPU0 to map 0-4MiB physical
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* to KZERO, and include an identity map for the switch from protected
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- * to paging mode. There's an assumption here that the creation and later
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+ * to paging mode. There`s an assumption here that the creation and later
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* removal of the identity map will not interfere with the KZERO mappings;
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* the conditions for clearing the identity map are
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* clear PML4 entry when (KZER0 & 0x0000ff8000000000) != 0;
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* clear PDP entry when (KZER0 & 0x0000007fc0000000) != 0;
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- * don't clear PD entry when (KZER0 & 0x000000003fe00000) == 0;
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+ * don`t clear PD entry when (KZER0 & 0x000000003fe00000) == 0;
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* the code below assumes these conditions are met.
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*
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* Assume a recent processor with Page Size Extensions
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@@ -172,7 +172,7 @@ _warp64:
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* set Long Mode Enable in the Extended Feature Enable MSR;
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* set Paging Enable in CR0;
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* make an inter-segment jump to the Long Mode code.
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- * It's all in 32-bit mode until the jump is made.
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+ * It`s all in 32-bit mode until the jump is made.
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*/
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lme:
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movl %cr4, %eax
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