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riscv: spike utilities. In principle, we can print hello.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Ronald G. Minnich 4 years ago
parent
commit
bb54e623d4

+ 2 - 47
sys/src/9/riscv/atomic.h

@@ -25,26 +25,11 @@
  * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  */
 
-#ifndef _RISCV_ATOMIC_H
-#define _RISCV_ATOMIC_H
-
-#include <arch/encoding.h>
-
-#define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
-#define enable_irqrestore(flags) set_csr(sstatus, (flags) & SSTATUS_IE)
-
-typedef struct { int lock; } spinlock_t;
-#define SPINLOCK_INIT {0}
-
 #define mb() __sync_synchronize()
 #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
-#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
+#define atomic_read(ptr) (*(volatile __typeof__(*(ptr)) *)(ptr))
 
-#ifdef PK_ENABLE_ATOMICS
-# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
-# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
-# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
-#else
+#if 0
 # define atomic_add(ptr, inc) ({ \
   long flags = disable_irqsave(); \
   typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
@@ -65,33 +50,3 @@ typedef struct { int lock; } spinlock_t;
   res; })
 #endif
 
-static inline void spinlock_lock(spinlock_t* lock)
-{
-  do
-  {
-    while (atomic_read(&lock->lock))
-      ;
-  } while (atomic_swap(&lock->lock, -1));
-  mb();
-}
-
-static inline void spinlock_unlock(spinlock_t* lock)
-{
-  mb();
-  atomic_set(&lock->lock,0);
-}
-
-static inline long spinlock_lock_irqsave(spinlock_t* lock)
-{
-  long flags = disable_irqsave();
-  spinlock_lock(lock);
-  return flags;
-}
-
-static inline void spinlock_unlock_irqrestore(spinlock_t* lock, long flags)
-{
-  spinlock_unlock(lock);
-  enable_irqrestore(flags);
-}
-
-#endif

+ 7 - 28
sys/src/9/riscv/encoding.h

@@ -127,55 +127,37 @@
    (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
              ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 
-#ifdef __riscv
-
-#ifdef __riscv64
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
 # define RISCV_PGLEVEL_BITS 9
-#else
-# define MSTATUS_SD MSTATUS32_SD
-# define SSTATUS_SD SSTATUS32_SD
-# define RISCV_PGLEVEL_BITS 10
-#endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
 
 #ifndef __ASSEMBLER__
 
-#ifdef __GNUC__
-
-#if __GNUC__ < 5
-// stubbed out until we're safely on gcc-5.1+ with the new ABI
-#define read_csr(reg) ({ 0; })
-#define write_csr(reg, val)
-#define swap_csr(reg, val) ({ val; })
-#define set_csr(reg, bit) ({ bit; })
-#define clear_csr(reg, bit) ({ bit; })
-#else
 #define read_csr(reg) ({ unsigned long __tmp; \
-  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __asm__ __volatile__ ("csrr %0, " #reg : "=r"(__tmp)); \
   __tmp; })
 
 #define write_csr(reg, val) \
-  asm volatile ("csrw " #reg ", %0" :: "r"(val))
+  __asm__ __volatile__ ("csrw " #reg ", %0" :: "r"(val))
 
 #define swap_csr(reg, val) ({ long __tmp; \
-  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  __asm__ __volatile__ ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
   __tmp; })
 
 #define set_csr(reg, bit) ({ unsigned long __tmp; \
   if (__builtin_constant_p(bit) && (bit) < 32) \
-    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+    __asm__ __volatile__ ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
   else \
-    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+    __asm__ __volatile__ ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
   __tmp; })
 
 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
   if (__builtin_constant_p(bit) && (bit) < 32) \
-    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+    __asm__ __volatile__ ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
   else \
-    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+    __asm__ __volatile__ ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
   __tmp; })
 #endif
 
@@ -183,13 +165,10 @@
 #define rdcycle() read_csr(cycle)
 #define rdinstret() read_csr(instret)
 
-#endif
 
-#endif
 
 #endif
 
-#endif
 /* Automatically generated by parse-opcodes */
 #ifndef RISCV_ENCODING_H
 #define RISCV_ENCODING_H

+ 4 - 1
sys/src/9/riscv/main.c

@@ -19,5 +19,8 @@
 void
 main(uint32_t mbmagic, uint32_t mbaddress)
 {
-	while (1);
+	void testPrint(void);
+	
+	while (1)
+		testPrint();
 }

+ 7 - 1
sys/src/9/riscv/spike_util.c

@@ -31,6 +31,8 @@
 #include "dat.h"
 #include "fns.h"
 
+#include "encoding.h"
+#include "atomic.h"
 #include "spike_util.h"
 
 uintptr_t translate_address(uintptr_t vAddr) {
@@ -55,6 +57,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p)
 	return -1;
 }
 
+#if 0
 uintptr_t mcall_send_ipi(uintptr_t recipient)
 {
 	//if (recipient >= num_harts)
@@ -79,6 +82,8 @@ uintptr_t mcall_clear_ipi(void)
 	return atomic_swap(&HLS()->ipi_pending, 0);
 }
 
+#endif
+
 uintptr_t mcall_shutdown(void)
 {
 	while (1) write_csr(mtohost, 1);
@@ -93,6 +98,7 @@ uintptr_t mcall_set_timer(unsigned long long when)
 	return 0;
 }
 
+#if 0
 uintptr_t mcall_dev_req(sbi_device_message *m)
 {
 	if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL;
@@ -105,7 +111,7 @@ uintptr_t mcall_dev_req(sbi_device_message *m)
 
 	return 0;
 }
-
+#endif
 uintptr_t mcall_dev_resp(void)
 {
 	htif_interrupt(0, 0);

+ 1 - 1
sys/src/9/riscv/spike_util.h

@@ -51,7 +51,7 @@ typedef struct {
 } hls_t;
 
 #define MACHINE_STACK_TOP() ({ \
-  register uintptr_t sp asm ("sp"); \
+  register uintptr_t sp __asm__ ("sp"); \
   (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
 
 // hart-local storage, at top of stack

+ 5 - 0
sys/src/libc/riscv/atomic.S

@@ -16,3 +16,8 @@ _tas:
 	amoswap.w.aq a0, a1, 0(a0)
 	ret
 
+.globl aswap				/* int aswap(int *, int); */
+aswap:
+	amoswap.w.aq a0, a1, 0(a0)
+	ret
+