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@@ -127,55 +127,37 @@
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(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
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-#ifdef __riscv
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-
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-#ifdef __riscv64
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define RISCV_PGLEVEL_BITS 9
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-#else
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-# define MSTATUS_SD MSTATUS32_SD
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-# define SSTATUS_SD SSTATUS32_SD
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-# define RISCV_PGLEVEL_BITS 10
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-#endif
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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#ifndef __ASSEMBLER__
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-#ifdef __GNUC__
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-
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-#if __GNUC__ < 5
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-// stubbed out until we're safely on gcc-5.1+ with the new ABI
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-#define read_csr(reg) ({ 0; })
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-#define write_csr(reg, val)
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-#define swap_csr(reg, val) ({ val; })
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-#define set_csr(reg, bit) ({ bit; })
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-#define clear_csr(reg, bit) ({ bit; })
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-#else
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#define read_csr(reg) ({ unsigned long __tmp; \
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- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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+ __asm__ __volatile__ ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define write_csr(reg, val) \
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- asm volatile ("csrw " #reg ", %0" :: "r"(val))
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+ __asm__ __volatile__ ("csrw " #reg ", %0" :: "r"(val))
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#define swap_csr(reg, val) ({ long __tmp; \
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- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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+ __asm__ __volatile__ ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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__tmp; })
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#define set_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (bit) < 32) \
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- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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+ __asm__ __volatile__ ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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+ __asm__ __volatile__ ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define clear_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (bit) < 32) \
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- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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+ __asm__ __volatile__ ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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+ __asm__ __volatile__ ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#endif
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@@ -183,13 +165,10 @@
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#define rdcycle() read_csr(cycle)
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#define rdinstret() read_csr(instret)
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-#endif
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-#endif
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#endif
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-#endif
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/* Automatically generated by parse-opcodes */
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#ifndef RISCV_ENCODING_H
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#define RISCV_ENCODING_H
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