Plan 9 from Bell Labs 2010-04-17

cfg/pxe/example-kw

@@ -0,0 +1,8 @@
+# sheevaplug configuration
+nvram=/boot/nvram
+nvroff=0
+nvrlen=512
+nobootprompt=tcp
+
+# aoeif=ether0
+# aoedev=e!#æ/aoe/1.0

sys/src/9/kw/archkw.c

@@ -19,14 +19,8 @@
 #define SDRAMDREG	((SDramdReg*)AddrSDramd)
 
 enum {
-	/*
-	 * Things might run faster if we could make L2writeback = 1 work,
-	 * but currently that causes the system to wedge shortly after we
-	 * start running user procs, even if the Buffered bit is never set
-	 * in a PTE(!) or if all of memory is made uncacheable by the l2
-	 * cache(!).  We may be dealing with a broken l2 cache.
-	 */
 	L2writeback = 0,
+	Debug = 0,
 };
 
 typedef struct GpioReg GpioReg;
@@ -117,8 +111,6 @@ enum {
 	Winenable	= 1<<0,
 };
 
-void l2cacheinv(void);
-
 /*
  * u-boot leaves us with this address map:
  *
@@ -140,6 +132,10 @@ praddrwin(Addrwin *win, int i)
 {
 	ulong ctl, targ, attr, size64k;
 
+	if (!Debug) {
+		USED(win, i);
+		return;
+	}
 	ctl = win->ctl;
 	targ = WINTARG(ctl);
 	attr = WINATTR(ctl);
@@ -330,6 +326,7 @@ l2cacheon(void)
 	L2uncache *l2p;
 
 	cacheuwbinv();
+	l2cacheuwbinv();
 	l1cachesoff();			/* turns off L2 as a side effect */
 
 	cpwrsc(CpDef, CpCLD, 0, 0, 0);  /* GL-CPU-100: set D cache lockdown reg. */
@@ -338,10 +335,6 @@ l2cacheon(void)
 	cpu = CPUCSREG;
 	cfg = cpu->cpucfg | L2exists | L2ecc | Cfgiprefetch | Cfgdprefetch;
 
-	/*
-	 * writeback requires extra care; i thought we were now taking that
-	 * extra care, but trying to allow L2 write-back wedges the system.
-	 */
 	if (L2writeback)
 		cfg &= ~L2writethru;	/* see PTE Cached & Buffered bits */
 	else
@@ -355,7 +348,7 @@ l2cacheon(void)
 //	l2cachecfgoff();
 
 	cachedinv();
-	l2cacheinv();
+	l2cacheuinv();
 
 	/* disable l2 caching of i/o registers */
 	l2p = (L2uncache *)Addrl2cache;
@@ -363,12 +356,11 @@ l2cacheon(void)
 	/* l2: don't cache upper half of address space */
 	l2p->win[0].base = 0x80000000 | L2enable;	/* 64K multiple */
 	l2p->win[0].size = (32*1024-1) << 16;		/* 64K multiples */
-
 	coherence();
 
 	l2cachecfgon();
 	l1cacheson();			/* turns L2 on as a side effect */
-	print("l2 cache: write-%s, low memory only\n",
+	print("l2 cache: 256K or 512K: 4 ways, 32-byte lines, write-%s, low memory only\n",
 		cpu->l2cfg & L2writethru? "through": "back");
 }
 

sys/src/9/kw/clock.c

@@ -16,17 +16,17 @@
 
 enum {
 	Tcycles		= CLOCKFREQ / HZ,	/* cycles per clock tick */
-	Dogperiod	= 5 * CLOCKFREQ,	// TODO tune
+	Dogperiod	= 5 * CLOCKFREQ, /* at most 21 s.; must fit in ulong */
 	MaxPeriod	= Tcycles,
 	MinPeriod	= MaxPeriod / 100,
 
 	/* timer ctl bits */
 	Tmr0enable	= 1<<0,
-	Tmr0periodic	= 1<<1,	/* at 0 count, load timer0 from reload0 */
+	Tmr0reload	= 1<<1,	/* at 0 count, load timer0 from reload0 */
 	Tmr1enable	= 1<<2,
-	Tmr1periodic	= 1<<3,	/* at 0 count, load timer1 from reload1 */
+	Tmr1reload	= 1<<3,	/* at 0 count, load timer1 from reload1 */
 	TmrWDenable	= 1<<4,
-	TmrWDperiodic	= 1<<5,
+	TmrWDreload	= 1<<5,
 };
 
 typedef struct TimerReg TimerReg;
@@ -42,17 +42,24 @@ struct TimerReg
 	ulong	timerwd;
 };
 
-static int ticks; /* for sanity checking; m->ticks doesn't always get called */
+static int ticks; /* for sanity checking; m->ticks doesn't always get updated */
 
 static void
 clockintr(Ureg *ureg, void *arg)
 {
 	TimerReg *tmr = arg;
+	static int nesting;
 
 	tmr->timerwd = Dogperiod;		/* reassure the watchdog */
 	ticks++;
 	coherence();
-	timerintr(ureg, 0);
+
+	if (nesting == 0) {	/* if the clock interrupted itself, bail out */
+		++nesting;
+		timerintr(ureg, 0);
+		--nesting;
+	}
+
 	intrclear(Irqbridge, IRQcputimer0);
 }
 
@@ -76,7 +83,7 @@ clockinit(void)
 	 * verify sanity of timer0
 	 */
 
-	intrenable(Irqbridge, IRQcputimer0, clockintr, tmr, "clock");
+	intrenable(Irqbridge, IRQcputimer0, clockintr, tmr, "clock0");
 	s = spllo();			/* risky */
 	/* take any deferred clock (& other) interrupts here */
 	splx(s);
@@ -113,7 +120,8 @@ clockinit(void)
 	tmr->reload1 = tmr->timer1 = ~0;	/* cycle clock */
 	tmr->timerwd = Dogperiod;		/* watch dog timer */
 	coherence();
-	tmr->ctl = Tmr0enable | Tmr1enable | Tmr1periodic | TmrWDenable;
+	tmr->ctl = Tmr0enable | Tmr0reload | Tmr1enable | Tmr1reload |
+		TmrWDenable;
 	CPUCSREG->rstout |= RstoutWatchdog;
 	coherence();
 }

sys/src/9/kw/etherkw.c

@@ -552,10 +552,12 @@ rxreplenish(Ctlr *ctlr)
 		r->countsize = Bufsize(Rxblklen);
 		r->buf = PADDR(b->rp);
 		cachedwbse(r, sizeof *r);
+		l2cacheuwbse(r, sizeof *r);
 
 		/* and fire */
 		r->cs = RCSdmaown | RCSenableintr;
 		cachedwbse(&r->cs, BY2SE);
+		l2cacheuwbse(&r->cs, BY2SE);
 
 		ctlr->rxtail = NEXT(ctlr->rxtail, Nrx);
 	}
@@ -600,6 +602,7 @@ receive(Ether *ether)
 		r = &ctlr->rx[ctlr->rxhead];
 		assert(((uintptr)r & (Descralign - 1)) == 0);
 		cachedinvse(r, sizeof *r);
+		l2cacheuinvse(r, sizeof *r);
 		if(r->cs & RCSdmaown)
 			break;
 
@@ -624,6 +627,7 @@ receive(Ether *ether)
 		assert(n >= 2 && n < 2048);
 
 		cachedinvse(b->rp, n);
+		l2cacheuinvse(b->rp, n);
 		b->wp = b->rp + n;
 		/*
 		 * skip hardware padding to align ipv4 address in memory
@@ -646,6 +650,7 @@ txreplenish(Ether *ether)			/* free transmitted packets */
 	ctlr = ether->ctlr;
 	while(ctlr->txtail != ctlr->txhead) {
 		cachedinvse(&ctlr->tx[ctlr->txtail].cs, BY2SE);
+		l2cacheuinvse(&ctlr->tx[ctlr->txtail].cs, BY2SE);
 		if(ctlr->tx[ctlr->txtail].cs & TCSdmaown)
 			break;
 		if(ctlr->txb[ctlr->txtail] == nil)
@@ -681,6 +686,7 @@ transmit(Ether *ether)
 		t = &ctlr->tx[ctlr->txhead];
 		assert(((uintptr)t & (Descralign - 1)) == 0);
 		cachedinvse(t, sizeof *t);
+		l2cacheuinvse(t, sizeof *t);
 		if(t->cs & TCSdmaown) {		/* free descriptor? */
 			ctlr->txringfull++;
 			break;
@@ -700,11 +706,13 @@ transmit(Ether *ether)
 		t->buf = PADDR(b->rp);
 		t->countchk = len << 16;
 		cachedwbse(t, sizeof *t);
+		l2cacheuwbse(t, sizeof *t);
 
 		/* and fire */
 		t->cs = TCSpadding | TCSfirst | TCSlast | TCSdmaown |
 			TCSenableintr;
 		cachedwbse(&t->cs, BY2SE);
+		l2cacheuwbse(&t->cs, BY2SE);
 
 		kick++;
 		ctlr->txhead = NEXT(ctlr->txhead, Ntx);
@@ -826,12 +834,12 @@ interrupt(Ureg*, void *arg)
 		if (irq & Irxerrq(Qno)) {
 			ether->buffs++;		/* approx. error */
 			/* null descriptor pointer or descriptor owned by cpu */
-			panic("etherkw: rx err on queue 0");
+			iprint("etherkw: rx err on queue 0 - input ring full\n");
 		}
 		if (irq & Irxerr) {
 			ether->buffs++;		/* approx. error */
 			/* null descriptor pointer or descriptor owned by cpu */
-			panic("etherkw: rx err");
+			iprint("etherkw: rx err - input ring full\n");
 		}
 		if(irq & (Irxerr | Irxerrq(Qno)))
 			handled++;
@@ -1258,6 +1266,7 @@ ctlrinit(Ether *ether)
 	}
 	ctlr->rxtail = ctlr->rxhead = 0;
 	cachedwb();
+	l2cacheuwb();
 	rxreplenish(ctlr);
 
 	ctlr->tx = xspanalloc(Ntx * sizeof(Tx), Descralign, 0);
@@ -1273,6 +1282,7 @@ ctlrinit(Ether *ether)
 	}
 	ctlr->txtail = ctlr->txhead = 0;
 	cachedwb();
+	l2cacheuwb();
 
 	/* clear stats by reading them into fake ctlr */
 	getmibstats(&fakectlr);

sys/src/9/kw/fns.h

@@ -55,6 +55,12 @@ extern void l1cacheson(void);
 extern void l2cachecfgoff(void);
 extern void l2cachecfgon(void);
 extern void l2cacheon(void);
+extern void l2cacheuinv(void);
+extern void l2cacheuinvse(void*, int);
+extern void l2cacheuwb(void);
+extern void l2cacheuwbinv(void);
+extern void l2cacheuwbinvse(void*, int);
+extern void l2cacheuwbse(void*, int);
 extern void lastresortprint(char *buf, long bp);
 extern int log2(ulong);
 extern void mmuinvalidate(void);		/* 'mmu' or 'tlb'? */

sys/src/9/kw/l.s

@@ -6,8 +6,6 @@
  */
 #include "arm.s"
 
-#undef L1SETWAY
-
 /*
  * MCR and MRC are counter-intuitively named.
  *	MCR	coproc, opcode1, Rd, CRn, CRm[, opcode2]	# arm -> coproc
@@ -31,6 +29,7 @@ _main:
 	/* SVC mode, interrupts disabled */
 	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
 	MOVW	R1, CPSR
+	BARRIERS
 
 	/*
 	 * disable the MMU & caches,
@@ -206,6 +205,7 @@ TEXT _reset(SB), 1, $-4
 	/* turn the caches off */
 	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R0
 	MOVW	R0, CPSR
+	BARRIERS
 	BL	cacheuwbinv(SB)
 	MRC	CpSC, 0, R0, C(CpCONTROL), C(0)
 	BIC	$(CpCwb|CpCicache|CpCdcache|CpCalign), R0
@@ -283,6 +283,10 @@ _busy:
 	BARRIERS
 	RET
 
+/*
+ * l1 caches
+ */
+
 TEXT l1cacheson(SB), 1, $-4
 	MOVW	CPSR, R5
 	ORR	$(PsrDirq|PsrDfiq), R5, R4
@@ -318,22 +322,17 @@ TEXT l1cachesoff(SB), 1, $-4
 	MOVM.IA.W (SP), [R14]			/* restore lr */
 	RET
 
-#define MAXFLUSH 32000
+/*
+ * cache* functions affect only the L1 caches, which are VIVT.
+ */
 
-TEXT cachedwb(SB), 1, $-4			/* D writeback */
-	/* flush l2 before masking interrupts */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
-	BARRIERS
+#define MAXFLUSH 320000
 
+TEXT cachedwb(SB), 1, $-4			/* D writeback */
 	MOVW	CPSR, R3			/* splhi */
 	ORR	$(PsrDirq), R3, R1
 	MOVW	R1, CPSR
 	BARRIERS
-	MOVM.DB.W [R14], (SP)			/* save lr on stack */
-
-#ifdef L1SETWAY
-	BL	cache1dwb(SB)
-#else
 	/* keep writing back dirty cache lines until no more exist */
 	MOVW	$MAXFLUSH, R1
 _dwb:
@@ -341,15 +340,9 @@ _dwb:
 	BEQ	stuck
 	MRC	CpSC, 0, PC, C(CpCACHE), C(CpCACHEwb), CpCACHEtest
 	BNE	_dwb
-#endif
-
 	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
 	BARRIERS
 dwbret:
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
-	BARRIERS
-
-	MOVM.IA.W (SP), [R14]			/* restore lr */
 	MOVW	R3, CPSR			/* splx */
 	BARRIERS
 	RET
@@ -373,56 +366,33 @@ TEXT cachedwbse(SB), 1, $-4			/* D writeback SE */
 	ADD	R2, R1
 	BIC	$(CACHELINESZ-1), R2
 _dwbse:
-	/* l1 first */
 	MCR	CpSC, 0, R2, C(CpCACHE), C(CpCACHEwb), CpCACHEse
-	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
-	BARRIERS
-
-	/* l2 second */
-	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
-	BARRIERS
-
 	ADD	$CACHELINESZ, R2
 	CMP.S	R2, R1
 	BGT	_dwbse
+	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
+	BARRIERS
 
 	MOVW	R3, CPSR			/* splx */
 	BARRIERS
 	RET
 
 TEXT cachedwbinv(SB), 1, $-4			/* D writeback+invalidate */
-	/* flush l2 before masking interrupts */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
-	BARRIERS
-
 	MOVW	CPSR, R3			/* splhi */
 	ORR	$(PsrDirq), R3, R1
 	MOVW	R1, CPSR
 	BARRIERS
-	MOVM.DB.W [R14], (SP)			/* save lr on stack */
 
-#ifdef L1SETWAY
-	BL	cache1dwbinv(SB)
-#else
 	/* keep writing back dirty cache lines until no more exist */
 	MOVW	$MAXFLUSH, R1
 _dwbinv:
 	SUB.S	$1, R1
 	BEQ	stuck
-	/* the kw inferno guys think this instruction doesn't work */
 	MRC	CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
 	BNE	_dwbinv
-#endif
 	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
 	BARRIERS
 
-	/* wb+inv l2 cache now */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
-	BARRIERS
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
-	BARRIERS
-
-	MOVM.IA.W (SP), [R14]			/* restore lr */
 	MOVW	R3, CPSR			/* splx */
 	BARRIERS
 	RET
@@ -443,18 +413,11 @@ TEXT cachedwbinvse(SB), 1, $-4			/* D writeback+invalidate SE */
 	BIC	$(CACHELINESZ-1), R2
 _dwbinvse:
 	MCR	CpSC, 0, R2, C(CpCACHE), C(CpCACHEwbi), CpCACHEse
-	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
-	BARRIERS
-
-	/* wb+inv l2 cache now */
-	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
-	BARRIERS
-	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
-	BARRIERS
-
 	ADD	$CACHELINESZ, R2
 	CMP.S	R2, R1
 	BGT	_dwbinvse
+	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
+	BARRIERS
 
 	MOVW	R3, CPSR			/* splx */
 	BARRIERS
@@ -476,45 +439,29 @@ TEXT cachedinvse(SB), 1, $-4			/* D invalidate SE */
 	BIC	$(CACHELINESZ-1), R2
 _dinvse:
 	MCR	CpSC, 0, R2, C(CpCACHE), C(CpCACHEinvd), CpCACHEse
-	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
-	BARRIERS
-
-	/* inv l2 cache now */
-	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
-	BARRIERS
-
 	ADD	$CACHELINESZ, R2
 	CMP.S	R2, R1
 	BGT	_dinvse
+	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
+	BARRIERS
 
 	MOVW	R3, CPSR			/* splx */
 	BARRIERS
 	RET
 
 TEXT cacheuwbinv(SB), 1, $-4			/* D+I writeback+invalidate */
-	/* flush l2 before masking interrupts */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
-	BARRIERS
-
 	MOVW	CPSR, R3			/* splhi */
 	ORR	$(PsrDirq), R3, R1
 	MOVW	R1, CPSR
 	BARRIERS
-	MOVM.DB.W [R14], (SP)			/* save lr on stack */
 
-#ifdef L1SETWAY
-	BL	cache1dwbinv(SB)
-#else
 	/* keep writing back dirty cache lines until no more exist */
 	MOVW	$MAXFLUSH, R1
 _uwbinv:					/* D writeback+invalidate */
 	SUB.S	$1, R1
 	BEQ	stuck
-	/* the kw inferno guys think this instruction doesn't work */
 	MRC	CpSC, 0, PC, C(CpCACHE), C(CpCACHEwbi), CpCACHEtest
 	BNE	_uwbinv
-#endif
-
 	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
 	BARRIERS
 
@@ -523,61 +470,29 @@ _uwbinv:					/* D writeback+invalidate */
 	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
 	BARRIERS
 
-	/* wb+inv l2 cache now */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
-	BARRIERS
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
-	BARRIERS
-
-	MOVM.IA.W (SP), [R14]			/* restore lr */
 	MOVW	R3, CPSR			/* splx */
 	BARRIERS
 	RET
 
 TEXT cacheiinv(SB), 1, $-4			/* I invalidate */
-	MOVW	CPSR, R3			/* splhi */
-	ORR	$(PsrDirq), R3, R1
-	MOVW	R1, CPSR
 	BARRIERS
-
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
 	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
 	BARRIERS
-
-	/* inv l2 cache now */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
-	BARRIERS
-
-	MOVW	R3, CPSR			/* splx */
-	BARRIERS
 	RET
 
 TEXT cachedinv(SB), 1, $-4			/* D invalidate */
-	MOVW	CPSR, R3			/* splhi */
-	ORR	$(PsrDirq), R3, R1
-	MOVW	R1, CPSR
 _dinv:
 	BARRIERS
-	MOVM.DB.W [R14], (SP)			/* save lr on stack */
-
-#ifdef L1SETWAY
-	BL	cache1dinv(SB)
-#else
-	MOVW	$0, R0
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEall
-#endif
 	/* drain L1 write buffer, also drains L2 eviction buffer on sheeva */
 	BARRIERS
-
-	/* inv l2 cache now */
-	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
-	BARRIERS
-
-	MOVM.IA.W (SP), [R14]			/* restore lr */
-	MOVW	R3, CPSR			/* splx */
-	BARRIERS
 	RET
 
+/*
+ * l2 cache
+ */
+
 /* enable l2 cache in config coproc. reg.  do this while l1 caches are off. */
 TEXT l2cachecfgon(SB), 1, $-4
 	BARRIERS
@@ -602,13 +517,104 @@ TEXT l2cachecfgoff(SB), 1, $-4
 	BARRIERS
 	RET
 
-/* invalidate l2 cache */
-TEXT l2cacheinv(SB), 1, $-4
+TEXT l2cacheuwb(SB), 1, $-4			/* L2 unified writeback */
+	BARRIERS
+	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
+	BARRIERS
+	RET
+
+TEXT l2cacheuwbse(SB), 1, $-4			/* L2 unified writeback SE */
+	MOVW	R0, R2				/* first arg: address */
+
+	MOVW	CPSR, R3			/* splhi */
+	ORR	$(PsrDirq), R3, R1
+	MOVW	R1, CPSR
+	BARRIERS
+
+	MOVW	4(FP), R1			/* second arg: size */
+
+	ADD	R2, R1
+	BIC	$(CACHELINESZ-1), R2
+_l2wbse:
+	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
+	ADD	$CACHELINESZ, R2
+	CMP.S	R2, R1
+	BGT	_l2wbse
+	BARRIERS
+
+	MOVW	R3, CPSR			/* splx */
+	BARRIERS
+	RET
+
+TEXT l2cacheuwbinv(SB), 1, $-4		/* L2 unified writeback+invalidate */
+	MOVW	CPSR, R3			/* splhi */
+	ORR	$(PsrDirq), R3, R1
+	MOVW	R1, CPSR
+	BARRIERS
+
+	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2flush), CpTCl2all
+	BARRIERS
+	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
+	BARRIERS
+
+	MOVW	R3, CPSR			/* splx */
+	BARRIERS
+	RET
+
+TEXT l2cacheuwbinvse(SB), 1, $-4	/* L2 unified writeback+invalidate SE */
+	MOVW	R0, R2				/* first arg: address */
+
+	MOVW	CPSR, R3			/* splhi */
+	ORR	$(PsrDirq), R3, R1
+	MOVW	R1, CPSR
+	BARRIERS
+
+	MOVW	4(FP), R1			/* second arg: size */
+
+	ADD	R2, R1
+	BIC	$(CACHELINESZ-1), R2
+_l2wbinvse:
+	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2flush), CpTCl2seva
+	BARRIERS
+	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
+	ADD	$CACHELINESZ, R2
+	CMP.S	R2, R1
+	BGT	_l2wbinvse
+	BARRIERS
+
+	MOVW	R3, CPSR			/* splx */
+	BARRIERS
+	RET
+
+TEXT l2cacheuinv(SB), 1, $-4			/* L2 unified invalidate */
 	BARRIERS
 	MCR	CpSC, CpL2, R0, C(CpTESTCFG), C(CpTCl2inv), CpTCl2all
 	BARRIERS
 	RET
 
+TEXT l2cacheuinvse(SB), 1, $-4			/* L2 unified invalidate SE */
+	MOVW	R0, R2				/* first arg: address */
+
+	MOVW	CPSR, R3			/* splhi */
+	ORR	$(PsrDirq), R3, R1
+	MOVW	R1, CPSR
+	BARRIERS
+
+	MOVW	4(FP), R1			/* second arg: size */
+
+	ADD	R2, R1
+	BIC	$(CACHELINESZ-1), R2
+_l2invse:
+	MCR	CpSC, CpL2, R2, C(CpTESTCFG), C(CpTCl2inv), CpTCl2seva
+	ADD	$CACHELINESZ, R2
+	CMP.S	R2, R1
+	BGT	_l2invse
+	BARRIERS
+
+	MOVW	R3, CPSR			/* splx */
+	BARRIERS
+	RET
+
 /*
  *  enable mmu, i and d caches, and high vector
  */
@@ -689,15 +695,19 @@ TEXT splhi(SB), 1, $-4
 	MOVW	$(MACHADDR+4), R2		/* save caller pc in Mach */
 	MOVW	R14, 0(R2)
 
-	MOVW	CPSR, R0			/* turn off interrupts */
-	ORR	$(PsrDirq), R0, R1
+	MOVW	CPSR, R3			/* turn off interrupts */
+	ORR	$(PsrDirq), R3, R1
 	MOVW	R1, CPSR
+	BARRIERS
+	MOVW	R3, R0
 	RET
 
 TEXT spllo(SB), 1, $-4
-	MOVW	CPSR, R0
-	BIC	$(PsrDirq), R0, R1
+	MOVW	CPSR, R3
+	BIC	$(PsrDirq), R3, R1
 	MOVW	R1, CPSR
+	BARRIERS
+	MOVW	R3, R0
 	RET
 
 TEXT splx(SB), 1, $-4
@@ -705,14 +715,18 @@ TEXT splx(SB), 1, $-4
 	MOVW	R14, 0(R2)
 
 	MOVW	R0, R1				/* reset interrupt level */
-	MOVW	CPSR, R0
+	MOVW	CPSR, R3
 	MOVW	R1, CPSR
+	BARRIERS
+	MOVW	R3, R0
 	RET
 
 TEXT splxpc(SB), 1, $-4				/* for iunlock */
 	MOVW	R0, R1
-	MOVW	CPSR, R0
+	MOVW	CPSR, R3
 	MOVW	R1, CPSR
+	BARRIERS
+	MOVW	R3, R0
 	RET
 
 TEXT spldone(SB), 1, $0
@@ -725,15 +739,19 @@ TEXT islo(SB), 1, $-4
 	RET
 
 TEXT splfhi(SB), $-4
-	MOVW	CPSR, R0
-	ORR	$(PsrDfiq|PsrDirq), R0, R1
+	MOVW	CPSR, R3
+	ORR	$(PsrDfiq|PsrDirq), R3, R1
 	MOVW	R1, CPSR
+	BARRIERS
+	MOVW	R3, R0
 	RET
 
 TEXT splflo(SB), $-4
-	MOVW	CPSR, R0
-	BIC	$(PsrDfiq), R0, R1
+	MOVW	CPSR, R3
+	BIC	$(PsrDfiq), R3, R1
 	MOVW	R1, CPSR
+	BARRIERS
+	MOVW	R3, R0
 	RET
 
 TEXT tas32(SB), 1, $-4
@@ -753,12 +771,14 @@ _tasout:
 TEXT setlabel(SB), 1, $-4
 	MOVW	R13, 0(R0)		/* sp */
 	MOVW	R14, 4(R0)		/* pc */
+	BARRIERS
 	MOVW	$0, R0
 	RET
 
 TEXT gotolabel(SB), 1, $-4
 	MOVW	0(R0), R13		/* sp */
 	MOVW	4(R0), R14		/* pc */
+	BARRIERS
 	MOVW	$1, R0
 	RET
 
@@ -770,17 +790,16 @@ TEXT _idlehands(SB), 1, $-4
 	MOVW	CPSR, R3
 	ORR	$(PsrDirq|PsrDfiq), R3, R1	/* splhi */
 	MOVW	R1, CPSR
-
 	BARRIERS
+
 	MOVW	$0, R0				/* wait for interrupt */
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
 	BARRIERS
 
 	MOVW	R3, CPSR			/* splx */
+	BARRIERS
 	RET
 
 TEXT barriers(SB), 1, $-4
 	BARRIERS
 	RET
-
-#include "cache.v5.s"

sys/src/9/kw/lexception.s

@@ -1,8 +1,7 @@
 /*
  * arm exception handlers
  */
-#include "mem.h"
-#include "arm.h"
+#include "arm.s"
 
 #undef B					/* B is for 'botch' */
 
@@ -101,6 +100,14 @@ _vswitch:
 	ORR	$(PsrDirq|PsrDfiq|PsrMsvc), R14
 	MOVW	R14, CPSR		/* switch! */
 
+	/*
+	 * execute barrier instructions (without changing R0) to force new CPSR
+	 * to take effect.
+	 */
+	MOVW	$0, R4
+	MCR	CpSC, 0, R4, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
+	MCR	CpSC, 0, R4, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait
+
 	AND.S	$0xf, R1, R4		/* interrupted code kernel or user? */
 	BEQ	_userexcep
 
@@ -121,7 +128,6 @@ _vswitch:
 	MOVW	$setR12(SB), R12	/* Make sure we've got the kernel's SB loaded */
 
 	MOVW	R13, R0			/* first arg is pointer to ureg */
-//	BL	printr0(SB)
 	SUB	$(4*2), R13		/* space for argument+link (for debugger) */
 	MOVW	$0xdeaddead, R11	/* marker */
 
@@ -178,9 +184,13 @@ TEXT setr13(SB), 1, $-4
 	BIC	$PsrMask, R2, R3
 	ORR	R0, R3
 	MOVW	R3, CPSR
+	BARRIERS
 
-	MOVW	R13, R0
+	MOVW	R13, R3
 	MOVW	R1, R13
 
 	MOVW	R2, CPSR
+	BARRIERS
+
+	MOVW	R3, R0
 	RET

sys/src/9/kw/mkfile

@@ -110,7 +110,7 @@ trap$O:		/$objtype/include/ureg.h
 devether.$0:	etherif.h ../port/netif.h
 etherkw.$0:	etherif.h ../port/netif.h
 
-l.$O lexception.$O lproc.$O: arm.s arm.h mem.h cache.v5.s
+l.$O lexception.$O lproc.$O: arm.s arm.h mem.h
 
 init.h:D:	../port/initcode.c init9.s
 	$CC ../port/initcode.c

sys/src/9/kw/plug

@@ -28,7 +28,8 @@ dev
 ##	kbin
 
 	uart
-	usb
+# usb is temporarily excluded until we add cache ops to it, 16 apr 2010
+#	usb
 
 link
 	etherkw		ethermii
@@ -36,7 +37,7 @@ link
 	ethermedium
 	loopbackmedium
 	netdevmedium
-	usbehci
+#	usbehci
 
 ip
 	tcp
@@ -66,5 +67,5 @@ bootdir
 	boot$CONF.out boot
 	/arm/bin/ip/ipconfig ipconfig
 	/arm/bin/auth/factotum factotum
-	/arm/bin/usb/usbd
+#	/arm/bin/usb/usbd
 	nvram

sys/src/9/kw/plug.words

@@ -2,8 +2,16 @@ global scale sheevaplug
 
 marvell 88f6281 (feroceon kirkwood) SoC; ours are revision A0
 arm926ej-s rev 1 [56251311] (armv5tejl) 1.2GHz cpu
-i & d l1 caches 16K each, associativity 4, 32-byte lines, 128 sets
-unified l2 cache 256K, associativity 4, 32-byte lines
+
+l1 I & D VIVT caches 16K each: 4-way, 128 sets, 32-byte lines
+	l1 D is write-through, l1 I is write-back
+unified l2 PIPT cache 256K: 4-way, 2048 sets, 32-byte lines
+	potentially 512K: 8-way
+thus the l1 caches need to be flushed or invalidated when mmu mappings
+change, but l2 only needs to be flushed or invalidated around dma
+operations, and only the affected dma buffers need to be flushed or
+invalidated in l2.
+
 512MB of dram at physical address 0
 512MB of flash
 16550 uart for console
@@ -20,9 +28,8 @@ ___
 unfinished business:
 
 usb almost works.  we can see devices but not perform i/o to them.
-
-the l2 cache is run write-through because setting it to write-back
-makes the kernel wedge shortly after it starts running user processes.
+this may be due to lack of cache flushing and invalidation around dma
+operations.
 
 access to nand or spi flash would be handy for nvram and small
 fossils.  flash access isn't well documented.  inferno implements

sys/src/9/kw/syscall.c

@@ -188,7 +188,7 @@ syscall(Ureg* ureg)
 	int i, scallnr;
 
 	if(!userureg(ureg))
-		panic("syscall: pc %#ux r14 %#ux psr %#ux",
+		panic("syscall: from kernel: pc %#ux r14 %#ux psr %#ux",
 			ureg->pc, ureg->r14, ureg->psr);
 
 	cycles(&up->kentry);

sys/src/9/kw/usbehci.c

@@ -34,6 +34,10 @@ typedef struct Qtree Qtree;
 typedef struct Isoio Isoio;
 typedef struct Poll Poll;
 
+enum {
+	Debug = 0,
+};
+
 /*
  * EHCI interface registers and bits
  */
@@ -3224,6 +3228,8 @@ addrmapdump(void)
 	Kwusb *map;
 	Usbwin *win;
 
+	if (!Debug)
+		return;
 	map = (Kwusb *)(Addrusb + 0x300);
 	for (i = 0; i < nelem(map->win); i++) {
 		win = &map->win[i];
@@ -3232,8 +3238,8 @@ addrmapdump(void)
 			targ = WINTARG(ctl);
 			attr = WINATTR(ctl);
 			size64k = WIN64KSIZE(ctl);
-			print("usbehci: address map window %d: "
-				"targ %ld attr %#lux size %,ld addr %#lux\n",
+			print("usbehci: addr map window %d: targ %ld "
+				"attr %#lux size %,ld addr %#lux\n",
 				i, targ, attr, size64k * 64*1024, win->base);
 		}
 	}

sys/src/cmd/netstat.c

@@ -63,14 +63,14 @@ main(int argc, char *argv[])
 		exits(0);
 	}
 
-	fd = open(netroot, OREAD);
-	if(fd < 0)
-		sysfatal("open %s: %r", netroot);
-
 	if(nproto){
 		for(i=0; i<nproto; i++)
 			nstat(proto[i], pip);
 	}else{
+		fd = open(netroot, OREAD);
+		if(fd < 0)
+			sysfatal("open %s: %r", netroot);
+
 		tot = dirreadall(fd, &d);
 		for(i=0; i<tot; i++){
 			if(strcmp(d[i].name, "ipifc") == 0)
@@ -131,38 +131,37 @@ pip(char *net, Dir *db)
 	if(strcmp(db->name, "stats") == 0)
 		return;
 
-	snprint(buf, sizeof buf, "%s/%s/%s/ctl", netroot, net, db->name);
-
-	sprint(buf, "%s/%s/%s/status", netroot, net, db->name);
+	snprint(buf, sizeof buf, "%s/%s/%s/status", netroot, net, db->name);
 	fd = open(buf, OREAD);
 	if(fd < 0)
 		return;
-
 	n = read(fd, buf, sizeof(buf));
+	close(fd);
 	if(n < 0)
 		return;
 	buf[n] = 0;
-	close(fd);
 
 	p = strchr(buf, ' ');
 	if(p != 0)
 		*p = 0;
-	
+	p = strrchr(buf, '\n');
+	if(p != 0)
+		*p = 0;
 	Bprint(&out, "%-4s %-4s %-10s %-12s ", net, db->name, db->uid, buf);
 
-	sprint(buf, "%s/%s/%s/local", netroot, net, db->name);
+	snprint(buf, sizeof buf, "%s/%s/%s/local", netroot, net, db->name);
 	fd = open(buf, OREAD);
 	if(fd < 0) {
 		Bprint(&out, "\n");
 		return;
 	}
 	n = read(fd, buf, sizeof(buf));
+	close(fd);
 	if(n < 0) {
 		Bprint(&out, "\n");
 		return;
 	}
 	buf[n-1] = 0;
-	close(fd);
 	p = strchr(buf, '!');
 	if(p == 0) {
 		Bprint(&out, "\n");
@@ -171,21 +170,22 @@ pip(char *net, Dir *db)
 	*p = '\0';
 	Bprint(&out, "%-10s ", getport(net, p+1));
 
-	sprint(buf, "%s/%s/%s/remote", netroot, net, db->name);
+	snprint(buf, sizeof buf, "%s/%s/%s/remote", netroot, net, db->name);
 	fd = open(buf, OREAD);
 	if(fd < 0) {
 		print("\n");
 		return;
 	}
 	n = read(fd, buf, sizeof(buf));
+	close(fd);
 	if(n < 0) {
 		print("\n");
 		return;
 	}
 	buf[n-1] = 0;
-	close(fd);
 	p = strchr(buf, '!');
-	*p++ = '\0';
+	if(p != nil)
+		*p++ = '\0';
 
 	if(notrans){
 		Bprint(&out, "%-10s %s\n", getport(net, p), buf);