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@@ -90,7 +90,7 @@ enum {
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* an array of these structs is preceded by error_log at 0x20, control,
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* error_clear_single, error_clear_multi. first struct is at offset 0x48.
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*/
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-struct L3protreg { /* an L3 protection region */
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+struct L3protreg { /* hw: an L3 protection region */
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uvlong req_info_perm;
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uvlong read_perm;
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uvlong write_perm;
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@@ -105,7 +105,7 @@ enum {
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Permmpu = 1<<1,
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};
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-struct L3agent {
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+struct L3agent { /* hw registers */
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uchar _pad0[0x20];
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uvlong ctl;
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uvlong sts;
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@@ -245,7 +245,7 @@ log2(ulong n)
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int i;
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i = 31 - clz(n);
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- if (!ispow2(n))
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+ if (!ispow2(n) || n == 0)
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i++;
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return i;
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}
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@@ -254,13 +254,16 @@ void
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archconfinit(void)
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{
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char *p;
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+ ulong mhz;
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assert(m != nil);
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+ m->cpuhz = 500 * 1000 * 1000; /* beagle speed */
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p = getconf("*cpumhz");
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- if (p)
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- m->cpuhz = atoi(p) * 1000 * 1000;
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- else
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- m->cpuhz = 500 * 1000 * 1000; /* beagle speed */
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+ if (p) {
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+ mhz = atoi(p) * 1000 * 1000;
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+ if (mhz >= 100*1000*1000 && mhz <= 3000UL*1000*1000)
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+ m->cpuhz = mhz;
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+ }
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m->delayloop = m->cpuhz/2000; /* initial estimate */
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}
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@@ -832,9 +835,9 @@ prcachecfg(void)
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if (mc.linelen != CACHELINESZ)
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iprint(" *should* be %d", CACHELINESZ);
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if (mc.setsways & Cawt)
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- iprint("; can write-through");
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+ iprint("; can WT");
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if (mc.setsways & Cawb)
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- iprint("; can write-back");
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+ iprint("; can WB");
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#ifdef COMPULSIVE /* both caches can do this */
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if (mc.setsways & Cara)
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iprint("; can read-allocate");
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@@ -875,7 +878,7 @@ subarch(int impl, uint sa)
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}
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/*
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- * padconf bits in a short, 2 per register
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+ * padconf bits in a short, 2 per long register
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* 15 wakeupevent
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* 14 wakeupenable
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* 13 offpulltypeselect
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@@ -890,7 +893,61 @@ subarch(int impl, uint sa)
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*/
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enum {
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- Muxmode = MASK(3),
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+ /* pad config register bits */
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+ Inena = 1 << 8, /* input enable */
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+ Indis = 0 << 8, /* input disable */
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+ Ptup = 1 << 4, /* pull type up */
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+ Ptdown = 0 << 4, /* pull type down */
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+ Ptena = 1 << 3, /* pull type selection is active */
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+ Ptdis = 0 << 3, /* pull type selection is inactive */
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+ Muxmode = MASK(3),
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+
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+ /* pad config registers relevant to flash */
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+ GpmcA1 = 0x4800207A,
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+ GpmcA2 = 0x4800207C,
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+ GpmcA3 = 0x4800207E,
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+ GpmcA4 = 0x48002080,
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+ GpmcA5 = 0x48002082,
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+ GpmcA6 = 0x48002084,
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+ GpmcA7 = 0x48002086,
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+ GpmcA8 = 0x48002088,
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+ GpmcA9 = 0x4800208A,
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+ GpmcA10 = 0x4800208C,
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+ GpmcD0 = 0x4800208E,
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+ GpmcD1 = 0x48002090,
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+ GpmcD2 = 0x48002092,
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+ GpmcD3 = 0x48002094,
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+ GpmcD4 = 0x48002096,
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+ GpmcD5 = 0x48002098,
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+ GpmcD6 = 0x4800209A,
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+ GpmcD7 = 0x4800209C,
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+ GpmcD8 = 0x4800209E,
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+ GpmcD9 = 0x480020A0,
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+ GpmcD10 = 0x480020A2,
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+ GpmcD11 = 0x480020A4,
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+ GpmcD12 = 0x480020A6,
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+ GpmcD13 = 0x480020A8,
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+ GpmcD14 = 0x480020AA,
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+ GpmcD15 = 0x480020AC,
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+ GpmcNCS0 = 0x480020AE,
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+ GpmcNCS1 = 0x480020B0,
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+ GpmcNCS2 = 0x480020B2,
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+ GpmcNCS3 = 0x480020B4,
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+ GpmcNCS4 = 0x480020B6,
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+ GpmcNCS5 = 0x480020B8,
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+ GpmcNCS6 = 0x480020BA,
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+ GpmcNCS7 = 0x480020BC,
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+ GpmcCLK = 0x480020BE,
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+ GpmcNADV_ALE = 0x480020C0,
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+ GpmcNOE = 0x480020C2,
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+ GpmcNWE = 0x480020C4,
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+ GpmcNBE0_CLE = 0x480020C6,
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+ GpmcNBE1 = 0x480020C8,
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+ GpmcNWP = 0x480020CA,
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+ GpmcWAIT0 = 0x480020CC,
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+ GpmcWAIT1 = 0x480020CE,
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+ GpmcWAIT2 = 0x480020D0,
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+ GpmcWAIT3 = 0x480020D2,
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};
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/* set SCM pad config mux mode */
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@@ -902,12 +959,8 @@ setmuxmode(ulong addr, int shorts, int mode)
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for (ptr = (ushort *)addr; shorts-- > 0; ptr++) {
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omode = *ptr & Muxmode;
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- if (omode != mode) {
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-// print("scm pad %#p was mux mode %d, now %d\n",
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-// ptr, omode, mode);
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-// delay(10);
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+ if (omode != mode)
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*ptr = *ptr & ~Muxmode | mode & Muxmode;
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- }
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}
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coherence();
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}
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@@ -915,7 +968,7 @@ setmuxmode(ulong addr, int shorts, int mode)
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static void
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setpadmodes(void)
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{
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- ushort *ptr;
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+ int off;
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/* set scm pad modes for usb; hasn't made any difference yet */
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setmuxmode(0x48002166, 7, 5); /* hsusb3_tll; is mode 4 */
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@@ -931,10 +984,70 @@ setpadmodes(void)
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* igep only: mode 4 of 21d2 is gpio_176 (smsc9221 ether irq).
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* see ether9221.c for more.
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*/
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- ptr = (ushort *)0x480021d2;
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-// setmuxmode((uintptr)ptr, 1, 4);
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- /* input enable, pu/pd = 3, muxmode 4 */
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- *ptr = 1 << 8 | 3 << 3 | 4;
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+ *(ushort *)0x480021d2 = Inena | Ptup | Ptena | 4;
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+
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+ /* magic from u-boot */
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+ *(ushort *)GpmcA1 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA2 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA3 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA4 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA5 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA6 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA7 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA8 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA9 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcA10 = Indis | Ptup | Ptena | 0;
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+
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+ *(ushort *)GpmcD0 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD1 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD2 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD3 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD4 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD5 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD6 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD7 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD8 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD9 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD10 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD11 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD12 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD13 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD14 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcD15 = Inena | Ptup | Ptena | 0;
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+
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+ *(ushort *)GpmcNCS0 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcNCS1 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcNCS2 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcNCS3 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcNCS4 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcNCS5 = Indis | Ptup | Ptena | 0;
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+ *(ushort *)GpmcNCS6 = Indis | Ptup | Ptena | 0;
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+
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+ *(ushort *)GpmcNOE = Indis | Ptdown | Ptdis | 0;
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+ *(ushort *)GpmcNWE = Indis | Ptdown | Ptdis | 0;
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+
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+ *(ushort *)GpmcWAIT2 = Inena | Ptup | Ptena | 4; /* GPIO_64 -ETH_NRESET */
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+ *(ushort *)GpmcNCS7 = Inena | Ptup | Ptena | 1; /* SYS_nDMA_REQ3 */
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+
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+ *(ushort *)GpmcCLK = Indis | Ptdown | Ptdis | 0;
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+
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+ *(ushort *)GpmcNBE1 = Inena | Ptdown | Ptdis | 0;
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+
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+ *(ushort *)GpmcNADV_ALE = Indis | Ptdown | Ptdis | 0;
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+ *(ushort *)GpmcNBE0_CLE = Indis | Ptdown | Ptdis | 0;
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+
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+ *(ushort *)GpmcNWP = Inena | Ptdown | Ptdis | 0;
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+
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+ *(ushort *)GpmcWAIT0 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcWAIT1 = Inena | Ptup | Ptena | 0;
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+ *(ushort *)GpmcWAIT3 = Inena | Ptup | Ptena | 0;
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+
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+ /*
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+ * magic from u-boot: set 0xe00 bits in gpmc_(nwe|noe|nadv_ale)
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+ * to enable `off' mode for each.
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+ */
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+ for (off = 0xc0; off <= 0xc4; off += sizeof(short))
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+ *((ushort *)(PHYSSCM + off)) |= 0xe00;
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coherence();
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}
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