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+/*
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+ * Realtek RTL8110S/8169S.
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+ * Mostly there. There are some magic register values used
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+ * which are not described in any datasheet or driver but seem
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+ * to be necessary.
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+ * Why is the Fovf descriptor bit set for every received packet?
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+ * Occasionally the hardware indicates an input TCP checksum error
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+ * although the higher-level software seems to check the packet OK?
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+ * No tuning has been done. Only tested on an RTL8110S, there
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+ * are slight differences between the chips in the series so some
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+ * tweaks may be needed.
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+ */
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+#include "u.h"
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+#include "lib.h"
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+#include "mem.h"
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+#include "dat.h"
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+#include "fns.h"
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+#include "io.h"
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+
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+
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+typedef struct QLock { int r; } QLock;
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+#define qlock(i) while(0)
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+#define qunlock(i) while(0)
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+#define iallocb allocb
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+extern void mb386(void);
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+#define coherence() mb386()
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+#define iprint print
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+#define mallocalign(n, a, o, s) ialloc((n), (a))
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+
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+#include "etherif.h"
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+#include "ethermii.h"
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+
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+enum { /* registers */
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+ Idr0 = 0x00, /* MAC address */
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+ Mar0 = 0x08, /* Multicast address */
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+ Dtccr = 0x10, /* Dump Tally Counter Command */
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+ Tnpds = 0x20, /* Transmit Normal Priority Descriptors */
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+ Thpds = 0x28, /* Transmit High Priority Descriptors */
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+ Flash = 0x30, /* Flash Memory Read/Write */
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+ Erbcr = 0x34, /* Early Receive Byte Count */
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+ Ersr = 0x36, /* Early Receive Status */
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+ Cr = 0x37, /* Command Register */
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+ Tppoll = 0x38, /* Transmit Priority Polling */
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+ Imr = 0x3C, /* Interrupt Mask */
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+ Isr = 0x3E, /* Interrupt Status */
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+ Tcr = 0x40, /* Transmit Configuration */
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+ Rcr = 0x44, /* Receive Configuration */
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+ Tctr = 0x48, /* Timer Count */
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+ Mpc = 0x4C, /* Missed Packet Counter */
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+ Cr9346 = 0x50, /* 9346 Command Register */
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+ Config0 = 0x51, /* Configuration Register 0 */
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+ Config1 = 0x52, /* Configuration Register 1 */
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+ Config2 = 0x53, /* Configuration Register 2 */
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+ Config3 = 0x54, /* Configuration Register 3 */
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+ Config4 = 0x55, /* Configuration Register 4 */
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+ Config5 = 0x56, /* Configuration Register 5 */
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+ Timerint = 0x58, /* Timer Interrupt */
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+ Mulint = 0x5C, /* Multiple Interrupt Select */
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+ Phyar = 0x60, /* PHY Access */
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+ Tbicsr0 = 0x64, /* TBI Control and Status */
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+ Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
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+ Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
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+ Phystatus = 0x6C, /* PHY Status */
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+
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+ Rms = 0xDA, /* Receive Packet Maximum Size */
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+ Cplusc = 0xE0, /* C+ Command */
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+ Rdsar = 0xE4, /* Receive Descriptor Start Address */
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+ Mtps = 0xEC, /* Max. Transmit Packet Size */
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+};
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+
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+enum { /* Dtccr */
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+ Cmd = 0x00000008, /* Command */
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+};
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+
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+enum { /* Cr */
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+ Te = 0x04, /* Transmitter Enable */
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+ Re = 0x08, /* Receiver Enable */
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+ Rst = 0x10, /* Software Reset */
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+};
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+
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+enum { /* Tppoll */
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+ Fswint = 0x01, /* Forced Software Interrupt */
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+ Npq = 0x40, /* Normal Priority Queue polling */
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+ Hpq = 0x80, /* High Priority Queue polling */
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+};
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+
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+enum { /* Imr/Isr */
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+ Rok = 0x0001, /* Receive OK */
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+ Rer = 0x0002, /* Receive Error */
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+ Tok = 0x0004, /* Transmit OK */
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+ Ter = 0x0008, /* Transmit Error */
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+ Rdu = 0x0010, /* Receive Descriptor Unavailable */
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+ Punlc = 0x0020, /* Packet Underrun or Link Change */
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+ Fovw = 0x0040, /* Receive FIFO Overflow */
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+ Tdu = 0x0080, /* Transmit Descriptor Unavailable */
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+ Swint = 0x0100, /* Software Interrupt */
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+ Timeout = 0x4000, /* Timer */
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+ Serr = 0x8000, /* System Error */
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+};
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+
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+enum { /* Tcr */
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+ MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
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+ MtxdmaMASK = 0x00000700,
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+ Mtxdmaunlimited = 0x00000700,
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+ Acrc = 0x00010000, /* Append CRC (not) */
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+ Lbk0 = 0x00020000, /* Loopback Test 0 */
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+ Lbk1 = 0x00040000, /* Loopback Test 1 */
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+ Ifg2 = 0x00080000, /* Interframe Gap 2 */
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+ HwveridSHIFT = 23, /* Hardware Version ID */
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+ HwveridMASK = 0x7C800000,
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+ Ifg0 = 0x01000000, /* Interframe Gap 0 */
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+ Ifg1 = 0x02000000, /* Interframe Gap 1 */
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+};
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+
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+enum { /* Rcr */
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+ Aap = 0x00000001, /* Accept All Packets */
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+ Apm = 0x00000002, /* Accept Physical Match */
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+ Am = 0x00000004, /* Accept Multicast */
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+ Ab = 0x00000008, /* Accept Broadcast */
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+ Ar = 0x00000010, /* Accept Runt */
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+ Aer = 0x00000020, /* Accept Error */
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+ Sel9356 = 0x00000040, /* 9356 EEPROM used */
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+ MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
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+ MrxdmaMASK = 0x00000700,
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+ Mrxdmaunlimited = 0x00000700,
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+ RxfthSHIFT = 13, /* Receive Buffer Length */
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+ RxfthMASK = 0x0000E000,
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+ Rxfth256 = 0x00008000,
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+ Rxfthnone = 0x0000E000,
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+ Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
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+ MulERINT = 0x01000000, /* Multiple Early Interrupt Select */
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+};
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+
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+enum { /* Cr9346 */
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+ Eedo = 0x01, /* */
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+ Eedi = 0x02, /* */
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+ Eesk = 0x04, /* */
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+ Eecs = 0x08, /* */
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+ Eem0 = 0x40, /* Operating Mode */
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+ Eem1 = 0x80,
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+};
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+
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+enum { /* Phyar */
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+ DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */
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+ DataSHIFT = 0,
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+ RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */
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+ RegaddrSHIFT = 16,
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+ Flag = 0x80000000, /* */
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+};
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+
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+enum { /* Phystatus */
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+ Fd = 0x01, /* Full Duplex */
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+ Linksts = 0x02, /* Link Status */
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+ Speed10 = 0x04, /* */
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+ Speed100 = 0x08, /* */
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+ Speed1000 = 0x10, /* */
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+ Rxflow = 0x20, /* */
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+ Txflow = 0x40, /* */
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+ Entbi = 0x80, /* */
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+};
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+
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+enum { /* Cplusc */
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+ Mulrw = 0x0008, /* PCI Multiple R/W Enable */
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+ Dac = 0x0010, /* PCI Dual Address Cycle Enable */
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+ Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
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+ Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */
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+ Endian = 0x0200, /* Endian Mode */
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+};
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+
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+typedef struct D D; /* Transmit/Receive Descriptor */
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+struct D {
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+ u32int control;
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+ u32int vlan;
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+ u32int addrlo;
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+ u32int addrhi;
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+};
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+
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+enum { /* Transmit Descriptor control */
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+ TxflMASK = 0x0000FFFF, /* Transmit Frame Length */
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+ TxflSHIFT = 0,
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+ Tcps = 0x00010000, /* TCP Checksum Offload */
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+ Udpcs = 0x00020000, /* UDP Checksum Offload */
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+ Ipcs = 0x00040000, /* IP Checksum Offload */
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+ Lgsen = 0x08000000, /* Large Send */
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+};
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+
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+enum { /* Receive Descriptor control */
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+ RxflMASK = 0x00003FFF, /* Receive Frame Length */
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+ RxflSHIFT = 0,
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+ Tcpf = 0x00004000, /* TCP Checksum Failure */
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+ Udpf = 0x00008000, /* UDP Checksum Failure */
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+ Ipf = 0x00010000, /* IP Checksum Failure */
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+ Pid0 = 0x00020000, /* Protocol ID0 */
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+ Pid1 = 0x00040000, /* Protocol ID1 */
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+ Crce = 0x00080000, /* CRC Error */
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+ Runt = 0x00100000, /* Runt Packet */
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+ Res = 0x00200000, /* Receive Error Summary */
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+ Rwt = 0x00400000, /* Receive Watchdog Timer Expired */
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+ Fovf = 0x00800000, /* FIFO Overflow */
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+ Bovf = 0x01000000, /* Buffer Overflow */
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+ Bar = 0x02000000, /* Broadcast Address Received */
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+ Pam = 0x04000000, /* Physical Address Matched */
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+ Mar = 0x08000000, /* Multicast Address Received */
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+};
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+
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+enum { /* General Descriptor control */
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+ Ls = 0x10000000, /* Last Segment Descriptor */
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+ Fs = 0x20000000, /* First Segment Descriptor */
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+ Eor = 0x40000000, /* End of Descriptor Ring */
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+ Own = 0x80000000, /* Ownership */
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+};
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+
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+/*
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+ */
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+enum { /* Ring sizes (<= 1024) */
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+ Ntd = 8, /* Transmit Ring */
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+ Nrd = 32, /* Receive Ring */
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+
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+ Mps = ROUNDUP(ETHERMAXTU+4, 128),
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+};
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+
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+typedef struct Dtcc Dtcc;
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+struct Dtcc {
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+ u64int txok;
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+ u64int rxok;
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+ u64int txer;
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+ u32int rxer;
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+ u16int misspkt;
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+ u16int fae;
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+ u32int tx1col;
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+ u32int txmcol;
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+ u64int rxokph;
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+ u64int rxokbrd;
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+ u32int rxokmu;
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+ u16int txabt;
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+ u16int txundrn;
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+};
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+
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+typedef struct Ctlr Ctlr;
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+typedef struct Ctlr {
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+ int port;
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+ Pcidev* pcidev;
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+ Ctlr* next;
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+ int active;
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+ uint id;
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+
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+ QLock alock; /* attach */
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+ Lock ilock; /* init */
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+ int init; /* */
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+
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+ Mii* mii;
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+
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+ Lock tlock; /* transmit */
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+ D* td; /* descriptor ring */
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+ Block** tb; /* transmit buffers */
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+ int ntd;
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+
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+ int tdh; /* head - producer index (host) */
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+ int tdt; /* tail - consumer index (NIC) */
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+ int ntdfree;
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+ int ntq;
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+
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+ int mtps; /* Max. Transmit Packet Size */
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+
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+ Lock rlock; /* receive */
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+ D* rd; /* descriptor ring */
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+ void** rb; /* receive buffers */
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+ int nrd;
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+
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+ int rdh; /* head - producer index (NIC) */
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+ int rdt; /* tail - consumer index (host) */
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+ int nrdfree;
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+
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+ int rcr; /* receive configuration register */
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+
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+ QLock slock; /* statistics */
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+ Dtcc* dtcc;
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+ uint txdu;
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+ uint tcpf;
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+ uint udpf;
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+ uint ipf;
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+ uint fovf;
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+ uint ierrs;
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+ uint rer;
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+ uint rdu;
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+ uint punlc;
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+ uint fovw;
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+} Ctlr;
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+
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+static Ctlr* ctlrhead;
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+static Ctlr* ctlrtail;
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+
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+#define csr8r(c, r) (inb((c)->port+(r)))
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+#define csr16r(c, r) (ins((c)->port+(r)))
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+#define csr32r(c, r) (inl((c)->port+(r)))
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+#define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
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+#define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
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+#define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
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+
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+static int
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+rtl8169miimir(Mii* mii, int pa, int ra)
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+{
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+ uint r;
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+ int timeo;
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+ Ctlr *ctlr;
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+
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+ if(pa != 1)
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+ return -1;
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+ ctlr = mii->ctlr;
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+
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+ r = (ra<<16) & RegaddrMASK;
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+ csr32w(ctlr, Phyar, r);
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+ delay(1);
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+ for(timeo = 0; timeo < 2000; timeo++){
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+ if((r = csr32r(ctlr, Phyar)) & Flag)
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+ break;
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+ microdelay(100);
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+ }
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+ if(!(r & Flag))
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+ return -1;
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+
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+ return (r & DataMASK)>>DataSHIFT;
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+}
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+
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+static int
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+rtl8169miimiw(Mii* mii, int pa, int ra, int data)
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+{
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+ uint r;
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+ int timeo;
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+ Ctlr *ctlr;
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+
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+ if(pa != 1)
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+ return -1;
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+ ctlr = mii->ctlr;
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+
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+ r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
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+ csr32w(ctlr, Phyar, r);
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+ delay(1);
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+ for(timeo = 0; timeo < 2000; timeo++){
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+ if(!((r = csr32r(ctlr, Phyar)) & Flag))
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+ break;
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+ microdelay(100);
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+ }
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+ if(r & Flag)
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+ return -1;
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+
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+ return 0;
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+}
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+
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+static int
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+rtl8169mii(Ctlr* ctlr)
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+{
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+ MiiPhy *phy;
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+
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+ /*
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+ * Link management.
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+ */
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+ if((ctlr->mii = malloc(sizeof(Mii))) == nil)
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+ return -1;
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+ ctlr->mii->mir = rtl8169miimir;
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+ ctlr->mii->miw = rtl8169miimiw;
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+ ctlr->mii->ctlr = ctlr;
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+ rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
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+
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+ if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
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+ free(ctlr->mii);
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+ ctlr->mii = nil;
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+ return -1;
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+ }
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+ print("oui %X phyno %d\n", phy->oui, phy->phyno);
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+
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+ miiane(ctlr->mii, ~0, ~0, ~0);
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+
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+ return 0;
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+}
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+
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+static int
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+rtl8169reset(Ctlr* ctlr)
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+{
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+ int timeo;
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+
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+ /*
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+ * Soft reset the controller.
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+ */
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+ csr8w(ctlr, Cr, Rst);
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+ for(timeo = 0; timeo < 1000; timeo++){
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+ if(!(csr8r(ctlr, Cr) & Rst))
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+ return 0;
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+ delay(1);
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+ }
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+
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+ return -1;
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+}
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+
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+static void
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+rtl8169detach(Ether* edev)
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+{
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+ rtl8169reset(edev->ctlr);
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+}
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+
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+static void
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+rtl8169halt(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ csr8w(ctlr, Cr, 0);
|
|
|
+ csr16w(ctlr, Imr, 0);
|
|
|
+ csr16w(ctlr, Isr, ~0);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169replenish(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ D *d;
|
|
|
+ int rdt;
|
|
|
+ void *bp;
|
|
|
+
|
|
|
+ rdt = ctlr->rdt;
|
|
|
+ while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
|
|
|
+ d = &ctlr->rd[rdt];
|
|
|
+ if(ctlr->rb[rdt] == nil){
|
|
|
+ /*
|
|
|
+ * simple allocation for now
|
|
|
+ */
|
|
|
+ bp = malloc(Mps);
|
|
|
+ ctlr->rb[rdt] = bp;
|
|
|
+ d->addrlo = PCIWADDR(bp);
|
|
|
+ d->addrhi = 0;
|
|
|
+ }
|
|
|
+ coherence();
|
|
|
+ d->control |= Own|Mps;
|
|
|
+ rdt = NEXT(rdt, ctlr->nrd);
|
|
|
+ ctlr->nrdfree++;
|
|
|
+ }
|
|
|
+ ctlr->rdt = rdt;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169init(Ether* edev)
|
|
|
+{
|
|
|
+ uint r;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ ilock(&ctlr->ilock);
|
|
|
+
|
|
|
+ rtl8169halt(ctlr);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst settings
|
|
|
+ * in Tcr/Rcr.
|
|
|
+ */
|
|
|
+ csr16w(ctlr, Cplusc, (1<<14)|Rxchksum|Mulrw); /* magic (1<<14) */
|
|
|
+
|
|
|
+ /*
|
|
|
+ * MAC Address.
|
|
|
+ * Must put chip into config register write enable mode.
|
|
|
+ */
|
|
|
+ csr8w(ctlr, Cr9346, Eem1|Eem0);
|
|
|
+ r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
|
|
|
+ csr32w(ctlr, Idr0, r);
|
|
|
+ r = (edev->ea[5]<<8)|edev->ea[4];
|
|
|
+ csr32w(ctlr, Idr0+4, r);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Enable receiver/transmitter.
|
|
|
+ * Need to do this first or some of the settings below
|
|
|
+ * won't take.
|
|
|
+ */
|
|
|
+ csr8w(ctlr, Cr, Te|Re);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Transmitter.
|
|
|
+ * Mtps is in units of 128.
|
|
|
+ */
|
|
|
+ memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
|
|
|
+ ctlr->tdh = ctlr->tdt = 0;
|
|
|
+ ctlr->td[ctlr->ntd-1].control = Eor;
|
|
|
+ ctlr->mtps = HOWMANY(Mps, 128);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Receiver.
|
|
|
+ */
|
|
|
+ memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
|
|
|
+ ctlr->rdh = ctlr->rdt = 0;
|
|
|
+ ctlr->rd[ctlr->nrd-1].control = Eor;
|
|
|
+
|
|
|
+ //for(i = 0; i < ctlr->nrd; i++){
|
|
|
+ // if((bp = ctlr->rb[i]) != nil){
|
|
|
+ // ctlr->rb[i] = nil;
|
|
|
+ // freeb(bp);
|
|
|
+ // }
|
|
|
+ //}
|
|
|
+ rtl8169replenish(ctlr);
|
|
|
+ ctlr->rcr = Rxfth256|Mrxdmaunlimited|Ab|Apm;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Interrupts.
|
|
|
+ * Disable Tdu|Tok for now, the transmit routine will tidy.
|
|
|
+ * Tdu means the NIC ran out of descritors to send, so it
|
|
|
+ * doesn't really need to ever be on.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Timerint, 0);
|
|
|
+ csr16w(ctlr, Imr, Serr|Timeout/*|Tdu*/|Fovw|Punlc|Rdu|Ter/*|Tok*/|Rer|Rok);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Clear missed-packet counter;
|
|
|
+ * initial early transmit threshold value;
|
|
|
+ * set the descriptor ring base addresses;
|
|
|
+ * set the maximum receive packet size;
|
|
|
+ * no early-receive interrupts.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Mpc, 0);
|
|
|
+ csr8w(ctlr, Mtps, ctlr->mtps);
|
|
|
+ csr32w(ctlr, Tnpds+4, 0);
|
|
|
+ csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
|
|
|
+ csr32w(ctlr, Rdsar+4, 0);
|
|
|
+ csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
|
|
|
+ csr16w(ctlr, Rms, Mps);
|
|
|
+ csr16w(ctlr, Mulint, 0);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set configuration.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
|
|
|
+ csr32w(ctlr, Rcr, ctlr->rcr);
|
|
|
+ csr16w(ctlr, 0xE2, 0); /* magic */
|
|
|
+
|
|
|
+ csr8w(ctlr, Cr9346, 0);
|
|
|
+
|
|
|
+ iunlock(&ctlr->ilock);
|
|
|
+
|
|
|
+ //rtl8169mii(ctlr);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169attach(Ether* edev)
|
|
|
+{
|
|
|
+ int timeo;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ qlock(&ctlr->alock);
|
|
|
+ if(ctlr->init == 0){
|
|
|
+ /*
|
|
|
+ * Handle allocation/init errors here.
|
|
|
+ */
|
|
|
+ ctlr->td = xspanalloc(sizeof(D)*Ntd, 256, 0);
|
|
|
+ ctlr->tb = malloc(Ntd*sizeof(Block*));
|
|
|
+ ctlr->ntd = Ntd;
|
|
|
+ ctlr->rd = xspanalloc(sizeof(D)*Nrd, 256, 0);
|
|
|
+ ctlr->rb = malloc(Nrd*sizeof(Block*));
|
|
|
+ ctlr->nrd = Nrd;
|
|
|
+ ctlr->dtcc = xspanalloc(sizeof(Dtcc), 64, 0);
|
|
|
+ rtl8169init(edev);
|
|
|
+ ctlr->init = 1;
|
|
|
+ }
|
|
|
+ qunlock(&ctlr->alock);
|
|
|
+
|
|
|
+ for(timeo = 0; timeo < 3500; timeo++){
|
|
|
+ if(miistatus(ctlr->mii) == 0)
|
|
|
+ break;
|
|
|
+ delay(10);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169transmit(Ether* edev)
|
|
|
+{
|
|
|
+ D *d;
|
|
|
+ Block *bp;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int control, x;
|
|
|
+ RingBuf *tb;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ ilock(&ctlr->tlock);
|
|
|
+ for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
|
|
|
+ d = &ctlr->td[x];
|
|
|
+ if((control = d->control) & Own)
|
|
|
+ break;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Check errors and log here.
|
|
|
+ */
|
|
|
+ USED(control);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Free it up.
|
|
|
+ * Need to clean the descriptor here? Not really.
|
|
|
+ * Simple freeb for now (no chain and freeblist).
|
|
|
+ * Use ntq count for now.
|
|
|
+ */
|
|
|
+ freeb(ctlr->tb[x]);
|
|
|
+ ctlr->tb[x] = nil;
|
|
|
+ d->control &= Eor;
|
|
|
+
|
|
|
+ ctlr->ntq--;
|
|
|
+ }
|
|
|
+ ctlr->tdh = x;
|
|
|
+
|
|
|
+ x = ctlr->tdt;
|
|
|
+ while(ctlr->ntq < (ctlr->ntd-1)){
|
|
|
+ tb = &edev->tb[edev->ti];
|
|
|
+ if(tb->owner != Interface)
|
|
|
+ break;
|
|
|
+
|
|
|
+ bp = allocb(tb->len);
|
|
|
+ memmove(bp->wp, tb->pkt, tb->len);
|
|
|
+ memmove(bp->wp+Eaddrlen, edev->ea, Eaddrlen);
|
|
|
+ bp->wp += tb->len;
|
|
|
+
|
|
|
+ tb->owner = Host;
|
|
|
+ edev->ti = NEXT(edev->ti, edev->ntb);
|
|
|
+
|
|
|
+ d = &ctlr->td[x];
|
|
|
+ d->addrlo = PCIWADDR(bp->rp);
|
|
|
+ d->addrhi = 0;
|
|
|
+ ctlr->tb[x] = bp;
|
|
|
+ coherence();
|
|
|
+ d->control |= Own|Fs|Ls|((BLEN(bp)<<TxflSHIFT) & TxflMASK);
|
|
|
+
|
|
|
+ x = NEXT(x, ctlr->ntd);
|
|
|
+ ctlr->ntq++;
|
|
|
+ }
|
|
|
+ if(x != ctlr->tdt){
|
|
|
+ ctlr->tdt = x;
|
|
|
+ csr8w(ctlr, Tppoll, Npq);
|
|
|
+ }
|
|
|
+ else if(ctlr->ntq >= (ctlr->ntd-1))
|
|
|
+ ctlr->txdu++;
|
|
|
+
|
|
|
+ iunlock(&ctlr->tlock);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169receive(Ether* edev)
|
|
|
+{
|
|
|
+ D *d;
|
|
|
+ int len, rdh;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ u32int control;
|
|
|
+ RingBuf *ring;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ rdh = ctlr->rdh;
|
|
|
+ for(;;){
|
|
|
+ d = &ctlr->rd[rdh];
|
|
|
+
|
|
|
+ if(d->control & Own)
|
|
|
+ break;
|
|
|
+
|
|
|
+ control = d->control;
|
|
|
+ if((control & (Fs|Ls|Res)) == (Fs|Ls)){
|
|
|
+ len = ((control & RxflMASK)>>RxflSHIFT) - 4;
|
|
|
+
|
|
|
+ ring = &edev->rb[edev->ri];
|
|
|
+ if(ring->owner == Interface){
|
|
|
+ ring->owner = Host;
|
|
|
+ ring->len = len;
|
|
|
+ memmove(ring->pkt, ctlr->rb[rdh], len);
|
|
|
+ edev->ri = NEXT(edev->ri, edev->nrb);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else{
|
|
|
+ /*
|
|
|
+ * Error stuff here.
|
|
|
+ print("control %8.8uX\n", control);
|
|
|
+ */
|
|
|
+ }
|
|
|
+ d->control &= Eor;
|
|
|
+ ctlr->nrdfree--;
|
|
|
+ rdh = NEXT(rdh, ctlr->nrd);
|
|
|
+ }
|
|
|
+ ctlr->rdh = rdh;
|
|
|
+
|
|
|
+ if(ctlr->nrdfree < ctlr->nrd/2)
|
|
|
+ rtl8169replenish(ctlr);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+rtl8169interrupt(Ureg*, void* arg)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+ Ether *edev;
|
|
|
+ u32int isr;
|
|
|
+
|
|
|
+ edev = arg;
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ while((isr = csr16r(ctlr, Isr)) != 0){
|
|
|
+ csr16w(ctlr, Isr, isr);
|
|
|
+ if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){
|
|
|
+ rtl8169receive(edev);
|
|
|
+ if(!(isr & (Punlc|Rok)))
|
|
|
+ ctlr->ierrs++;
|
|
|
+ if(isr & Rer)
|
|
|
+ ctlr->rer++;
|
|
|
+ if(isr & Rdu)
|
|
|
+ ctlr->rdu++;
|
|
|
+ if(isr & Punlc)
|
|
|
+ ctlr->punlc++;
|
|
|
+ if(isr & Fovw)
|
|
|
+ ctlr->fovw++;
|
|
|
+ isr &= ~(Fovw|Rdu|Rer|Rok);
|
|
|
+ }
|
|
|
+
|
|
|
+ if(isr & (Tdu|Ter|Tok)){
|
|
|
+ rtl8169transmit(edev);
|
|
|
+ isr &= ~(Tdu|Ter|Tok);
|
|
|
+ }
|
|
|
+
|
|
|
+ if(isr & Punlc){
|
|
|
+ //rtl8169link(edev);
|
|
|
+ isr &= ~Punlc;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Some of the reserved bits get set sometimes...
|
|
|
+ */
|
|
|
+ if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
|
|
|
+ panic("rtl8139interrupt: imr %4.4uX isr %4.4uX\n",
|
|
|
+ csr16r(ctlr, Imr), isr);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static Ctlr*
|
|
|
+rtl8169match(Ether* edev, int id)
|
|
|
+{
|
|
|
+ Pcidev *p;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int port;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Any adapter matches if no edev->port is supplied,
|
|
|
+ * otherwise the ports must match.
|
|
|
+ */
|
|
|
+ for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
|
+ if(ctlr->active)
|
|
|
+ continue;
|
|
|
+ p = ctlr->pcidev;
|
|
|
+ if(((p->did<<16)|p->vid) != id)
|
|
|
+ continue;
|
|
|
+ port = p->mem[0].bar & ~0x01;
|
|
|
+ if(edev->port != 0 && edev->port != port)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ ctlr->port = port;
|
|
|
+ if(rtl8169reset(ctlr))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ csr8w(ctlr, 0x82, 1); /* magic */
|
|
|
+
|
|
|
+ rtl8169mii(ctlr);
|
|
|
+
|
|
|
+ pcisetbme(p);
|
|
|
+ ctlr->active = 1;
|
|
|
+ return ctlr;
|
|
|
+ }
|
|
|
+ return nil;
|
|
|
+}
|
|
|
+
|
|
|
+static struct {
|
|
|
+ char* name;
|
|
|
+ int id;
|
|
|
+} rtl8169pci[] = {
|
|
|
+ { "rtl8169", (0x8169<<16)|0x10EC, }, /* generic */
|
|
|
+ { nil },
|
|
|
+};
|
|
|
+
|
|
|
+int
|
|
|
+rtl8169pnp(Ether* edev)
|
|
|
+{
|
|
|
+ Pcidev *p;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int i, id;
|
|
|
+ uchar ea[Eaddrlen];
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Make a list of all ethernet controllers
|
|
|
+ * if not already done.
|
|
|
+ */
|
|
|
+ if(ctlrhead == nil){
|
|
|
+ p = nil;
|
|
|
+ while(p = pcimatch(p, 0, 0)){
|
|
|
+ if(p->ccrb != 0x02 || p->ccru != 0)
|
|
|
+ continue;
|
|
|
+ ctlr = malloc(sizeof(Ctlr));
|
|
|
+ ctlr->pcidev = p;
|
|
|
+ ctlr->id = (p->did<<16)|p->vid;
|
|
|
+
|
|
|
+ if(ctlrhead != nil)
|
|
|
+ ctlrtail->next = ctlr;
|
|
|
+ else
|
|
|
+ ctlrhead = ctlr;
|
|
|
+ ctlrtail = ctlr;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Is it an RTL8169 under a different name?
|
|
|
+ * Normally a search is made through all the found controllers
|
|
|
+ * for one which matches any of the known vid+did pairs.
|
|
|
+ * If a vid+did pair is specified a search is made for that
|
|
|
+ * specific controller only.
|
|
|
+ */
|
|
|
+ id = 0;
|
|
|
+ for(i = 0; i < edev->nopt; i++){
|
|
|
+ if(cistrncmp(edev->opt[i], "id=", 3) == 0)
|
|
|
+ id = strtol(&edev->opt[i][3], nil, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ ctlr = nil;
|
|
|
+ if(id != 0)
|
|
|
+ ctlr = rtl8169match(edev, id);
|
|
|
+ else for(i = 0; rtl8169pci[i].name; i++){
|
|
|
+ if((ctlr = rtl8169match(edev, rtl8169pci[i].id)) != nil)
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ if(ctlr == nil)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ edev->ctlr = ctlr;
|
|
|
+ edev->port = ctlr->port;
|
|
|
+ edev->irq = ctlr->pcidev->intl;
|
|
|
+ edev->tbdf = ctlr->pcidev->tbdf;
|
|
|
+
|
|
|
+ /*
|
|
|
+ */
|
|
|
+ memset(ea, 0, Eaddrlen);
|
|
|
+ i = csr32r(ctlr, Idr0);
|
|
|
+ edev->ea[0] = i;
|
|
|
+ edev->ea[1] = i>>8;
|
|
|
+ edev->ea[2] = i>>16;
|
|
|
+ edev->ea[3] = i>>24;
|
|
|
+ i = csr32r(ctlr, Idr0+4);
|
|
|
+ edev->ea[4] = i;
|
|
|
+ edev->ea[5] = i>>8;
|
|
|
+
|
|
|
+ edev->attach = rtl8169attach;
|
|
|
+ edev->transmit = rtl8169transmit;
|
|
|
+ edev->interrupt = rtl8169interrupt;
|
|
|
+ edev->detach = rtl8169detach;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|