// ARM support defn acidinit() // Called after all the init modules are loaded { bplist = {}; bpfmt = 'X'; srcpath = { "./", "/sys/src/libc/port/", "/sys/src/libc/9sys/", "/sys/src/libc/arm/" }; srcfiles = {}; // list of loaded files srctext = {}; // the text of the files } defn linkreg(addr) { return *R14; } defn stk() // trace { _stk(*PC, *SP, linkreg(0), 0); } defn lstk() // trace with locals { _stk(*PC, *SP, linkreg(0), 1); } defn gpr() // print general purpose registers { print("R0\t", *R0, " R1\t", *R1, " R2\t", *R2, "\n"); print("R3\t", *R3, " R4\t", *R4, " R5\t", *R5, "\n"); print("R6\t", *R6, " R7\t", *R7, " R8\t", *R8, "\n"); print("R9\t", *R9, " R10\t", *R10, " R11\t", *R11, "\n"); print("R12\t", *R12, " R13\t", *R13, " R14\t", *R14, "\n"); print("R15\t", *R15, "\n"); } defn regs() // print all registers { gpr(); } defn pstop(pid) { local l; local pc; pc = *PC; print(pid,": ", reason(*TYPE), "\t"); print(fmt(pc, 'a'), "\t", fmt(pc, 'i'), "\n"); if notes then { if notes[0] != "sys: breakpoint" then { print("Notes pending:\n"); l = notes; while l do { print("\t", head l, "\n"); l = tail l; } } } } sizeofUreg=72; aggr Ureg { 'U' 0 r0; 'U' 4 r1; 'U' 8 r2; 'U' 12 r3; 'U' 16 r4; 'U' 20 r5; 'U' 24 r6; 'U' 28 r7; 'U' 32 r8; 'U' 36 r9; 'U' 40 r10; 'U' 44 r11; 'U' 48 r12; 'U' 52 r13; 'U' 56 r14; 'U' 60 type; 'U' 64 psr; 'U' 68 pc; }; defn Ureg(addr) { complex Ureg addr; print(" r0 ", addr.r0, "\n"); print(" r1 ", addr.r1, "\n"); print(" r2 ", addr.r2, "\n"); print(" r3 ", addr.r3, "\n"); print(" r4 ", addr.r4, "\n"); print(" r5 ", addr.r5, "\n"); print(" r6 ", addr.r6, "\n"); print(" r7 ", addr.r7, "\n"); print(" r8 ", addr.r8, "\n"); print(" r9 ", addr.r9, "\n"); print(" r10 ", addr.r10, "\n"); print(" r11 ", addr.r11, "\n"); print(" r12 ", addr.r12, "\n"); print(" r13 ", addr.r13, "\n"); print(" r14 ", addr.r14, "\n"); print(" type ", addr.type, "\n"); print(" psr ", addr.psr, "\n"); print(" pc ", addr.pc, "\n"); }; print("/sys/lib/acid/arm");