ether82563.c 24 KB

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  1. /*
  2. * bootstrap driver for
  3. * Intel 82563 Gigabit Ethernet Controller
  4. */
  5. #include "u.h"
  6. #include "lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "etherif.h"
  12. /* compatibility with cpu kernels */
  13. #define iallocb allocb
  14. #ifndef CACHELINESZ
  15. #define CACHELINESZ 32 /* pentium & later */
  16. #endif
  17. /* from pci.c */
  18. enum
  19. { /* command register (pcidev->pcr) */
  20. IOen = (1<<0),
  21. MEMen = (1<<1),
  22. MASen = (1<<2),
  23. MemWrInv = (1<<4),
  24. PErrEn = (1<<6),
  25. SErrEn = (1<<8),
  26. };
  27. /*
  28. * these are in the order they appear in the manual, not numeric order.
  29. * It was too hard to find them in the book. Ref 21489, rev 2.6
  30. */
  31. enum {
  32. /* General */
  33. Ctrl = 0x00000000, /* Device Control */
  34. Status = 0x00000008, /* Device Status */
  35. Eec = 0x00000010, /* EEPROM/Flash Control/Data */
  36. Eerd = 0x00000014, /* EEPROM Read */
  37. Ctrlext = 0x00000018, /* Extended Device Control */
  38. Fla = 0x0000001c, /* Flash Access */
  39. Mdic = 0x00000020, /* MDI Control */
  40. Seresctl = 0x00000024, /* Serdes ana */
  41. Fcal = 0x00000028, /* Flow Control Address Low */
  42. Fcah = 0x0000002C, /* Flow Control Address High */
  43. Fct = 0x00000030, /* Flow Control Type */
  44. Kumctrlsta = 0x00000034, /* Kumeran Controll and Status Register */
  45. Vet = 0x00000038, /* VLAN EtherType */
  46. Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
  47. Txcw = 0x00000178, /* Transmit Configuration Word */
  48. Rxcw = 0x00000180, /* Receive Configuration Word */
  49. Ledctl = 0x00000E00, /* LED control */
  50. Pba = 0x00001000, /* Packet Buffer Allocation */
  51. /* Interrupt */
  52. Icr = 0x000000C0, /* Interrupt Cause Read */
  53. Ics = 0x000000C8, /* Interrupt Cause Set */
  54. Ims = 0x000000D0, /* Interrupt Mask Set/Read */
  55. Imc = 0x000000D8, /* Interrupt mask Clear */
  56. Iam = 0x000000E0, /* Interrupt acknowledge Auto Mask */
  57. /* Receive */
  58. Rctl = 0x00000100, /* Receive Control */
  59. Ert = 0x00002008, /* Early Receive Threshold (573[EVL] only) */
  60. Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
  61. Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
  62. Psrctl = 0x00002170, /* Packet Split Receive Control */
  63. Rdbal = 0x00002800, /* Rdesc Base Address Low Queue 0 */
  64. Rdbah = 0x00002804, /* Rdesc Base Address High Queue 0 */
  65. Rdlen = 0x00002808, /* Receive Descriptor Length Queue 0 */
  66. Rdh = 0x00002810, /* Receive Descriptor Head Queue 0 */
  67. Rdt = 0x00002818, /* Receive Descriptor Tail Queue 0 */
  68. Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
  69. Rxdctl = 0x00002828, /* Receive Descriptor Control */
  70. Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
  71. Rdbal1 = 0x00002900, /* Rdesc Base Address Low Queue 1 */
  72. Rdbah1 = 0x00002804, /* Rdesc Base Address High Queue 1 */
  73. Rdlen1 = 0x00002908, /* Receive Descriptor Length Queue 1 */
  74. Rdh1 = 0x00002910, /* Receive Descriptor Head Queue 1 */
  75. Rdt1 = 0x00002918, /* Receive Descriptor Tail Queue 1 */
  76. Rxdctl1 = 0x00002928, /* Receive Descriptor Control Queue 1 */
  77. Rsrpd = 0x00002c00, /* Receive Small Packet Detect */
  78. Raid = 0x00002c08, /* Receive ACK interrupt delay */
  79. Cpuvec = 0x00002c10, /* CPU Vector */
  80. Rxcsum = 0x00005000, /* Receive Checksum Control */
  81. Rfctl = 0x00005008, /* Receive Filter Control */
  82. Mta = 0x00005200, /* Multicast Table Array */
  83. Ral = 0x00005400, /* Receive Address Low */
  84. Rah = 0x00005404, /* Receive Address High */
  85. Vfta = 0x00005600, /* VLAN Filter Table Array */
  86. Mrqc = 0x00005818, /* Multiple Receive Queues Command */
  87. Rssim = 0x00005864, /* RSS Interrupt Mask */
  88. Rssir = 0x00005868, /* RSS Interrupt Request */
  89. Reta = 0x00005c00, /* Redirection Table */
  90. Rssrk = 0x00005c80, /* RSS Random Key */
  91. /* Transmit */
  92. Tctl = 0x00000400, /* Transmit Control */
  93. Tipg = 0x00000410, /* Transmit IPG */
  94. Tdbal = 0x00003800, /* Tdesc Base Address Low */
  95. Tdbah = 0x00003804, /* Tdesc Base Address High */
  96. Tdlen = 0x00003808, /* Transmit Descriptor Length */
  97. Tdh = 0x00003810, /* Transmit Descriptor Head */
  98. Tdt = 0x00003818, /* Transmit Descriptor Tail */
  99. Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
  100. Txdctl = 0x00003828, /* Transmit Descriptor Control */
  101. Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
  102. Tarc0 = 0x00003840, /* Transmit Arbitration Counter Queue 0 */
  103. Tdbal1 = 0x00003900, /* Transmit Descriptor Base Low Queue 1 */
  104. Tdbah1 = 0x00003904, /* Transmit Descriptor Base High Queue 1 */
  105. Tdlen1 = 0x00003908, /* Transmit Descriptor Length Queue 1 */
  106. Tdh1 = 0x00003910, /* Transmit Descriptor Head Queue 1 */
  107. Tdt1 = 0x00003918, /* Transmit Descriptor Tail Queue 1 */
  108. Txdctl1 = 0x00003928, /* Transmit Descriptor Control 1 */
  109. Tarc1 = 0x00003940, /* Transmit Arbitration Counter Queue 1 */
  110. /* Statistics */
  111. Statistics = 0x00004000, /* Start of Statistics Area */
  112. Gorcl = 0x88/4, /* Good Octets Received Count */
  113. Gotcl = 0x90/4, /* Good Octets Transmitted Count */
  114. Torl = 0xC0/4, /* Total Octets Received */
  115. Totl = 0xC8/4, /* Total Octets Transmitted */
  116. Nstatistics = 64,
  117. };
  118. enum { /* Ctrl */
  119. GIOmd = (1<<2), /* BIO master disable */
  120. Lrst = (1<<3), /* link reset */
  121. Slu = (1<<6), /* Set Link Up */
  122. SspeedMASK = (3<<8), /* Speed Selection */
  123. SspeedSHIFT = 8,
  124. Sspeed10 = 0x00000000, /* 10Mb/s */
  125. Sspeed100 = 0x00000100, /* 100Mb/s */
  126. Sspeed1000 = 0x00000200, /* 1000Mb/s */
  127. Frcspd = (1<<11), /* Force Speed */
  128. Frcdplx = (1<<12), /* Force Duplex */
  129. SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
  130. SwdpinsloSHIFT = 18,
  131. SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
  132. SwdpioloSHIFT = 22,
  133. Devrst = (1<<26), /* Device Reset */
  134. Rfce = (1<<27), /* Receive Flow Control Enable */
  135. Tfce = (1<<28), /* Transmit Flow Control Enable */
  136. Vme = (1<<30), /* VLAN Mode Enable */
  137. Phy_rst = (1<<31), /* Phy Reset */
  138. };
  139. enum { /* Status */
  140. Lu = (1<<1), /* Link Up */
  141. Lanid = (3<<2), /* mask for Lan ID.
  142. Txoff = (1<<4), /* Transmission Paused */
  143. Tbimode = (1<<5), /* TBI Mode Indication */
  144. SpeedMASK = 0x000000C0,
  145. Speed10 = 0x00000000, /* 10Mb/s */
  146. Speed100 = 0x00000040, /* 100Mb/s */
  147. Speed1000 = 0x00000080, /* 1000Mb/s */
  148. Phyra = (1<<10), /* PHY Reset Asserted */
  149. GIOme = (1<<19), /* GIO Master Enable Status */
  150. };
  151. enum { /* Ctrl and Status */
  152. Fd = 0x00000001, /* Full-Duplex */
  153. AsdvMASK = 0x00000300,
  154. Asdv10 = 0x00000000, /* 10Mb/s */
  155. Asdv100 = 0x00000100, /* 100Mb/s */
  156. Asdv1000 = 0x00000200, /* 1000Mb/s */
  157. };
  158. enum { /* Eec */
  159. Sk = (1<<0), /* Clock input to the EEPROM */
  160. Cs = (1<<1), /* Chip Select */
  161. Di = (1<<2), /* Data Input to the EEPROM */
  162. Do = (1<<3), /* Data Output from the EEPROM */
  163. Areq = (1<<6), /* EEPROM Access Request */
  164. Agnt = (1<<7), /* EEPROM Access Grant */
  165. };
  166. enum { /* Eerd */
  167. ee_start = (1<<0), /* Start Read */
  168. ee_done = (1<<1), /* Read done */
  169. ee_addr = (0xfff8<<2), /* Read address [15:2] */
  170. ee_data = (0xffff<<16), /* Read Data; Data returned from eeprom/nvm */
  171. };
  172. enum { /* Ctrlext */
  173. Asdchk = (1<<12), /* ASD Check */
  174. Eerst = (1<<13), /* EEPROM Reset */
  175. Spdbyps = (1<<15), /* Speed Select Bypass */
  176. };
  177. enum { /* EEPROM content offsets */
  178. Ea = 0x00, /* Ethernet Address */
  179. Cf = 0x03, /* Compatibility Field */
  180. Icw1 = 0x0A, /* Initialization Control Word 1 */
  181. Sid = 0x0B, /* Subsystem ID */
  182. Svid = 0x0C, /* Subsystem Vendor ID */
  183. Did = 0x0D, /* Device ID */
  184. Vid = 0x0E, /* Vendor ID */
  185. Icw2 = 0x0F, /* Initialization Control Word 2 */
  186. };
  187. enum { /* Mdic */
  188. MDIdMASK = 0x0000FFFF, /* Data */
  189. MDIdSHIFT = 0,
  190. MDIrMASK = 0x001F0000, /* PHY Register Address */
  191. MDIrSHIFT = 16,
  192. MDIpMASK = 0x03E00000, /* PHY Address */
  193. MDIpSHIFT = 21,
  194. MDIwop = 0x04000000, /* Write Operation */
  195. MDIrop = 0x08000000, /* Read Operation */
  196. MDIready = 0x10000000, /* End of Transaction */
  197. MDIie = 0x20000000, /* Interrupt Enable */
  198. MDIe = 0x40000000, /* Error */
  199. };
  200. enum { /* Icr, Ics, Ims, Imc */
  201. Txdw = 0x00000001, /* Transmit Descriptor Written Back */
  202. Txqe = 0x00000002, /* Transmit Queue Empty */
  203. Lsc = 0x00000004, /* Link Status Change */
  204. Rxseq = 0x00000008, /* Receive Sequence Error */
  205. Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
  206. Rxo = 0x00000040, /* Receiver Overrun */
  207. Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
  208. Mdac = 0x00000200, /* MDIO Access Completed */
  209. Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
  210. Gpi0 = 0x00000800, /* General Purpose Interrupts */
  211. Gpi1 = 0x00001000,
  212. Gpi2 = 0x00002000,
  213. Gpi3 = 0x00004000,
  214. };
  215. enum { /* Txcw */
  216. TxcwFd = 0x00000020, /* Full Duplex */
  217. TxcwHd = 0x00000040, /* Half Duplex */
  218. TxcwPauseMASK = 0x00000180, /* Pause */
  219. TxcwPauseSHIFT = 7,
  220. TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
  221. TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
  222. TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
  223. TxcwRfiSHIFT = 12,
  224. TxcwNpr = 0x00008000, /* Next Page Request */
  225. TxcwConfig = 0x40000000, /* Transmit COnfig Control */
  226. TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
  227. };
  228. enum { /* Rctl */
  229. Rrst = 0x00000001, /* Receiver Software Reset */
  230. Ren = 0x00000002, /* Receiver Enable */
  231. Sbp = 0x00000004, /* Store Bad Packets */
  232. Upe = 0x00000008, /* Unicast Promiscuous Enable */
  233. Mpe = 0x00000010, /* Multicast Promiscuous Enable */
  234. Lpe = 0x00000020, /* Long Packet Reception Enable */
  235. LbmMASK = 0x000000C0, /* Loopback Mode */
  236. LbmOFF = 0x00000000, /* No Loopback */
  237. LbmTBI = 0x00000040, /* TBI Loopback */
  238. LbmMII = 0x00000080, /* GMII/MII Loopback */
  239. LbmXCVR = 0x000000C0, /* Transceiver Loopback */
  240. RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
  241. RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
  242. RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
  243. RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
  244. MoMASK = 0x00003000, /* Multicast Offset */
  245. Bam = 0x00008000, /* Broadcast Accept Mode */
  246. BsizeMASK = 0x00030000, /* Receive Buffer Size */
  247. Bsize2048 = 0x00000000,
  248. Bsize1024 = 0x00010000,
  249. Bsize512 = 0x00020000,
  250. Bsize256 = 0x00030000,
  251. Vfe = 0x00040000, /* VLAN Filter Enable */
  252. Cfien = 0x00080000, /* Canonical Form Indicator Enable */
  253. Cfi = 0x00100000, /* Canonical Form Indicator value */
  254. Dpf = 0x00400000, /* Discard Pause Frames */
  255. Pmcf = 0x00800000, /* Pass MAC Control Frames */
  256. Bsex = 0x02000000, /* Buffer Size Extension */
  257. Secrc = 0x04000000, /* Strip CRC from incoming packet */
  258. };
  259. enum { /* Tctl */
  260. Trst = 0x00000001, /* Transmitter Software Reset */
  261. Ten = 0x00000002, /* Transmit Enable */
  262. Psp = 0x00000008, /* Pad Short Packets */
  263. CtMASK = 0x00000FF0, /* Collision Threshold */
  264. CtSHIFT = 4,
  265. ColdMASK = 0x003FF000, /* Collision Distance */
  266. ColdSHIFT = 12,
  267. Swxoff = 0x00400000, /* Sofware XOFF Transmission */
  268. Pbe = 0x00800000, /* Packet Burst Enable */
  269. Rtlc = 0x01000000, /* Re-transmit on Late Collision */
  270. Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
  271. };
  272. enum { /* [RT]xdctl */
  273. PthreshMASK = 0x0000003F, /* Prefetch Threshold */
  274. PthreshSHIFT = 0,
  275. HthreshMASK = 0x00003F00, /* Host Threshold */
  276. HthreshSHIFT = 8,
  277. WthreshMASK = 0x003F0000, /* Writebacj Threshold */
  278. WthreshSHIFT = 16,
  279. Gran = 0x01000000, /* Granularity */
  280. };
  281. enum { /* Rxcsum */
  282. PcssMASK = 0x000000FF, /* Packet Checksum Start */
  283. PcssSHIFT = 0,
  284. Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
  285. Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
  286. };
  287. typedef struct Rdesc { /* Receive Descriptor */
  288. uint addr[2];
  289. ushort length;
  290. ushort checksum;
  291. uchar status;
  292. uchar errors;
  293. ushort special;
  294. } Rdesc;
  295. enum { /* Rdesc status */
  296. Rdd = 0x01, /* Descriptor Done */
  297. Reop = 0x02, /* End of Packet */
  298. Ixsm = 0x04, /* Ignore Checksum Indication */
  299. Vp = 0x08, /* Packet is 802.1Q (matched VET) */
  300. Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
  301. Ipcs = 0x40, /* IP Checksum Calculated on Packet */
  302. Pif = 0x80, /* Passed in-exact filter */
  303. };
  304. enum { /* Rdesc errors */
  305. Ce = 0x01, /* CRC Error or Alignment Error */
  306. Se = 0x02, /* Symbol Error */
  307. Seq = 0x04, /* Sequence Error */
  308. Cxe = 0x10, /* Carrier Extension Error */
  309. Tcpe = 0x20, /* TCP/UDP Checksum Error */
  310. Ipe = 0x40, /* IP Checksum Error */
  311. Rxe = 0x80, /* RX Data Error */
  312. };
  313. typedef struct Tdesc { /* Legacy+Normal Transmit Descriptor */
  314. uint addr[2];
  315. uint control; /* varies with descriptor type */
  316. uint status; /* varies with descriptor type */
  317. } Tdesc;
  318. enum { /* Tdesc control */
  319. LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
  320. LenSHIFT = 0,
  321. DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
  322. DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
  323. PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
  324. Teop = 0x01000000, /* End of Packet (DD) */
  325. PtypeIP = 0x02000000, /* IP Packet Type (CD) */
  326. Ifcs = 0x02000000, /* Insert FCS (DD) */
  327. Tse = 0x04000000, /* TCP Segmentation Enable */
  328. Rs = 0x08000000, /* Report Status */
  329. Rps = 0x10000000, /* Report Status Sent */
  330. Dext = 0x20000000, /* Descriptor Extension */
  331. Vle = 0x40000000, /* VLAN Packet Enable */
  332. Ide = 0x80000000, /* Interrupt Delay Enable */
  333. };
  334. enum { /* Tdesc status */
  335. Tdd = 0x00000001, /* Descriptor Done */
  336. Ec = 0x00000002, /* Excess Collisions */
  337. Lc = 0x00000004, /* Late Collision */
  338. Tu = 0x00000008, /* Transmit Underrun */
  339. CssMASK = 0x0000FF00, /* Checksum Start Field */
  340. CssSHIFT = 8,
  341. };
  342. enum {
  343. Nrdesc = 128, /* multiple of 8 */
  344. Ntdesc = 128, /* multiple of 8 */
  345. };
  346. typedef struct Ctlr Ctlr;
  347. struct Ctlr {
  348. int port;
  349. Pcidev* pcidev;
  350. Ctlr* next;
  351. int active;
  352. int cls;
  353. ushort eeprom[0x40];
  354. int* nic;
  355. Lock imlock;
  356. int im; /* interrupt mask */
  357. Lock slock;
  358. uint statistics[Nstatistics];
  359. uchar ra[Eaddrlen]; /* receive address */
  360. ulong mta[128]; /* multicast table array */
  361. Rdesc* rdba; /* receive descriptor base address */
  362. Block** rb; /* receive buffers */
  363. int rdh; /* receive descriptor head */
  364. int rdt; /* receive descriptor tail */
  365. Tdesc* tdba; /* transmit descriptor base address */
  366. Lock tdlock;
  367. Block** tb; /* transmit buffers */
  368. int tdh; /* transmit descriptor head */
  369. int tdt; /* transmit descriptor tail */
  370. int txcw;
  371. int fcrtl;
  372. int fcrth;
  373. /* bootstrap goo */
  374. Block* bqhead; /* transmission queue */
  375. Block* bqtail;
  376. };
  377. static Ctlr* ctlrhead;
  378. static Ctlr* ctlrtail;
  379. #define csr32r(c, r) (*((c)->nic+((r)/4)))
  380. #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
  381. static void
  382. i82563im(Ctlr* ctlr, int im)
  383. {
  384. ilock(&ctlr->imlock);
  385. ctlr->im |= im;
  386. csr32w(ctlr, Ims, ctlr->im);
  387. iunlock(&ctlr->imlock);
  388. }
  389. static void
  390. i82563attach(Ether* edev)
  391. {
  392. int ctl;
  393. Ctlr *ctlr;
  394. ctlr = edev->ctlr;
  395. i82563im(ctlr, 0);
  396. ctl = csr32r(ctlr, Rctl)|Ren;
  397. csr32w(ctlr, Rctl, ctl);
  398. ctl = csr32r(ctlr, Tctl)|Ten;
  399. csr32w(ctlr, Tctl, ctl);
  400. }
  401. static void
  402. txstart(Ether *edev)
  403. {
  404. int tdh, tdt, len, olen;
  405. Ctlr *ctlr = edev->ctlr;
  406. Block *bp;
  407. Tdesc *tdesc;
  408. /*
  409. * Try to fill the ring back up, moving buffers from the transmit q.
  410. */
  411. tdh = PREV(ctlr->tdh, Ntdesc);
  412. for(tdt = ctlr->tdt; tdt != tdh; tdt = NEXT(tdt, Ntdesc)){
  413. /* pull off the head of the transmission queue */
  414. if((bp = ctlr->bqhead) == nil) /* was qget(edev->oq) */
  415. break;
  416. ctlr->bqhead = bp->next;
  417. if (ctlr->bqtail == bp)
  418. ctlr->bqtail = nil;
  419. len = olen = BLEN(bp);
  420. /*
  421. * if packet is too short, make it longer rather than relying
  422. * on ethernet interface to pad it and complain so the caller
  423. * will get fixed. I don't think Psp is working right, or it's
  424. * getting cleared.
  425. */
  426. if (len < ETHERMINTU) {
  427. if (bp->rp + ETHERMINTU <= bp->lim)
  428. bp->wp = bp->rp + ETHERMINTU;
  429. else
  430. bp->wp = bp->lim;
  431. len = BLEN(bp);
  432. print("txstart: extended short pkt %d -> %d bytes\n",
  433. olen, len);
  434. }
  435. /* set up a descriptor for it */
  436. tdesc = &ctlr->tdba[tdt];
  437. tdesc->addr[0] = PCIWADDR(bp->rp);
  438. tdesc->addr[1] = 0;
  439. tdesc->control = /* Ide| */ Rs|Dext|Ifcs|Teop|DtypeDD|len;
  440. tdesc->status = 0;
  441. ctlr->tb[tdt] = bp;
  442. }
  443. ctlr->tdt = tdt;
  444. csr32w(ctlr, Tdt, tdt);
  445. i82563im(ctlr, Txdw);
  446. }
  447. static Block *
  448. fromringbuf(Ether *ether)
  449. {
  450. RingBuf *tb = &ether->tb[ether->ti];
  451. Block *bp = allocb(tb->len);
  452. memmove(bp->wp, tb->pkt, tb->len);
  453. memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen);
  454. bp->wp += tb->len;
  455. return bp;
  456. }
  457. static void
  458. i82563transmit(Ether* edev)
  459. {
  460. Block *bp;
  461. Ctlr *ctlr;
  462. Tdesc *tdesc;
  463. RingBuf *tb;
  464. int tdh;
  465. ctlr = edev->ctlr;
  466. ilock(&ctlr->tdlock);
  467. /*
  468. * Free any completed packets
  469. * - try to get the soft tdh to catch the tdt;
  470. * - if the packet had an underrun bump the threshold
  471. * - the Tu bit doesn't seem to ever be set, perhaps
  472. * because Rs mode is used?
  473. */
  474. tdh = ctlr->tdh;
  475. for(;;){
  476. tdesc = &ctlr->tdba[tdh];
  477. if(!(tdesc->status & Tdd))
  478. break;
  479. tdesc->status = 0;
  480. if(ctlr->tb[tdh] != nil){
  481. freeb(ctlr->tb[tdh]);
  482. ctlr->tb[tdh] = nil;
  483. }
  484. tdh = NEXT(tdh, Ntdesc);
  485. }
  486. ctlr->tdh = tdh;
  487. /* copy packets from the software RingBuf to the transmission q */
  488. while((tb = &edev->tb[edev->ti])->owner == Interface){
  489. bp = fromringbuf(edev);
  490. if(ctlr->bqhead)
  491. ctlr->bqtail->next = bp;
  492. else
  493. ctlr->bqhead = bp;
  494. ctlr->bqtail = bp;
  495. txstart(edev); /* kick transmitter */
  496. tb->owner = Host; /* give descriptor back */
  497. edev->ti = NEXT(edev->ti, edev->ntb);
  498. }
  499. iunlock(&ctlr->tdlock);
  500. }
  501. static void
  502. i82563replenish(Ctlr* ctlr)
  503. {
  504. int rdt;
  505. Block *bp;
  506. Rdesc *rdesc;
  507. rdt = ctlr->rdt;
  508. while(NEXT(rdt, Nrdesc) != ctlr->rdh){
  509. rdesc = &ctlr->rdba[rdt];
  510. if(ctlr->rb[rdt] != nil){
  511. /* nothing to do */
  512. }
  513. else if((bp = iallocb(2048)) != nil){
  514. ctlr->rb[rdt] = bp;
  515. rdesc->addr[0] = PCIWADDR(bp->rp);
  516. rdesc->addr[1] = 0;
  517. }
  518. else
  519. break;
  520. rdesc->status = 0;
  521. rdt = NEXT(rdt, Nrdesc);
  522. }
  523. ctlr->rdt = rdt;
  524. csr32w(ctlr, Rdt, rdt);
  525. }
  526. static void
  527. toringbuf(Ether *ether, Block *bp)
  528. {
  529. RingBuf *rb = &ether->rb[ether->ri];
  530. if (rb->owner == Interface) {
  531. rb->len = BLEN(bp);
  532. memmove(rb->pkt, bp->rp, rb->len);
  533. rb->owner = Host;
  534. ether->ri = NEXT(ether->ri, ether->nrb);
  535. }
  536. /* else no one is expecting packets from the network */
  537. }
  538. static void
  539. i82563interrupt(Ureg*, void* arg)
  540. {
  541. Block *bp;
  542. Ctlr *ctlr;
  543. Ether *edev;
  544. Rdesc *rdesc;
  545. int icr, im, rdh, txdw = 0;
  546. edev = arg;
  547. ctlr = edev->ctlr;
  548. ilock(&ctlr->imlock);
  549. csr32w(ctlr, Imc, ~0);
  550. im = ctlr->im;
  551. for(icr = csr32r(ctlr, Icr); icr & ctlr->im; icr = csr32r(ctlr, Icr)){
  552. if(icr & (Rxseq|Lsc)){
  553. }
  554. rdh = ctlr->rdh;
  555. for (;;) {
  556. rdesc = &ctlr->rdba[rdh];
  557. if(!(rdesc->status & Rdd))
  558. break;
  559. if ((rdesc->status & Reop) && rdesc->errors == 0) {
  560. bp = ctlr->rb[rdh];
  561. ctlr->rb[rdh] = nil;
  562. bp->wp += rdesc->length;
  563. toringbuf(edev, bp);
  564. freeb(bp);
  565. } else if ((rdesc->status & Reop) && rdesc->errors)
  566. print("i82563: input packet error 0x%ux\n",
  567. rdesc->errors);
  568. rdesc->status = 0;
  569. rdh = NEXT(rdh, Nrdesc);
  570. }
  571. ctlr->rdh = rdh;
  572. if(icr & Rxdmt0)
  573. i82563replenish(ctlr);
  574. if(icr & Txdw){
  575. im &= ~Txdw;
  576. txdw++;
  577. }
  578. }
  579. ctlr->im = im;
  580. csr32w(ctlr, Ims, im);
  581. iunlock(&ctlr->imlock);
  582. if(txdw)
  583. i82563transmit(edev);
  584. }
  585. static void
  586. i82563init(Ether* edev)
  587. {
  588. int csr, i, r;
  589. Ctlr *ctlr;
  590. ctlr = edev->ctlr;
  591. csr = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
  592. csr32w(ctlr, Ral, csr);
  593. csr = 0x80000000|(edev->ea[5]<<8)|edev->ea[4];
  594. csr32w(ctlr, Rah, csr);
  595. for (i = 1; i < 16; i++) {
  596. csr32w(ctlr, Ral+i*8, 0);
  597. csr32w(ctlr, Rah+i*8, 0);
  598. }
  599. for(i = 0; i < 128; i++)
  600. csr32w(ctlr, Mta+i*4, 0);
  601. csr32w(ctlr, Rctl, 0);
  602. ctlr->rdba = xspanalloc(Nrdesc*sizeof(Rdesc), 128 /* was 16 */, 0);
  603. csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
  604. csr32w(ctlr, Rdbah, 0);
  605. csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc));
  606. ctlr->rdh = 0;
  607. csr32w(ctlr, Rdh, ctlr->rdh);
  608. ctlr->rdt = 0;
  609. csr32w(ctlr, Rdt, ctlr->rdt);
  610. ctlr->rb = malloc(sizeof(Block*)*Nrdesc);
  611. i82563replenish(ctlr);
  612. csr32w(ctlr, Rdtr, 0);
  613. csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam);
  614. i82563im(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
  615. csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(0x3f<<ColdSHIFT)); /* Fd */
  616. csr32w(ctlr, Tipg, (7<<20)|(8<<10)|9);
  617. csr32w(ctlr, Tidv, 1);
  618. ctlr->tdba = xspanalloc(Ntdesc*sizeof(Tdesc), 128 /* was 16 */, 0);
  619. csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
  620. csr32w(ctlr, Tdbah, 0);
  621. csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc));
  622. ctlr->tdh = 0;
  623. csr32w(ctlr, Tdh, ctlr->tdh);
  624. ctlr->tdt = 0;
  625. csr32w(ctlr, Tdt, ctlr->tdt);
  626. ctlr->tb = malloc(sizeof(Block*)*Ntdesc);
  627. r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
  628. csr32w(ctlr, Txdctl, r);
  629. r = csr32r(ctlr, Tctl);
  630. r |= Ten;
  631. csr32w(ctlr, Tctl, r);
  632. }
  633. static ushort
  634. eeread(Ctlr* ctlr, int adr)
  635. {
  636. csr32w(ctlr, Eerd, ee_start | adr << 2);
  637. while ((csr32r(ctlr, Eerd) & ee_done) == 0)
  638. ;
  639. return csr32r(ctlr, Eerd) >> 16;
  640. }
  641. static int
  642. eeload(Ctlr* ctlr)
  643. {
  644. ushort sum;
  645. int data, adr;
  646. sum = 0;
  647. for (adr = 0; adr < 0x40; adr++) {
  648. data = eeread(ctlr, adr);
  649. ctlr->eeprom[adr] = data;
  650. sum += data;
  651. }
  652. return sum;
  653. }
  654. static void
  655. detach(Ctlr *ctlr)
  656. {
  657. csr32w(ctlr, Imc, ~0);
  658. csr32w(ctlr, Rctl, 0);
  659. csr32w(ctlr, Tctl, 0);
  660. delay(10);
  661. csr32w(ctlr, Ctrl, Devrst);
  662. /* apparently needed on multi-GHz processors to avoid infinite loops */
  663. delay(1);
  664. while(csr32r(ctlr, Ctrl) & Devrst)
  665. ;
  666. csr32w(ctlr, Ctrlext, Eerst | csr32r(ctlr, Ctrlext));
  667. delay(1);
  668. while(csr32r(ctlr, Ctrlext) & Eerst)
  669. ;
  670. csr32w(ctlr, Imc, ~0);
  671. delay(1);
  672. while(csr32r(ctlr, Icr))
  673. ;
  674. }
  675. static void
  676. i82563detach(Ether *edev)
  677. {
  678. detach(edev->ctlr);
  679. }
  680. static void
  681. i82563shutdown(Ether* ether)
  682. {
  683. i82563detach(ether);
  684. }
  685. static int
  686. i82563reset(Ctlr* ctlr)
  687. {
  688. int i, r;
  689. detach(ctlr);
  690. r = eeload(ctlr);
  691. if (r != 0 && r != 0xBABA){
  692. print("i82563: bad EEPROM checksum - 0x%4.4uX\n", r);
  693. return -1;
  694. }
  695. for(i = Ea; i < Eaddrlen/2; i++){
  696. ctlr->ra[2*i] = ctlr->eeprom[i];
  697. ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
  698. }
  699. r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
  700. csr32w(ctlr, Ral, r);
  701. r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
  702. csr32w(ctlr, Rah, r);
  703. for(i = 1; i < 16; i++){
  704. csr32w(ctlr, Ral+i*8, 0);
  705. csr32w(ctlr, Rah+i*8, 0);
  706. }
  707. memset(ctlr->mta, 0, sizeof(ctlr->mta));
  708. for(i = 0; i < 128; i++)
  709. csr32w(ctlr, Mta+i*4, 0);
  710. csr32w(ctlr, Fcal, 0x00C28001);
  711. csr32w(ctlr, Fcah, 0x00000100);
  712. csr32w(ctlr, Fct, 0x00008808);
  713. csr32w(ctlr, Fcttv, 0x00000100);
  714. csr32w(ctlr, Fcrtl, ctlr->fcrtl);
  715. csr32w(ctlr, Fcrth, ctlr->fcrth);
  716. ilock(&ctlr->imlock);
  717. csr32w(ctlr, Imc, ~0);
  718. ctlr->im = Lsc;
  719. csr32w(ctlr, Ims, ctlr->im);
  720. iunlock(&ctlr->imlock);
  721. return 0;
  722. }
  723. static void
  724. i82563pci(void)
  725. {
  726. int port, cls;
  727. Pcidev *p;
  728. Ctlr *ctlr;
  729. static int first = 1;
  730. if (first)
  731. first = 0;
  732. else
  733. return;
  734. p = nil;
  735. while(p = pcimatch(p, 0, 0)){
  736. if(p->ccrb != 0x02 || p->ccru != 0)
  737. continue;
  738. if (p->did != 0x1096)
  739. continue;
  740. if (p->vid != 0x8086)
  741. continue;
  742. port = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0);
  743. if(port == 0){
  744. print("i82563: can't map %d @ 0x%8.8luX\n",
  745. p->mem[0].size, p->mem[0].bar);
  746. continue;
  747. }
  748. if(p->pcr & MemWrInv){
  749. cls = pcicfgr8(p, PciCLS) * 4;
  750. if(cls != CACHELINESZ)
  751. pcicfgw8(p, PciCLS, CACHELINESZ/4);
  752. }
  753. cls = pcicfgr8(p, PciCLS);
  754. switch(cls){
  755. default:
  756. print("i82563: unexpected CLS - %d bytes\n",
  757. cls*sizeof(long));
  758. break;
  759. case 0x00:
  760. case 0xFF:
  761. /* alphapc 164lx returns 0 */
  762. print("i82563: unusable PciCLS: %d, using %d longs\n",
  763. cls, CACHELINESZ/sizeof(long));
  764. cls = CACHELINESZ/sizeof(long);
  765. pcicfgw8(p, PciCLS, cls);
  766. break;
  767. case 0x08:
  768. case 0x10:
  769. break;
  770. }
  771. ctlr = malloc(sizeof(Ctlr));
  772. ctlr->port = port;
  773. ctlr->pcidev = p;
  774. ctlr->cls = cls*4;
  775. ctlr->nic = KADDR(ctlr->port);
  776. if(i82563reset(ctlr)){
  777. free(ctlr);
  778. continue;
  779. }
  780. pcisetbme(p);
  781. if(ctlrhead != nil)
  782. ctlrtail->next = ctlr;
  783. else
  784. ctlrhead = ctlr;
  785. ctlrtail = ctlr;
  786. }
  787. }
  788. int
  789. i82563pnp(Ether* edev)
  790. {
  791. int i;
  792. Ctlr *ctlr;
  793. uchar ea[Eaddrlen];
  794. if(ctlrhead == nil)
  795. i82563pci();
  796. /*
  797. * Any adapter matches if no edev->port is supplied,
  798. * otherwise the ports must match.
  799. */
  800. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  801. if(ctlr->active)
  802. continue;
  803. if(edev->port == 0 || edev->port == ctlr->port){
  804. ctlr->active = 1;
  805. break;
  806. }
  807. }
  808. if(ctlr == nil)
  809. return -1;
  810. edev->ctlr = ctlr;
  811. edev->port = ctlr->port;
  812. edev->irq = ctlr->pcidev->intl;
  813. edev->tbdf = ctlr->pcidev->tbdf;
  814. // edev->mbps = 1000;
  815. /*
  816. * Check if the adapter's station address is to be overridden.
  817. * If not, read it from the EEPROM and set in ether->ea prior to
  818. * loading the station address in the hardware.
  819. */
  820. memset(ea, 0, Eaddrlen);
  821. if(memcmp(ea, edev->ea, Eaddrlen) == 0){
  822. for(i = 0; i < Eaddrlen/2; i++){
  823. edev->ea[2*i] = ctlr->eeprom[i];
  824. edev->ea[2*i+1] = ctlr->eeprom[i]>>8;
  825. }
  826. }
  827. i82563init(edev);
  828. /*
  829. * Linkage to the generic ethernet driver.
  830. */
  831. edev->attach = i82563attach;
  832. edev->transmit = i82563transmit;
  833. edev->interrupt = i82563interrupt;
  834. edev->detach = i82563detach;
  835. return 0;
  836. }