amd64.h 7.3 KB

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  1. /*
  2. * This file is part of the UCB release of Plan 9. It is subject to the license
  3. * terms in the LICENSE file found in the top-level directory of this
  4. * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
  5. * part of the UCB release of Plan 9, including this file, may be copied,
  6. * modified, propagated, or distributed except according to the terms contained
  7. * in the LICENSE file.
  8. */
  9. enum { /* Cr0 */
  10. Pe = 0x00000001, /* Protected Mode Enable */
  11. Mp = 0x00000002, /* Monitor Coprocessor */
  12. Em = 0x00000004, /* Emulate Coprocessor */
  13. Ts = 0x00000008, /* Task Switched */
  14. Et = 0x00000010, /* Extension Type */
  15. Ne = 0x00000020, /* Numeric Error */
  16. Wp = 0x00010000, /* Write Protect */
  17. Am = 0x00040000, /* Alignment Mask */
  18. Nw = 0x20000000, /* Not Writethrough */
  19. Cd = 0x40000000, /* Cache Disable */
  20. Pg = 0x80000000, /* Paging Enable */
  21. };
  22. enum { /* Cr3 */
  23. Pwt = 0x00000008, /* Page-Level Writethrough */
  24. Pcd = 0x00000010, /* Page-Level Cache Disable */
  25. };
  26. enum { /* Cr4 */
  27. Vme = 0x00000001, /* Virtual-8086 Mode Extensions */
  28. Pvi = 0x00000002, /* Protected Mode Virtual Interrupts */
  29. Tsd = 0x00000004, /* Time-Stamp Disable */
  30. De = 0x00000008, /* Debugging Extensions */
  31. Pse = 0x00000010, /* Page-Size Extensions */
  32. Pae = 0x00000020, /* Physical Address Extension */
  33. Mce = 0x00000040, /* Machine Check Enable */
  34. Pge = 0x00000080, /* Page-Global Enable */
  35. Pce = 0x00000100, /* Performance Monitoring Counter Enable */
  36. Osfxsr = 0x00000200, /* FXSAVE/FXRSTOR Support */
  37. Osxmmexcpt = 0x00000400, /* Unmasked Exception Support */
  38. };
  39. enum { /* Rflags */
  40. Cf = 0x00000001, /* Carry Flag */
  41. Pf = 0x00000004, /* Parity Flag */
  42. Af = 0x00000010, /* Auxiliary Flag */
  43. Zf = 0x00000040, /* Zero Flag */
  44. Sf = 0x00000080, /* Sign Flag */
  45. Tf = 0x00000100, /* Trap Flag */
  46. If = 0x00000200, /* Interrupt Flag */
  47. Df = 0x00000400, /* Direction Flag */
  48. Of = 0x00000800, /* Overflow Flag */
  49. Iopl0 = 0x00000000, /* I/O Privilege Level */
  50. Iopl1 = 0x00001000,
  51. Iopl2 = 0x00002000,
  52. Iopl3 = 0x00003000,
  53. Nt = 0x00004000, /* Nested Task */
  54. Rf = 0x00010000, /* Resume Flag */
  55. Vm = 0x00020000, /* Virtual-8086 Mode */
  56. Ac = 0x00040000, /* Alignment Check */
  57. Vif = 0x00080000, /* Virtual Interrupt Flag */
  58. Vip = 0x00100000, /* Virtual Interrupt Pending */
  59. Id = 0x00200000, /* ID Flag */
  60. };
  61. enum { /* MSRs */
  62. PerfEvtbase = 0xc0010000, /* Performance Event Select */
  63. PerfCtrbase = 0xc0010004, /* Performance Counters */
  64. Efer = 0xc0000080, /* Extended Feature Enable */
  65. Star = 0xc0000081, /* Legacy Target IP and [CS]S */
  66. Lstar = 0xc0000082, /* Long Mode Target IP */
  67. Cstar = 0xc0000083, /* Compatibility Target IP */
  68. Sfmask = 0xc0000084, /* SYSCALL Flags Mask */
  69. FSbase = 0xc0000100, /* 64-bit FS Base Address */
  70. GSbase = 0xc0000101, /* 64-bit GS Base Address */
  71. KernelGSbase = 0xc0000102, /* SWAPGS instruction */
  72. };
  73. enum { /* Efer */
  74. Sce = 0x00000001, /* System Call Extension */
  75. Lme = 0x00000100, /* Long Mode Enable */
  76. Lma = 0x00000400, /* Long Mode Active */
  77. Nxe = 0x00000800, /* No-Execute Enable */
  78. Svme = 0x00001000, /* SVM Extension Enable */
  79. Ffxsr = 0x00004000, /* Fast FXSAVE/FXRSTOR */
  80. };
  81. enum { /* PML4E/PDPE/PDE/PTE */
  82. PteP = 0x0000000000000001ull,/* Present */
  83. PteRW = 0x0000000000000002ull,/* Read/Write */
  84. PteU = 0x0000000000000004ull,/* User/Supervisor */
  85. PtePWT = 0x0000000000000008ull,/* Page-Level Write Through */
  86. PtePCD = 0x0000000000000010ull,/* Page Level Cache Disable */
  87. PteA = 0x0000000000000020ull,/* Accessed */
  88. PteD = 0x0000000000000040ull,/* Dirty */
  89. PtePS = 0x0000000000000080ull,/* Page Size */
  90. Pte4KPAT = PtePS, /* PTE PAT */
  91. PteG = 0x0000000000000100ull,/* Global */
  92. Pte2MPAT = 0x0000000000001000ull,/* PDE PAT */
  93. Pte1GPAT = Pte2MPAT, /* PDPE PAT */
  94. PteNX = 0x8000000000000000ull,/* No Execute */
  95. };
  96. enum { /* Exceptions */
  97. IdtDE = 0, /* Divide-by-Zero Error */
  98. IdtDB = 1, /* Debug */
  99. IdtNMI = 2, /* Non-Maskable-Interrupt */
  100. IdtBP = 3, /* Breakpoint */
  101. IdtOF = 4, /* Overflow */
  102. IdtBR = 5, /* Bound-Range */
  103. IdtUD = 6, /* Invalid-Opcode */
  104. IdtNM = 7, /* Device-Not-Available */
  105. IdtDF = 8, /* Double-Fault */
  106. Idt09 = 9, /* unsupported */
  107. IdtTS = 10, /* Invalid-TSS */
  108. IdtNP = 11, /* Segment-Not-Present */
  109. IdtSS = 12, /* Stack */
  110. IdtGP = 13, /* General-Protection */
  111. IdtPF = 14, /* Page-Fault */
  112. Idt0F = 15, /* reserved */
  113. IdtMF = 16, /* x87 FPE-Pending */
  114. IdtAC = 17, /* Alignment-Check */
  115. IdtMC = 18, /* Machine-Check */
  116. IdtXF = 19, /* SIMD Floating-Point */
  117. };
  118. /*
  119. * Vestigial Segmented Virtual Memory.
  120. */
  121. enum { /* Segment Descriptor */
  122. SdISTM = 0x0000000700000000ull,/* Interrupt Stack Table Mask */
  123. SdA = 0x0000010000000000ull,/* Accessed */
  124. SdR = 0x0000020000000000ull,/* Readable (Code) */
  125. SdW = 0x0000020000000000ull,/* Writeable (Data) */
  126. SdE = 0x0000040000000000ull,/* Expand Down */
  127. SdaTSS = 0x0000090000000000ull,/* Available TSS */
  128. SdbTSS = 0x00000b0000000000ull,/* Busy TSS */
  129. SdCG = 0x00000c0000000000ull,/* Call Gate */
  130. SdIG = 0x00000e0000000000ull,/* Interrupt Gate */
  131. SdTG = 0x00000f0000000000ull,/* Trap Gate */
  132. SdCODE = 0x0000080000000000ull,/* Code/Data */
  133. SdS = 0x0000100000000000ull,/* System/User */
  134. SdDPL0 = 0x0000000000000000ull,/* Descriptor Privilege Level */
  135. SdDPL1 = 0x0000200000000000ull,
  136. SdDPL2 = 0x0000400000000000ull,
  137. SdDPL3 = 0x0000600000000000ull,
  138. SdP = 0x0000800000000000ull,/* Present */
  139. Sd4G = 0x000f00000000ffffull,/* 4G Limit */
  140. SdL = 0x0020000000000000ull,/* Long Attribute */
  141. SdD = 0x0040000000000000ull,/* Default Operand Size */
  142. SdG = 0x0080000000000000ull,/* Granularity */
  143. };
  144. /*
  145. * Performance Counter Configuration
  146. */
  147. enum { /* Performance Event Selector */
  148. PeHo = 0x0000020000000000ull,/* Host only */
  149. PeGo = 0x0000010000000000ull,/* Guest only */
  150. PeEvMskH = 0x0000000f00000000ull,/* Event mask H */
  151. PeCtMsk = 0x00000000ff000000ull,/* Counter mask */
  152. PeInMsk = 0x0000000000800000ull,/* Invert mask */
  153. PeCtEna = 0x0000000000400000ull,/* Counter enable */
  154. PeInEna = 0x0000000000100000ull,/* Interrupt enable */
  155. PePnCtl = 0x0000000000080000ull,/* Pin control */
  156. PeEdg = 0x0000000000040000ull,/* Edge detect */
  157. PeOS = 0x0000000000020000ull,/* OS mode */
  158. PeUsr = 0x0000000000010000ull,/* User mode */
  159. PeUnMsk = 0x000000000000ff00ull,/* Unit Mask */
  160. PeEvMskL = 0x00000000000000ffull,/* Event Mask L */
  161. PeEvMsksh = 32ull, /* Event mask shift */
  162. };
  163. enum { /* Segment Selector */
  164. SsRPL0 = 0x0000, /* Requestor Privilege Level */
  165. SsRPL1 = 0x0001,
  166. SsRPL2 = 0x0002,
  167. SsRPL3 = 0x0003,
  168. SsTIGDT = 0x0000, /* GDT Table Indicator */
  169. SsTILDT = 0x0004, /* LDT Table Indicator */
  170. SsSIM = 0xfff8, /* Selector Index Mask */
  171. };
  172. #define SSEL(si, tirpl) (((si)<<3)|(tirpl)) /* Segment Selector */
  173. enum {
  174. SiNULL = 0, /* NULL selector index */
  175. SiCS = 1, /* CS selector index */
  176. SiDS = 2, /* DS selector index */
  177. SiU32CS = 3, /* User CS selector index */
  178. SiUDS = 4, /* User DS selector index */
  179. SiUCS = 5, /* User CS selector index */
  180. SiFS = 6, /* FS selector index */
  181. SiGS = 7, /* GS selector index */
  182. SiTSS = 8, /* TSS selector index */
  183. };
  184. /*
  185. * Extern registers.
  186. */
  187. #define RMACH R15 /* m-> */
  188. #define RUSER R14 /* up-> */