ether8139.c 21 KB

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  1. /*
  2. * This file is part of the UCB release of Plan 9. It is subject to the license
  3. * terms in the LICENSE file found in the top-level directory of this
  4. * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
  5. * part of the UCB release of Plan 9, including this file, may be copied,
  6. * modified, propagated, or distributed except according to the terms contained
  7. * in the LICENSE file.
  8. */
  9. /*
  10. * Realtek 8139 (but not the 8129).
  11. * Error recovery for the various over/under -flow conditions
  12. * may need work.
  13. */
  14. #include "u.h"
  15. #include "../port/lib.h"
  16. #include "mem.h"
  17. #include "dat.h"
  18. #include "fns.h"
  19. #include "io.h"
  20. #include "../port/error.h"
  21. #include "../port/netif.h"
  22. #include "etherif.h"
  23. enum { /* registers */
  24. Idr0 = 0x0000, /* MAC address */
  25. Mar0 = 0x0008, /* Multicast address */
  26. Tsd0 = 0x0010, /* Transmit Status Descriptor0 */
  27. Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
  28. Rbstart = 0x0030, /* Receive Buffer Start Address */
  29. Erbcr = 0x0034, /* Early Receive Byte Count */
  30. Ersr = 0x0036, /* Early Receive Status */
  31. Cr = 0x0037, /* Command Register */
  32. Capr = 0x0038, /* Current Address of Packet Read */
  33. Cbr = 0x003A, /* Current Buffer Address */
  34. Imr = 0x003C, /* Interrupt Mask */
  35. Isr = 0x003E, /* Interrupt Status */
  36. Tcr = 0x0040, /* Transmit Configuration */
  37. Rcr = 0x0044, /* Receive Configuration */
  38. Tctr = 0x0048, /* Timer Count */
  39. Mpc = 0x004C, /* Missed Packet Counter */
  40. Cr9346 = 0x0050, /* 9346 Command Register */
  41. Config0 = 0x0051, /* Configuration Register 0 */
  42. Config1 = 0x0052, /* Configuration Register 1 */
  43. TimerInt = 0x0054, /* Timer Interrupt */
  44. Msr = 0x0058, /* Media Status */
  45. Config3 = 0x0059, /* Configuration Register 3 */
  46. Config4 = 0x005A, /* Configuration Register 4 */
  47. Mulint = 0x005C, /* Multiple Interrupt Select */
  48. RerID = 0x005E, /* PCI Revision ID */
  49. Tsad = 0x0060, /* Transmit Status of all Descriptors */
  50. Bmcr = 0x0062, /* Basic Mode Control */
  51. Bmsr = 0x0064, /* Basic Mode Status */
  52. Anar = 0x0066, /* Auto-Negotiation Advertisment */
  53. Anlpar = 0x0068, /* Auto-Negotiation Link Partner */
  54. Aner = 0x006A, /* Auto-Negotiation Expansion */
  55. Dis = 0x006C, /* Disconnect Counter */
  56. Fcsc = 0x006E, /* False Carrier Sense Counter */
  57. Nwaytr = 0x0070, /* N-way Test */
  58. Rec = 0x0072, /* RX_ER Counter */
  59. Cscr = 0x0074, /* CS Configuration */
  60. Phy1parm = 0x0078, /* PHY Parameter 1 */
  61. Twparm = 0x007C, /* Twister Parameter */
  62. Phy2parm = 0x0080, /* PHY Parameter 2 */
  63. };
  64. enum { /* Cr */
  65. Bufe = 0x01, /* Rx Buffer Empty */
  66. Te = 0x04, /* Transmitter Enable */
  67. Re = 0x08, /* Receiver Enable */
  68. Rst = 0x10, /* Software Reset */
  69. };
  70. enum { /* Imr/Isr */
  71. Rok = 0x0001, /* Receive OK */
  72. Rer = 0x0002, /* Receive Error */
  73. Tok = 0x0004, /* Transmit OK */
  74. Ter = 0x0008, /* Transmit Error */
  75. Rxovw = 0x0010, /* Receive Buffer Overflow */
  76. PunLc = 0x0020, /* Packet Underrun or Link Change */
  77. Fovw = 0x0040, /* Receive FIFO Overflow */
  78. Clc = 0x2000, /* Cable Length Change */
  79. Timerbit = 0x4000, /* Timer */
  80. Serr = 0x8000, /* System Error */
  81. };
  82. enum { /* Tcr */
  83. Clrabt = 0x00000001, /* Clear Abort */
  84. TxrrSHIFT = 4, /* Transmit Retry Count */
  85. TxrrMASK = 0x000000F0,
  86. MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
  87. MtxdmaMASK = 0x00000700,
  88. Mtxdma2048 = 0x00000700,
  89. Acrc = 0x00010000, /* Append CRC (not) */
  90. LbkSHIFT = 17, /* Loopback Test */
  91. LbkMASK = 0x00060000,
  92. Rtl8139ArevG = 0x00800000, /* RTL8139A Rev. G ID */
  93. IfgSHIFT = 24, /* Interframe Gap */
  94. IfgMASK = 0x03000000,
  95. HwveridSHIFT = 26, /* Hardware Version ID */
  96. HwveridMASK = 0x7C000000,
  97. };
  98. enum { /* Rcr */
  99. Aap = 0x00000001, /* Accept All Packets */
  100. Apm = 0x00000002, /* Accept Physical Match */
  101. Am = 0x00000004, /* Accept Multicast */
  102. Ab = 0x00000008, /* Accept Broadcast */
  103. Ar = 0x00000010, /* Accept Runt */
  104. Aer = 0x00000020, /* Accept Error */
  105. Sel9356 = 0x00000040, /* 9356 EEPROM used */
  106. Wrap = 0x00000080, /* Rx Buffer Wrap Control */
  107. MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
  108. MrxdmaMASK = 0x00000700,
  109. Mrxdmaunlimited = 0x00000700,
  110. RblenSHIFT = 11, /* Receive Buffer Length */
  111. RblenMASK = 0x00001800,
  112. Rblen8K = 0x00000000, /* 8KB+16 */
  113. Rblen16K = 0x00000800, /* 16KB+16 */
  114. Rblen32K = 0x00001000, /* 32KB+16 */
  115. Rblen64K = 0x00001800, /* 64KB+16 */
  116. RxfthSHIFT = 13, /* Receive Buffer Length */
  117. RxfthMASK = 0x0000E000,
  118. Rxfth256 = 0x00008000,
  119. Rxfthnone = 0x0000E000,
  120. Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
  121. MulERINT = 0x00020000, /* Multiple Early Interrupt Select */
  122. ErxthSHIFT = 24, /* Early Rx Threshold */
  123. ErxthMASK = 0x0F000000,
  124. Erxthnone = 0x00000000,
  125. };
  126. enum { /* Received Packet Status */
  127. Rcok = 0x0001, /* Receive Completed OK */
  128. Fae = 0x0002, /* Frame Alignment Error */
  129. Crc = 0x0004, /* CRC Error */
  130. Long = 0x0008, /* Long Packet */
  131. Runt = 0x0010, /* Runt Packet Received */
  132. Ise = 0x0020, /* Invalid Symbol Error */
  133. Bar = 0x2000, /* Broadcast Address Received */
  134. Pam = 0x4000, /* Physical Address Matched */
  135. Mar = 0x8000, /* Multicast Address Received */
  136. };
  137. enum { /* Media Status Register */
  138. Rxpf = 0x01, /* Pause Flag */
  139. Txpf = 0x02, /* Pause Flag */
  140. Linkb = 0x04, /* Inverse of Link Status */
  141. Speed10 = 0x08, /* 10Mbps */
  142. Auxstatus = 0x10, /* Aux. Power Present Status */
  143. Rxfce = 0x40, /* Receive Flow Control Enable */
  144. Txfce = 0x80, /* Transmit Flow Control Enable */
  145. };
  146. typedef struct Td Td;
  147. struct Td { /* Soft Transmit Descriptor */
  148. int tsd;
  149. int tsad;
  150. unsigned char* data;
  151. Block* bp;
  152. };
  153. enum { /* Tsd0 */
  154. SizeSHIFT = 0, /* Descriptor Size */
  155. SizeMASK = 0x00001FFF,
  156. Own = 0x00002000,
  157. Tun = 0x00004000, /* Transmit FIFO Underrun */
  158. Tcok = 0x00008000, /* Transmit COmpleted OK */
  159. EtxthSHIFT = 16, /* Early Tx Threshold */
  160. EtxthMASK = 0x001F0000,
  161. NccSHIFT = 24, /* Number of Collisions Count */
  162. NccMASK = 0x0F000000,
  163. Cdh = 0x10000000, /* CD Heartbeat */
  164. Owc = 0x20000000, /* Out of Window Collision */
  165. Tabt = 0x40000000, /* Transmit Abort */
  166. Crs = 0x80000000, /* Carrier Sense Lost */
  167. };
  168. enum {
  169. Rblen = Rblen64K, /* Receive Buffer Length */
  170. Ntd = 4, /* Number of Transmit Descriptors */
  171. Tdbsz = ROUNDUP(sizeof(Etherpkt), 4),
  172. };
  173. typedef struct Ctlr Ctlr;
  174. typedef struct Ctlr {
  175. int port;
  176. Pcidev* pcidev;
  177. Ctlr* next;
  178. int active;
  179. int id;
  180. QLock alock; /* attach */
  181. Lock ilock; /* init */
  182. void* alloc; /* base of per-Ctlr allocated data */
  183. int pcie; /* flag: pci-express device? */
  184. uint64_t mchash; /* multicast hash */
  185. int rcr; /* receive configuration register */
  186. unsigned char* rbstart; /* receive buffer */
  187. int rblen; /* receive buffer length */
  188. int ierrs; /* receive errors */
  189. Lock tlock; /* transmit */
  190. Td td[Ntd];
  191. int ntd; /* descriptors active */
  192. int tdh; /* host index into td */
  193. int tdi; /* interface index into td */
  194. int etxth; /* early transmit threshold */
  195. int taligned; /* packet required no alignment */
  196. int tunaligned; /* packet required alignment */
  197. int dis; /* disconnect counter */
  198. int fcsc; /* false carrier sense counter */
  199. int rec; /* RX_ER counter */
  200. uint mcast;
  201. } Ctlr;
  202. static Ctlr* ctlrhead;
  203. static Ctlr* ctlrtail;
  204. #define csr8r(c, r) (inb((c)->port+(r)))
  205. #define csr16r(c, r) (ins((c)->port+(r)))
  206. #define csr32r(c, r) (inl((c)->port+(r)))
  207. #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
  208. #define csr16w(c, r, w) (outs((c)->port+(r), (uint16_t)(w)))
  209. #define csr32w(c, r, l) (outl((c)->port+(r), (uint32_t)(l)))
  210. static void
  211. rtl8139promiscuous(void* arg, int on)
  212. {
  213. Ether *edev;
  214. Ctlr * ctlr;
  215. edev = arg;
  216. ctlr = edev->ctlr;
  217. ilock(&ctlr->ilock);
  218. if(on)
  219. ctlr->rcr |= Aap;
  220. else
  221. ctlr->rcr &= ~Aap;
  222. csr32w(ctlr, Rcr, ctlr->rcr);
  223. iunlock(&ctlr->ilock);
  224. }
  225. enum {
  226. /* everyone else uses 0x04c11db7, but they both produce the same crc */
  227. Etherpolybe = 0x04c11db6,
  228. Bytemask = (1<<8) - 1,
  229. };
  230. static uint32_t
  231. ethercrcbe(unsigned char *addr, int32_t len)
  232. {
  233. int i, j;
  234. uint64_t c, crc, carry;
  235. crc = ~0UL;
  236. for (i = 0; i < len; i++) {
  237. c = addr[i];
  238. for (j = 0; j < 8; j++) {
  239. carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
  240. crc <<= 1;
  241. c >>= 1;
  242. if (carry)
  243. crc = (crc ^ Etherpolybe) | carry;
  244. }
  245. }
  246. return crc;
  247. }
  248. static uint32_t
  249. swabl(uint32_t l)
  250. {
  251. return l>>24 | (l>>8) & (Bytemask<<8) |
  252. (l<<8) & (Bytemask<<16) | l<<24;
  253. }
  254. static void
  255. rtl8139multicast(void* ether, unsigned char *eaddr, int add)
  256. {
  257. Ether *edev;
  258. Ctlr *ctlr;
  259. if (!add)
  260. return; /* ok to keep receiving on old mcast addrs */
  261. edev = ether;
  262. ctlr = edev->ctlr;
  263. ilock(&ctlr->ilock);
  264. ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
  265. ctlr->rcr |= Am;
  266. csr32w(ctlr, Rcr, ctlr->rcr);
  267. /* pci-e variants reverse the order of the hash byte registers */
  268. if (0 && ctlr->pcie) {
  269. csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
  270. csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
  271. } else {
  272. csr32w(ctlr, Mar0, ctlr->mchash);
  273. csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
  274. }
  275. iunlock(&ctlr->ilock);
  276. }
  277. static int32_t
  278. rtl8139ifstat(Ether* edev, void* a, int32_t n, uint32_t offset)
  279. {
  280. int l;
  281. char *p;
  282. Ctlr *ctlr;
  283. ctlr = edev->ctlr;
  284. p = malloc(READSTR);
  285. if(p == nil)
  286. error(Enomem);
  287. l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr);
  288. l += snprint(p+l, READSTR-l, "multicast %ud\n", ctlr->mcast);
  289. l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
  290. l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
  291. l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
  292. l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
  293. ctlr->dis += csr16r(ctlr, Dis);
  294. l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis);
  295. ctlr->fcsc += csr16r(ctlr, Fcsc);
  296. l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
  297. ctlr->rec += csr16r(ctlr, Rec);
  298. l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec);
  299. l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr));
  300. l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0));
  301. l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1));
  302. l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr));
  303. l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3));
  304. l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4));
  305. l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr));
  306. l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr));
  307. l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar));
  308. l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar));
  309. l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner));
  310. l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr));
  311. snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr));
  312. n = readstr(offset, a, n, p);
  313. free(p);
  314. return n;
  315. }
  316. static int
  317. rtl8139reset(Ctlr* ctlr)
  318. {
  319. int timeo;
  320. /* stop interrupts */
  321. csr16w(ctlr, Imr, 0);
  322. csr16w(ctlr, Isr, ~0);
  323. csr32w(ctlr, TimerInt, 0);
  324. /*
  325. * Soft reset the controller.
  326. */
  327. csr8w(ctlr, Cr, Rst);
  328. for(timeo = 0; timeo < 1000; timeo++){
  329. if(!(csr8r(ctlr, Cr) & Rst))
  330. return 0;
  331. delay(1);
  332. }
  333. return -1;
  334. }
  335. static void
  336. rtl8139halt(Ctlr* ctlr)
  337. {
  338. int i;
  339. csr8w(ctlr, Cr, 0);
  340. csr16w(ctlr, Imr, 0);
  341. csr16w(ctlr, Isr, ~0);
  342. csr32w(ctlr, TimerInt, 0);
  343. for(i = 0; i < Ntd; i++){
  344. if(ctlr->td[i].bp == nil)
  345. continue;
  346. freeb(ctlr->td[i].bp);
  347. ctlr->td[i].bp = nil;
  348. }
  349. }
  350. static void
  351. rtl8139shutdown(Ether *edev)
  352. {
  353. Ctlr *ctlr;
  354. ctlr = edev->ctlr;
  355. ilock(&ctlr->ilock);
  356. rtl8139halt(ctlr);
  357. rtl8139reset(ctlr);
  358. iunlock(&ctlr->ilock);
  359. }
  360. static void
  361. rtl8139init(Ether* edev)
  362. {
  363. int i;
  364. uint32_t r;
  365. Ctlr *ctlr;
  366. unsigned char *alloc;
  367. ctlr = edev->ctlr;
  368. ilock(&ctlr->ilock);
  369. rtl8139halt(ctlr);
  370. /*
  371. * MAC Address.
  372. */
  373. r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
  374. csr32w(ctlr, Idr0, r);
  375. r = (edev->ea[5]<<8)|edev->ea[4];
  376. csr32w(ctlr, Idr0+4, r);
  377. /*
  378. * Receiver
  379. */
  380. alloc = (unsigned char*)ROUNDUP((uint64_t)ctlr->alloc, 32);
  381. ctlr->rbstart = alloc;
  382. alloc += ctlr->rblen+16;
  383. memset(ctlr->rbstart, 0, ctlr->rblen+16);
  384. csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
  385. ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Am|Apm;
  386. /*
  387. * Transmitter.
  388. */
  389. for(i = 0; i < Ntd; i++){
  390. ctlr->td[i].tsd = Tsd0+i*4;
  391. ctlr->td[i].tsad = Tsad0+i*4;
  392. ctlr->td[i].data = alloc;
  393. alloc += Tdbsz;
  394. ctlr->td[i].bp = nil;
  395. }
  396. ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
  397. ctlr->etxth = 128/32;
  398. /*
  399. * Enable receiver/transmitter.
  400. * Need to enable before writing the Rcr or it won't take.
  401. */
  402. csr8w(ctlr, Cr, Te|Re);
  403. csr32w(ctlr, Tcr, Mtxdma2048);
  404. csr32w(ctlr, Rcr, ctlr->rcr);
  405. csr32w(ctlr, Mar0, 0);
  406. csr32w(ctlr, Mar0+4, 0);
  407. ctlr->mchash = 0;
  408. /*
  409. * Interrupts.
  410. */
  411. csr32w(ctlr, TimerInt, 0);
  412. csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
  413. csr32w(ctlr, Mpc, 0);
  414. iunlock(&ctlr->ilock);
  415. }
  416. static void
  417. rtl8139attach(Ether* edev)
  418. {
  419. Ctlr *ctlr;
  420. if(edev == nil) {
  421. print("rtl8139attach: nil edev\n");
  422. return;
  423. }
  424. ctlr = edev->ctlr;
  425. if(ctlr == nil) {
  426. print("rtl8139attach: nil ctlr for Ether %#p\n", edev);
  427. return;
  428. }
  429. qlock(&ctlr->alock);
  430. if(ctlr->alloc == nil){
  431. ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
  432. ctlr->alloc = malloc(ctlr->rblen+16 + Ntd*Tdbsz + 32);
  433. if(ctlr->alloc == nil) {
  434. qunlock(&ctlr->alock);
  435. error(Enomem);
  436. }
  437. rtl8139init(edev);
  438. }
  439. qunlock(&ctlr->alock);
  440. }
  441. static void
  442. rtl8139txstart(Ether* edev)
  443. {
  444. Td *td;
  445. int size;
  446. Block *bp;
  447. Ctlr *ctlr;
  448. ctlr = edev->ctlr;
  449. while(ctlr->ntd < Ntd){
  450. bp = qget(edev->oq);
  451. if(bp == nil)
  452. break;
  453. size = BLEN(bp);
  454. td = &ctlr->td[ctlr->tdh];
  455. if(((int64_t)bp->rp) & 0x03){
  456. memmove(td->data, bp->rp, size);
  457. freeb(bp);
  458. csr32w(ctlr, td->tsad, PCIWADDR(td->data));
  459. ctlr->tunaligned++;
  460. }
  461. else{
  462. td->bp = bp;
  463. csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
  464. ctlr->taligned++;
  465. }
  466. csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
  467. ctlr->ntd++;
  468. ctlr->tdh = NEXT(ctlr->tdh, Ntd);
  469. }
  470. }
  471. static void
  472. rtl8139transmit(Ether* edev)
  473. {
  474. Ctlr *ctlr;
  475. ctlr = edev->ctlr;
  476. ilock(&ctlr->tlock);
  477. rtl8139txstart(edev);
  478. iunlock(&ctlr->tlock);
  479. }
  480. static void
  481. rtl8139receive(Ether* edev)
  482. {
  483. Block *bp;
  484. Ctlr *ctlr;
  485. uint16_t capr;
  486. unsigned char cr, *p;
  487. int l, length, status;
  488. ctlr = edev->ctlr;
  489. /*
  490. * Capr is where the host is reading from,
  491. * Cbr is where the NIC is currently writing.
  492. */
  493. if(ctlr->rblen == 0)
  494. return; /* not attached yet (shouldn't happen) */
  495. capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
  496. while(!(csr8r(ctlr, Cr) & Bufe)){
  497. p = ctlr->rbstart+capr;
  498. /*
  499. * Apparently the packet length may be 0xFFF0 if
  500. * the NIC is still copying the packet into memory.
  501. */
  502. length = (*(p+3)<<8)|*(p+2);
  503. if(length == 0xFFF0)
  504. break;
  505. status = (*(p+1)<<8)|*p;
  506. if(!(status & Rcok)){
  507. if(status & (Ise|Fae))
  508. edev->frames++;
  509. if(status & Crc)
  510. edev->crcs++;
  511. if(status & (Runt|Long))
  512. edev->buffs++;
  513. /*
  514. * Reset the receiver.
  515. * Also may have to restore the multicast list
  516. * here too if it ever gets used.
  517. */
  518. cr = csr8r(ctlr, Cr);
  519. csr8w(ctlr, Cr, cr & ~Re);
  520. csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
  521. csr8w(ctlr, Cr, cr);
  522. csr32w(ctlr, Rcr, ctlr->rcr);
  523. continue;
  524. }
  525. /*
  526. * Receive Completed OK.
  527. * Very simplistic; there are ways this could be done
  528. * without copying, but the juice probably isn't worth
  529. * the squeeze.
  530. * The packet length includes a 4 byte CRC on the end.
  531. */
  532. capr = (capr+4) % ctlr->rblen;
  533. p = ctlr->rbstart+capr;
  534. capr = (capr+length) % ctlr->rblen;
  535. if(status & Mar)
  536. ctlr->mcast++;
  537. if((bp = iallocb(length)) != nil){
  538. if(p+length >= ctlr->rbstart+ctlr->rblen){
  539. l = ctlr->rbstart+ctlr->rblen - p;
  540. memmove(bp->wp, p, l);
  541. bp->wp += l;
  542. length -= l;
  543. p = ctlr->rbstart;
  544. }
  545. if(length > 0){
  546. memmove(bp->wp, p, length);
  547. bp->wp += length;
  548. }
  549. bp->wp -= 4;
  550. etheriq(edev, bp, 1);
  551. }
  552. capr = ROUNDUP(capr, 4);
  553. csr16w(ctlr, Capr, capr-16);
  554. }
  555. }
  556. static void
  557. rtl8139interrupt(Ureg *ureg, void* arg)
  558. {
  559. Td *td;
  560. Ctlr *ctlr;
  561. Ether *edev;
  562. int isr, msr, tsd;
  563. edev = arg;
  564. ctlr = edev->ctlr;
  565. if(ctlr == nil) { /* not attached yet? (shouldn't happen) */
  566. print("rtl8139interrupt: interrupt for unattached Ether %#p\n",
  567. edev);
  568. return;
  569. }
  570. while((isr = csr16r(ctlr, Isr)) != 0){
  571. csr16w(ctlr, Isr, isr);
  572. if(ctlr->alloc == nil) {
  573. print("rtl8139interrupt: interrupt for unattached Ctlr "
  574. "%#p port %#p\n", ctlr, (void *)(int64_t)ctlr->port);
  575. return; /* not attached yet (shouldn't happen) */
  576. }
  577. if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
  578. rtl8139receive(edev);
  579. if(!(isr & Rok))
  580. ctlr->ierrs++;
  581. isr &= ~(Fovw|Rxovw|Rer|Rok);
  582. }
  583. if(isr & (Ter|Tok)){
  584. ilock(&ctlr->tlock);
  585. while(ctlr->ntd){
  586. td = &ctlr->td[ctlr->tdi];
  587. tsd = csr32r(ctlr, td->tsd);
  588. if(!(tsd & (Tabt|Tun|Tcok)))
  589. break;
  590. if(!(tsd & Tcok)){
  591. if(tsd & Tun){
  592. if(ctlr->etxth < ETHERMAXTU/32)
  593. ctlr->etxth++;
  594. }
  595. edev->oerrs++;
  596. }
  597. if(td->bp != nil){
  598. freeb(td->bp);
  599. td->bp = nil;
  600. }
  601. ctlr->ntd--;
  602. ctlr->tdi = NEXT(ctlr->tdi, Ntd);
  603. }
  604. rtl8139txstart(edev);
  605. iunlock(&ctlr->tlock);
  606. isr &= ~(Ter|Tok);
  607. }
  608. if(isr & PunLc){
  609. /*
  610. * Maybe the link changed - do we care very much?
  611. */
  612. msr = csr8r(ctlr, Msr);
  613. if(!(msr & Linkb)){
  614. if(!(msr & Speed10) && edev->mbps != 100){
  615. edev->mbps = 100;
  616. qsetlimit(edev->oq, 256*1024);
  617. }
  618. else if((msr & Speed10) && edev->mbps != 10){
  619. edev->mbps = 10;
  620. qsetlimit(edev->oq, 65*1024);
  621. }
  622. }
  623. isr &= ~(Clc|PunLc);
  624. }
  625. /*
  626. * Only Serr|Timerbit should be left by now.
  627. * Should anything be done to tidy up? TimerInt isn't
  628. * used so that can be cleared. A PCI bus error is indicated
  629. * by Serr, that's pretty serious; is there anyhing to do
  630. * other than try to reinitialise the chip?
  631. */
  632. if((isr & (Serr|Timerbit)) != 0){
  633. iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n",
  634. csr16r(ctlr, Imr), isr);
  635. if(isr & Timerbit)
  636. csr32w(ctlr, TimerInt, 0);
  637. if(isr & Serr)
  638. rtl8139init(edev);
  639. }
  640. }
  641. }
  642. static Ctlr*
  643. rtl8139match(Ether* edev, int id)
  644. {
  645. Pcidev *p;
  646. Ctlr *ctlr;
  647. int i, port;
  648. /*
  649. * Any adapter matches if no edev->port is supplied,
  650. * otherwise the ports must match.
  651. */
  652. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  653. if(ctlr->active)
  654. continue;
  655. p = ctlr->pcidev;
  656. if(((p->did<<16)|p->vid) != id)
  657. continue;
  658. port = p->mem[0].bar & ~0x01;
  659. if(edev->port != 0 && edev->port != port)
  660. continue;
  661. if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){
  662. print("rtl8139: port %#ux in use\n", port);
  663. continue;
  664. }
  665. if(pcigetpms(p) > 0){
  666. pcisetpms(p, 0);
  667. for(i = 0; i < 6; i++)
  668. pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
  669. pcicfgw8(p, PciINTL, p->intl);
  670. pcicfgw8(p, PciLTR, p->ltr);
  671. pcicfgw8(p, PciCLS, p->cls);
  672. pcicfgw16(p, PciPCR, p->pcr);
  673. }
  674. ctlr->port = port;
  675. if(rtl8139reset(ctlr)) {
  676. iofree(port);
  677. continue;
  678. }
  679. pcisetbme(p);
  680. ctlr->active = 1;
  681. return ctlr;
  682. }
  683. return nil;
  684. }
  685. static struct {
  686. char* name;
  687. int id;
  688. } rtl8139pci[] = {
  689. { "rtl8139", (0x8139<<16)|0x10EC, }, /* generic */
  690. { "smc1211", (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
  691. { "dfe-538tx", (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
  692. { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
  693. { nil },
  694. };
  695. static int
  696. rtl8139pnp(Ether* edev)
  697. {
  698. int i, id;
  699. Pcidev *p;
  700. Ctlr *ctlr;
  701. unsigned char ea[Eaddrlen];
  702. /*
  703. * Make a list of all ethernet controllers
  704. * if not already done.
  705. */
  706. if(ctlrhead == nil){
  707. p = nil;
  708. while(p = pcimatch(p, 0, 0)){
  709. if(p->ccrb != 0x02 || p->ccru != 0)
  710. continue;
  711. ctlr = malloc(sizeof(Ctlr));
  712. if(ctlr == nil)
  713. error(Enomem);
  714. ctlr->pcidev = p;
  715. ctlr->id = (p->did<<16)|p->vid;
  716. if(ctlrhead != nil)
  717. ctlrtail->next = ctlr;
  718. else
  719. ctlrhead = ctlr;
  720. ctlrtail = ctlr;
  721. }
  722. }
  723. /*
  724. * Is it an RTL8139 under a different name?
  725. * Normally a search is made through all the found controllers
  726. * for one which matches any of the known vid+did pairs.
  727. * If a vid+did pair is specified a search is made for that
  728. * specific controller only.
  729. */
  730. id = 0;
  731. for(i = 0; i < edev->nopt; i++){
  732. if(cistrncmp(edev->opt[i], "id=", 3) == 0)
  733. id = strtol(&edev->opt[i][3], nil, 0);
  734. }
  735. ctlr = nil;
  736. if(id != 0)
  737. ctlr = rtl8139match(edev, id);
  738. else for(i = 0; rtl8139pci[i].name; i++){
  739. if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil)
  740. break;
  741. }
  742. if(ctlr == nil)
  743. return -1;
  744. edev->ctlr = ctlr;
  745. edev->port = ctlr->port;
  746. edev->irq = ctlr->pcidev->intl;
  747. edev->tbdf = ctlr->pcidev->tbdf;
  748. /*
  749. * Check if the adapter's station address is to be overridden.
  750. * If not, read it from the device and set in edev->ea.
  751. */
  752. memset(ea, 0, Eaddrlen);
  753. if(memcmp(ea, edev->ea, Eaddrlen) == 0){
  754. i = csr32r(ctlr, Idr0);
  755. edev->ea[0] = i;
  756. edev->ea[1] = i>>8;
  757. edev->ea[2] = i>>16;
  758. edev->ea[3] = i>>24;
  759. i = csr32r(ctlr, Idr0+4);
  760. edev->ea[4] = i;
  761. edev->ea[5] = i>>8;
  762. }
  763. edev->arg = edev;
  764. edev->attach = rtl8139attach;
  765. edev->transmit = rtl8139transmit;
  766. edev->interrupt = rtl8139interrupt;
  767. edev->ifstat = rtl8139ifstat;
  768. edev->promiscuous = rtl8139promiscuous;
  769. edev->multicast = rtl8139multicast;
  770. edev->shutdown = rtl8139shutdown;
  771. /*
  772. * This should be much more dynamic but will do for now.
  773. */
  774. if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
  775. edev->mbps = 100;
  776. return 0;
  777. }
  778. void
  779. ether8139link(void)
  780. {
  781. addethercard("rtl8139", rtl8139pnp);
  782. }