6.c 3.3 KB

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  1. /*
  2. * amd64 definition
  3. */
  4. #include <u.h>
  5. #include <bio.h>
  6. #include "/amd64/include/ureg.h"
  7. #include <mach.h>
  8. #define REGOFF(x) (uvlong)(&((struct Ureg *) 0)->x)
  9. #define PC REGOFF(ip)
  10. #define SP REGOFF(sp)
  11. #define AX REGOFF(ax)
  12. #define REGSIZE sizeof(struct Ureg)
  13. #define FP_CTLS(x) (REGSIZE+2*(x))
  14. #define FP_CTL(x) (REGSIZE+4*(x))
  15. #define FP_REG(x) (FP_CTL(8)+16*(x))
  16. #define XM_REG(x) (FP_CTL(8)+8*16+16*(x))
  17. #define FPREGSIZE 512 /* TO DO? currently only 0x1A0 used */
  18. Reglist amd64reglist[] = {
  19. {"AX", REGOFF(ax), RINT, 'Y'},
  20. {"BX", REGOFF(bx), RINT, 'Y'},
  21. {"CX", REGOFF(cx), RINT, 'Y'},
  22. {"DX", REGOFF(dx), RINT, 'Y'},
  23. {"SI", REGOFF(si), RINT, 'Y'},
  24. {"DI", REGOFF(di), RINT, 'X'},
  25. {"BP", REGOFF(bp), RINT, 'Y'},
  26. {"R8", REGOFF(r8), RINT, 'Y'},
  27. {"R9", REGOFF(r9), RINT, 'Y'},
  28. {"R10", REGOFF(r10), RINT, 'Y'},
  29. {"R11", REGOFF(r11), RINT, 'Y'},
  30. {"R12", REGOFF(r12), RINT, 'Y'},
  31. {"R13", REGOFF(r13), RINT, 'Y'},
  32. {"R14", REGOFF(r14), RINT, 'Y'},
  33. {"R15", REGOFF(r15), RINT, 'Y'},
  34. {"DS", REGOFF(ds), RINT, 'x'},
  35. {"ES", REGOFF(es), RINT, 'x'},
  36. {"FS", REGOFF(fs), RINT, 'x'},
  37. {"GS", REGOFF(gs), RINT, 'x'},
  38. {"TYPE", REGOFF(type), RINT, 'Y'},
  39. {"ERROR", REGOFF(error), RINT, 'Y'},
  40. {"PC", PC, RINT, 'Y'},
  41. {"CS", REGOFF(cs), RINT, 'Y'},
  42. {"FLAGS", REGOFF(flags), RINT, 'Y'},
  43. {"SP", SP, RINT, 'Y'},
  44. {"SS", REGOFF(ss), RINT, 'Y'},
  45. {"FCW", FP_CTLS(0), RFLT, 'x'},
  46. {"FSW", FP_CTLS(1), RFLT, 'x'},
  47. {"FTW", FP_CTLS(2), RFLT, 'x'},
  48. {"FOP", FP_CTLS(3), RFLT, 'x'},
  49. {"FPC", FP_CTL(2), RFLT, 'Y'},
  50. {"RDP", FP_CTL(4), RFLT, 'Y'},
  51. {"MXCSR", FP_CTL(6), RFLT, 'X'},
  52. {"MXCSRMSK", FP_CTL(7), RFLT, 'X'},
  53. {"M0", FP_REG(0), RFLT, 'F'}, /* assumes double */
  54. {"M1", FP_REG(1), RFLT, 'F'},
  55. {"M2", FP_REG(2), RFLT, 'F'},
  56. {"M3", FP_REG(3), RFLT, 'F'},
  57. {"M4", FP_REG(4), RFLT, 'F'},
  58. {"M5", FP_REG(5), RFLT, 'F'},
  59. {"M6", FP_REG(6), RFLT, 'F'},
  60. {"M7", FP_REG(7), RFLT, 'F'},
  61. {"X0", XM_REG(0), RFLT, 'F'}, /* assumes double */
  62. {"X1", XM_REG(1), RFLT, 'F'},
  63. {"X2", XM_REG(2), RFLT, 'F'},
  64. {"X3", XM_REG(3), RFLT, 'F'},
  65. {"X4", XM_REG(4), RFLT, 'F'},
  66. {"X5", XM_REG(5), RFLT, 'F'},
  67. {"X6", XM_REG(6), RFLT, 'F'},
  68. {"X7", XM_REG(7), RFLT, 'F'},
  69. {"X8", XM_REG(8), RFLT, 'F'},
  70. {"X9", XM_REG(9), RFLT, 'F'},
  71. {"X10", XM_REG(10), RFLT, 'F'},
  72. {"X11", XM_REG(11), RFLT, 'F'},
  73. {"X12", XM_REG(12), RFLT, 'F'},
  74. {"X13", XM_REG(13), RFLT, 'F'},
  75. {"X14", XM_REG(14), RFLT, 'F'},
  76. {"X15", XM_REG(15), RFLT, 'F'},
  77. {"X16", XM_REG(16), RFLT, 'F'},
  78. /*
  79. {"F0", FP_REG(7), RFLT, '3'},
  80. {"F1", FP_REG(6), RFLT, '3'},
  81. {"F2", FP_REG(5), RFLT, '3'},
  82. {"F3", FP_REG(4), RFLT, '3'},
  83. {"F4", FP_REG(3), RFLT, '3'},
  84. {"F5", FP_REG(2), RFLT, '3'},
  85. {"F6", FP_REG(1), RFLT, '3'},
  86. {"F7", FP_REG(0), RFLT, '3'},
  87. */
  88. { 0 }
  89. };
  90. Mach mamd64=
  91. {
  92. "amd64",
  93. MI386, /* machine type */ /* TO DO */
  94. amd64reglist, /* register list */
  95. REGSIZE, /* size of registers in bytes */
  96. FPREGSIZE, /* size of fp registers in bytes */
  97. "PC", /* name of PC */
  98. "SP", /* name of SP */
  99. 0, /* link register */
  100. "setSB", /* static base register name (bogus anyways) */
  101. 0, /* static base register value */
  102. 0x1000, /* page size */
  103. 0x80100000, /* kernel base */ /* TO DO: uvlong or vlong */
  104. 0, /* kernel text mask */
  105. 1, /* quantization of pc */
  106. 8, /* szaddr */
  107. 4, /* szreg */
  108. 4, /* szfloat */
  109. 8, /* szdouble */
  110. };