vgadb 11 KB

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  1. .TH VGADB 6
  2. .SH NAME
  3. vgadb \- VGA controller and monitor database
  4. .SH DESCRIPTION
  5. .PP
  6. The VGA database,
  7. .BR /lib/vgadb ,
  8. consists of two parts,
  9. the first describing how to identify and program a VGA controller
  10. and the second describing the timing parameters for known
  11. monitors to be loaded into a VGA controller to give a particular
  12. resolution and refresh rate.
  13. Conventionally, at system boot, the program
  14. .B aux/vga
  15. (see
  16. .IR vga (8))
  17. uses the monitor type in
  18. .BR /env/monitor ,
  19. the display resolution in
  20. .BR /env/vgasize ,
  21. and the VGA controller information in the database to
  22. find a matching monitor entry and initialize the VGA controller accordingly.
  23. .PP
  24. The file comprises multi-line entries made up of
  25. attribute/value pairs of the form
  26. .IB attr = value
  27. or sometimes just
  28. .IR attr .
  29. Each line starting without white space starts a new entry.
  30. Lines starting with
  31. .B #
  32. are comments.
  33. .PP
  34. The first part of the database, the VGA controller identification and
  35. programming information,
  36. consists of a number of entries with attribute
  37. .B ctlr
  38. and no value.
  39. Within one of these entries the following attributes are
  40. meaningful:
  41. .TF 0xC0000
  42. .TP
  43. .I nnnnn
  44. an offset into the VGA BIOS area.
  45. The value is a string expected to be found there that will
  46. identify the controller.
  47. For example,
  48. .B 0xC0068="#9GXE64 Pro"
  49. would identify a #9GXEpro VGA controller if the string
  50. .B "#9GXE64 Pro"
  51. was found in the BIOS at address 0xC0068.
  52. There may be more than one identifier attribute per controller.
  53. If a match cannot be found, the first few bytes of the BIOS
  54. are printed to help identify the card and create a controller
  55. entry.
  56. .TP
  57. .IB nnnnn - mmmmm
  58. A range of the VGA BIOS area.
  59. The value is a string as above, but the entire range
  60. is searched for that string.
  61. The string must begin at or after
  62. .I nnnnn
  63. and not contain any characters at or after
  64. .IR mmmmm .
  65. For example,
  66. .B 0xC0000-0xC0200="MACH64LP"
  67. identifies a Mach 64 controller with the
  68. string
  69. .B MACH64LP
  70. occurring anywhere in the first 512 bytes of BIOS memory.
  71. .TP
  72. .B ctlr
  73. VGA controller chip type.
  74. This must match one of the VGA controller types
  75. known to
  76. .B /dev/vgactl
  77. (see
  78. .IR vga (3))
  79. and internally to
  80. .BR aux/vga .
  81. Currently,
  82. .BR ark2000pv ,
  83. .BR clgd542x ,
  84. .BR ct65540 ,
  85. .BR ct65545 ,
  86. .BR cyber938x ,
  87. .BR et4000 ,
  88. .BR hiqvideo ,
  89. .BR ibm8514 ,
  90. .BR mach32 ,
  91. .BR mach64 ,
  92. .BR mach64xx ,
  93. .BR mga2164w ,
  94. .BR neomagic ,
  95. .BR s3801 ,
  96. .BR s3805 ,
  97. .BR s3928 ,
  98. .BR t2r4 ,
  99. .BR trio64 ,
  100. .BR virge ,
  101. .BR vision864 ,
  102. .BR vision964 ,
  103. .BR vision968 ,
  104. and
  105. .B w30c516
  106. are recognized.
  107. .TP
  108. .B ramdac
  109. RAMDAC controller type.
  110. This must match one of the types
  111. known internally to
  112. .BR aux/vga .
  113. Currently
  114. .BR att20c490 ,
  115. .BR att20c491 ,
  116. .BR att20c492 ,
  117. .BR att21c498 ,
  118. .BR bt485 ,
  119. .BR rgb524mn ,
  120. .BR sc15025 ,
  121. .BR stg1702 ,
  122. .BR tvp3020 ,
  123. .BR tvp3025 ,
  124. and
  125. .B tvp3026
  126. are recognized.
  127. .TP
  128. .B clock
  129. clock generator type.
  130. This must match one of the types
  131. known internally to
  132. .BR aux/vga .
  133. Currently
  134. .BR ch9294 ,
  135. .BR icd2061a ,
  136. .BR ics2494 ,
  137. .BR ics2494a ,
  138. .BR s3clock ,
  139. .BR tvp3025clock ,
  140. and
  141. .B tvp3026clock
  142. are recognized.
  143. .TP
  144. .B hwgc
  145. hardware graphics cursor type.
  146. This must match one of the types
  147. known to
  148. .B /dev/vgactl
  149. and internally to
  150. .BR aux/vga .
  151. Currently
  152. .BR ark200pvhwgc ,
  153. .BR bt485hwgc ,
  154. .BR clgd542xhwgc ,
  155. .BR clgd546xhwgc ,
  156. .BR ct65545hwgc ,
  157. .BR cyber938xhwgc ,
  158. .BR hiqvideohwgc ,
  159. .BR mach64xxhwgc ,
  160. .BR mga2164whwgc ,
  161. .BR neomagichwgc ,
  162. .BR rgb524hwgc ,
  163. .BR s3hwgc ,
  164. .BR t2r4hwgc ,
  165. .BR tvp3020hwgc ,
  166. and
  167. .B tvp3026hwgc
  168. are recognized.
  169. .TP
  170. .B membw
  171. Memory bandwidth in megabytes per second.
  172. .I Vga
  173. chooses the highest refresh rate possible within the constraints
  174. of the monitor (explained below) and the
  175. card's memory bandwidth.
  176. .TP
  177. .B linear
  178. Whether the card supports a large (>64kb) linear memory
  179. window. The value is either
  180. .B 1
  181. or
  182. .B 0
  183. (equivalent to unspecified).
  184. The current kernel graphics subsystem
  185. requires a linear window; entries without
  186. .B linear=1
  187. are of historic value only.
  188. .TP
  189. .B link
  190. This must match one of the types
  191. known internally to
  192. .BR aux/vga .
  193. Currently
  194. .B vga
  195. and
  196. .B ibm8514
  197. are recognized.
  198. The type
  199. .B vga
  200. handles generic VGA functions and should almost always be included.
  201. The type
  202. .B Ibm8514
  203. handles basic graphics accelerator initialization on controllers
  204. such as the early S3 family of GUI chips.
  205. .PD
  206. .PP
  207. The
  208. .BR clock ,
  209. .BR ctlr ,
  210. .BR link ,
  211. and
  212. .B ramdac
  213. values can all take an extension following a
  214. .B '-'
  215. that can be used as a speed-grade
  216. or subtype; matching is done without the extension.
  217. For example,
  218. .B ramdac=stg1702-135
  219. indicates the STG1702 RAMDAC has a maximum clock frequency of 135MHz,
  220. and
  221. .B clock=ics2494a-324
  222. indicates that the frequency table numbered
  223. 324
  224. should be used for the ICS2494A clock generator.
  225. .PP
  226. The functions internal to
  227. .B aux/vga
  228. corresponding to the
  229. .BR clock ,
  230. .BR ctlr ,
  231. .BR link ,
  232. and
  233. .B ramdac
  234. values will be called in the order given for initialization.
  235. Sometimes the clock should be set before the RAMDAC is initialized,
  236. for example, depending on the components used.
  237. In general,
  238. .BR link=vga
  239. will always be first and,
  240. if appropriate,
  241. .BR link=ibm8514
  242. will be last.
  243. .PP
  244. The entries in the second part of
  245. .B /lib/vgadb
  246. have as attribute the name of a monitor type
  247. and the value is conventionally a resolution in the form
  248. .IB X x Y\f1,
  249. where
  250. .I X
  251. and
  252. .I Y
  253. are numbers representing width and height in pixels.
  254. The monitor type (i.e. entry)
  255. .B include
  256. has special properties, described below and shown in the examples.
  257. The remainder of the entry contains timing information for
  258. the desired resolution.
  259. Within one of these entries the following attributes are
  260. meaningful:
  261. .TF interlace
  262. .TP
  263. .B clock
  264. the video dot-clock frequency in MHz required for this resolution.
  265. The value 25.175 is known internally to
  266. .IR vga (8)
  267. as the baseline VGA clock rate.
  268. .B defaultclock
  269. the default video dot-clock frequency in MHz used
  270. for this resolution when no
  271. memory bandwidth is specified for the card
  272. or when
  273. .I vga
  274. cannot determine the maximum clock frequency of the card.
  275. .TP
  276. .B shb
  277. start horizontal blanking, in character clocks.
  278. .TP
  279. .B ehb
  280. end horizontal blanking, in character clocks.
  281. .TP
  282. .B ht
  283. horizontal total, in character clocks.
  284. .TP
  285. .B vrs
  286. vertical refresh start, in character clocks.
  287. .TP
  288. .B vre
  289. vertical refresh end, in character clocks.
  290. .TP
  291. .B vt
  292. vertical total, in character clocks.
  293. .TP
  294. .B hsync
  295. horizontal sync polarity.
  296. Value must be
  297. .B +
  298. or
  299. .BR - .
  300. .TP
  301. .B vsync
  302. vertical sync polarity.
  303. Value must be
  304. .B +
  305. or
  306. .BR - .
  307. .TP
  308. .B interlace
  309. interlaced mode.
  310. Only value
  311. .B v
  312. is recognized.
  313. .TP
  314. .B alias
  315. continue, replacing the
  316. .B alias
  317. line by the contents of the entry whose attribute is given as
  318. .IR value .
  319. .TP
  320. .B include
  321. continue, replacing this
  322. .B include
  323. line by the contents of the previously defined
  324. .B include
  325. monitor type with matching
  326. .IR value .
  327. (See the examples.)
  328. Any non-zero attributes already set will not be overwritten.
  329. This is used to save duplication of timing information.
  330. Note that
  331. .I value
  332. is not parsed, it is only used as a string
  333. to identify the previous
  334. .BI include= value
  335. monitor type entry.
  336. .PD
  337. .PP
  338. The values given for
  339. .BR shb ,
  340. .BR ehb ,
  341. .BR ht ,
  342. .BR vrs ,
  343. .BR vre ,
  344. .BR vt ,
  345. .BR hsync ,
  346. and
  347. .B vsync
  348. are beyond the
  349. scope of this manual page.
  350. See the book by
  351. Ferraro
  352. for details.
  353. .SH EXAMPLES
  354. Basic
  355. .B ctlr
  356. entry for a laptop with a Chips and Technology 65550
  357. controller:
  358. .EX
  359. ctlr # NEC Versa 6030X/6200MX
  360. 0xC0090="CHIPS 65550 PCI & VL Accelerated VGA BIOS"
  361. link=vga
  362. ctlr=hiqvideo linear=1
  363. hwgc=hiqvideohwgc
  364. .EE
  365. A more complex entry. Note the extensions on the
  366. .BR clock ,
  367. .BR ctlr ,
  368. and
  369. .B ramdac
  370. attributes. The order here is important: the RAMDAC clock input must be
  371. initialized before the RAMDAC itself. The clock frequency is selected by
  372. the
  373. .B ET4000
  374. chip.
  375. .EX
  376. ctlr # Hercules Dynamite Power
  377. 0xC0076="Tseng Laboratories, Inc. 03/04/94 V8.00N"
  378. link=vga
  379. clock=ics2494a-324
  380. ctlr=et4000-w32p
  381. ramdac=stg1702-135
  382. .EE
  383. Monitor entry for type
  384. .B vga
  385. (the default monitor type used by
  386. .IR vga (8))
  387. and resolution 640x480x[18].
  388. .EX
  389. include = 640x480@60Hz # 60Hz, 31.5KHz
  390. clock=25.175
  391. shb=664 ehb=760 ht=800
  392. vrs=491 vre=493 vt=525
  393. vga = 640x480 # 60Hz, 31.5KHz
  394. include=640x480@60Hz
  395. .EE
  396. Entries for multisync monitors with video bandwidth up to 65MHz.
  397. .EX
  398. #
  399. # Multisync monitors with video bandwidth up to 65MHz.
  400. #
  401. multisync65 = 1024x768 # 60Hz, 48.4KHz
  402. include=1024x768@60Hz
  403. multisync65 = 1024x768i # 87Hz, 35.5KHz (interlaced)
  404. include=1024x768i@87Hz
  405. multisync65
  406. alias=vga
  407. .EE
  408. Note how this builds on the existing
  409. .B vga
  410. entries.
  411. .SH FILES
  412. .TP
  413. .B /lib/vgadb
  414. .SH "SEE ALSO"
  415. .IR ndb (2),
  416. .IR vga (3),
  417. .IR ndb (6),
  418. .IR 9load (8),
  419. .IR vga (8)
  420. .br
  421. Richard E. Ferraro,
  422. .I
  423. Programming Guide to the EGA, VGA and Super VGA Cards,
  424. Third Edition
  425. .SH BUGS
  426. The database should provide a way
  427. to use the PCI bus
  428. as well as BIOS memory to identify cards.
  429. .SH "ADDING A NEW MONITOR"
  430. Adding a new monitor is usually fairly straightforward, as most modern monitors
  431. are multisync and the only interesting parameter is the
  432. maximum video bandwidth.
  433. Once the timing parameters are worked out for a particular maximum
  434. video bandwidth as in the example above, an entry for a new monitor
  435. with that limit is simply
  436. .EX
  437. #
  438. # Sony CPD-1304
  439. # Horizontal timing:
  440. # Allowable frequency range: 28-50KHz
  441. # Vertical timing:
  442. # Allowable frequency range: 50-87Hz
  443. #
  444. cpd-1304
  445. alias=multisync65
  446. .EE
  447. Even this is not necessary, as the monitor type could simply be
  448. given as
  449. .BR multisync65 .
  450. .SH "ADDING A NEW VGA CONTROLLER"
  451. While the use of this database formalizes the steps needed to
  452. program a VGA controller,
  453. unless you are lucky and all the important components on
  454. a new VGA controller card are interconnected in the same way as an
  455. existing entry, adding a new entry requires adding new internal
  456. types to
  457. .IR vga (8).
  458. Fortunately, the unit of variety
  459. has, for the most part, shifted from
  460. individual components to entire
  461. video chipsets.
  462. Thus in lucky cases all that is necessary
  463. is the addition of another
  464. .B 0xNNNNN=
  465. line to the entry for the controller.
  466. This is particularly true in the case
  467. of the ATI Mach 64 and the S3 Virge.
  468. .PP
  469. If you need to actually add support
  470. for a controller with a different chipset,
  471. you will need the data sheets for the VGA controller
  472. as well as any RAMDAC or clock generator
  473. (these are commonly integrated into the controller).
  474. You will also need to know how these components interact.
  475. For example, a common combination is an S3 86C928 VGA chip with
  476. an ICD2061A clock generator. The ICD2061A is usually loaded by clocking
  477. a serial bit-stream out of one of the 86C928 registers.
  478. Similarly, the RAMDAC may have an internal clock-doubler and/or
  479. pixel-multiplexing modes, in which case both the clock generator and
  480. VGA chip must be programmed accordingly.
  481. Hardware acceleration for rectangle fills
  482. and block copies is provided in the kernel;
  483. writing code to handle this is necessary
  484. to achieve reasonable performance at high
  485. pixel depths.