usbohci.c 47 KB

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  1. /*
  2. * USB Open Host Controller Interface (OHCI) driver
  3. * from devohci.c provided by Charles Forsyth, 5 Aug 2006.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #include "usb.h"
  13. #define XPRINT if(usbhdebug) print
  14. #define XIPRINT if(usbhdebug) iprint
  15. #define XEPRINT if(usbhdebug || ep->debug) print
  16. #define XEIPRINT if(usbhdebug || ep->debug) iprint
  17. #define IPRINT(x) iprint x
  18. static int usbhdebug = 0;
  19. static int dcls;
  20. enum {
  21. Ned = 63 + 32,
  22. Ntd = 256,
  23. };
  24. /*
  25. * USB packet definitions
  26. */
  27. enum {
  28. Otoksetup = 0,
  29. Otokout = 1,
  30. Otokin = 2,
  31. /* port status - UHCI style */
  32. Suspend = 1<<12,
  33. PortReset = 1<<9,
  34. SlowDevice = 1<<8,
  35. ResumeDetect = 1<<6,
  36. PortEnableChange = 1<<3, /* write 1 to clear */
  37. PortEnable = 1<<2,
  38. ConnectStatusChange = 1<<1, /* write 1 to clear */
  39. DevicePresent = 1<<0,
  40. };
  41. typedef struct Ctlr Ctlr;
  42. typedef struct QTree QTree;
  43. enum {
  44. ED_MPS_MASK = 0x7ff,
  45. ED_MPS_SHIFT = 16,
  46. ED_C_MASK = 1,
  47. ED_C_SHIFT = 1,
  48. ED_F_BIT = 1 << 15,
  49. ED_S_MASK = 1,
  50. ED_S_SHIFT = 13,
  51. ED_D_MASK = 3,
  52. ED_D_SHIFT = 11,
  53. ED_H_MASK = 1,
  54. ED_H_SHIFT = 0,
  55. };
  56. typedef struct Endptx Endptx;
  57. typedef struct TD TD;
  58. struct Endptx
  59. {
  60. Lock; /* for manipulating ed */
  61. ED *ed; /* Single endpoint descriptor */
  62. int ntd; /* Number of TDs in use */
  63. int overruns;
  64. };
  65. struct TD {
  66. ulong ctrl;
  67. ulong cbp;
  68. ulong nexttd;
  69. ulong be;
  70. ushort offsets[8]; /* Iso TDs only */
  71. /* driver specific; pad to multiple of 32 */
  72. TD* next;
  73. Endpt *ep;
  74. Block *bp;
  75. ulong flags;
  76. ulong offset; /* offset associated with end of data */
  77. ulong bytes; /* bytes in this TD */
  78. ulong pad[2];
  79. };
  80. enum {
  81. TD_R_SHIFT = 18,
  82. TD_DP_MASK = 3,
  83. TD_DP_SHIFT = 19,
  84. TD_CC_MASK = 0xf,
  85. TD_CC_SHIFT = 28,
  86. TD_EC_MASK = 3,
  87. TD_EC_SHIFT = 26,
  88. TD_FLAGS_LAST = 1 << 0,
  89. };
  90. typedef struct HCCA HCCA;
  91. struct HCCA {
  92. ulong intrtable[32];
  93. ushort framenumber;
  94. ushort pad1;
  95. ulong donehead;
  96. uchar reserved[116];
  97. };
  98. /* OHCI registers */
  99. typedef struct OHCI OHCI;
  100. struct OHCI {
  101. /* control and status group */
  102. /*00*/ ulong revision;
  103. ulong control;
  104. ulong cmdsts;
  105. ulong intrsts;
  106. /*10*/ ulong intrenable;
  107. ulong intrdisable;
  108. /* memory pointer group */
  109. ulong hcca;
  110. ulong periodcurred;
  111. /*20*/ ulong ctlheaded;
  112. ulong ctlcurred;
  113. ulong bulkheaded;
  114. ulong bulkcurred;
  115. /*30*/ ulong donehead;
  116. /* frame counter group */
  117. ulong fminterval;
  118. ulong fmremaining;
  119. ulong fmnumber;
  120. /*40*/ ulong periodicstart;
  121. ulong lsthreshold;
  122. /* root hub group */
  123. ulong rhdesca;
  124. ulong rhdescb;
  125. /*50*/ ulong rhsts;
  126. ulong rhportsts[15];
  127. /*90*/ ulong pad25[20];
  128. /* unknown */
  129. /*e0*/ ulong hostueaddr;
  130. ulong hostuests;
  131. ulong hosttimeoutctrl;
  132. ulong pad59;
  133. /*f0*/ ulong pad60;
  134. ulong hostrevision;
  135. ulong pad62[2];
  136. /*100*/
  137. };
  138. /*
  139. * software structures
  140. */
  141. static struct {
  142. int bit;
  143. char *name;
  144. } portstatus[] = {
  145. { Suspend, "suspend", },
  146. { PortReset, "reset", },
  147. { SlowDevice, "lowspeed", },
  148. { ResumeDetect, "resume", },
  149. { PortEnableChange, "portchange", },
  150. { PortEnable, "enable", },
  151. { ConnectStatusChange, "statuschange", },
  152. { DevicePresent, "present", },
  153. };
  154. struct QTree {
  155. QLock;
  156. int nel;
  157. int depth;
  158. ulong* bw;
  159. ED **root;
  160. };
  161. /* device parameters */
  162. static char *devstates[] = {
  163. [Disabled] "Disabled",
  164. [Attached] "Attached",
  165. [Enabled] "Enabled",
  166. };
  167. struct Ctlr {
  168. Lock; /* protects state shared with interrupt (eg, free list) */
  169. int active;
  170. Pcidev* pcidev;
  171. int irq;
  172. ulong tbdf;
  173. Ctlr* next;
  174. int nports;
  175. OHCI *base; /* equiv to io in uhci */
  176. HCCA *uchcca;
  177. int idgen; /* version # to distinguish new connections */
  178. QLock resetl; /* lock controller during USB reset */
  179. struct {
  180. Lock;
  181. TD* pool;
  182. TD* free;
  183. int alloced;
  184. } td;
  185. struct {
  186. QLock;
  187. ED* pool;
  188. ED* free;
  189. int alloced;
  190. } ed;
  191. /* TODO: what happened to ctlq, etc. from uhci? */
  192. QTree* tree; /* tree for t Endpt i/o */
  193. struct {
  194. QLock;
  195. Endpt* f;
  196. } activends;
  197. };
  198. enum {
  199. HcRevision = 0x00,
  200. HcControl = 0x01,
  201. HcfsMask = 3 << 6,
  202. HcfsReset = 0 << 6,
  203. HcfsResume = 1 << 6,
  204. HcfsOperational=2 << 6,
  205. HcfsSuspend = 3 << 6,
  206. Ble = 1 << 5,
  207. Cle = 1 << 4,
  208. Ie = 1 << 3,
  209. Ple = 1 << 2,
  210. Cbsr_MASK = 3,
  211. HcCommandStatus = 0x02,
  212. Ocr = 1 << 3,
  213. Blf = 1 << 2,
  214. Clf = 1 << 1,
  215. Hcr = 1 << 0,
  216. HcIntrStatus = 0x03,
  217. HcIntrEnable = 0x04,
  218. Mie = 1 << 31,
  219. Oc = 1 << 30,
  220. Rhsc = 1 << 6,
  221. Fno = 1 << 5,
  222. Ue = 1 << 4,
  223. Rd = 1 << 3,
  224. Sf = 1 << 2,
  225. Wdh = 1 << 1,
  226. So = 1 << 0,
  227. HcIntrDisable = 0x05,
  228. HcFmIntvl = 0x0d,
  229. HcFmIntvl_FSMaxpack_MASK = 0x7fff,
  230. HcFmIntvl_FSMaxpack_SHIFT = 16,
  231. HcFmRemaining = 0x0e,
  232. HcFmNumber = 0x0f,
  233. HcLSThreshold = 0x11,
  234. HcRhDescA = 0x12,
  235. HcRhDescA_POTPGT_MASK = 0xff << 24,
  236. HcRhDescA_POTPGT_SHIFT = 24,
  237. HcRhDescB = 0x13,
  238. HcRhStatus = 0x14,
  239. Lps = 1 << 0,
  240. Cgp = 1 << 0,
  241. Oci = 1 << 1,
  242. Drwe = 1 << 15,
  243. Srwe = 1 << 15,
  244. LpsC = 1 << 16,
  245. Sgp = 1 << 16,
  246. Ccic = 1 << 17,
  247. Crwe = 1 << 31,
  248. HcRhPortStatus1 = 0x15,
  249. Ccs = 1 << 0,
  250. Cpe = 1 << 0,
  251. Pes = 1 << 1,
  252. Spe = 1 << 1,
  253. Pss = 1 << 2,
  254. Poci = 1 << 3,
  255. Prs = 1 << 4,
  256. Spr = 1 << 4,
  257. Pps = 1 << 8,
  258. Spp= 1 << 8,
  259. Lsda = 1 << 9,
  260. Cpp = 1 << 9,
  261. Csc = 1 << 16,
  262. Pesc = 1 << 17,
  263. Pssc = 1 << 18,
  264. Ocic = 1 << 19,
  265. Prsc = 1 << 20,
  266. HcRhPortStatus2 = 0x16,
  267. L2NFRAME = 5,
  268. NFRAME = 1 << L2NFRAME,
  269. /* TODO: from UHCI; correct for OHCI? */
  270. FRAMESIZE = NFRAME*sizeof(ulong), /* fixed by hardware; aligned to same */
  271. };
  272. char *usbmode[] = {
  273. [Ctlmode]= "Ctl",
  274. [Bulkmode] = "Bulk",
  275. [Intrmode] = "Intr",
  276. [Isomode] = "Iso",
  277. };
  278. static char *ousbmode[] = {
  279. [OREAD] = "r",
  280. [OWRITE] = "w",
  281. [ORDWR] = "rw",
  282. };
  283. int ohciinterrupts[Nmodes];
  284. static Ctlr* ctlrhead;
  285. static Ctlr* ctlrtail;
  286. static char Estalled[] = "usb endpoint stalled";
  287. static char EnotWritten[] = "usb write unfinished";
  288. static char EnotRead[] = "usb read unfinished";
  289. static char Eunderrun[] = "usb endpoint underrun";
  290. static QLock usbhstate; /* protects name space state */
  291. static void eptactivate(Ctlr *ub, Endpt *ep);
  292. static void eptdeactivate(Ctlr *ub, Endpt *e);
  293. static long read (Usbhost *, Endpt*, void*, long, vlong);
  294. static void scanpci(void);
  295. static int schedendpt(Ctlr *ub, Endpt *ep, int direction);
  296. static void unschedendpt(Ctlr *ub, Endpt *ep, int);
  297. static long write(Usbhost *, Endpt*, void*, long, vlong, int);
  298. static long qtd(Ctlr*, Endpt*, int, Block*, uchar*, uchar*, int, ulong);
  299. void
  300. printdata(void *pdata, int itemsize, int nitems)
  301. {
  302. int i;
  303. uchar *p1;
  304. ushort *p2;
  305. ulong *p4;
  306. if(!usbhdebug)
  307. return;
  308. p1 = pdata;
  309. p2 = pdata;
  310. p4 = pdata;
  311. i = 0;
  312. for(;;){
  313. switch(itemsize){
  314. default:
  315. assert(0);
  316. case 1:
  317. print("%2.2ux ", *p1++);
  318. break;
  319. case 2:
  320. print("%4.4ux ", *p2++);
  321. break;
  322. case 4:
  323. print("%8.8lux ", *p4++);
  324. break;
  325. }
  326. if(++i >= nitems || (i & ((0x40 >> itemsize) - 1)) == 0){
  327. print("\n");
  328. if(i >= nitems)
  329. break;
  330. }
  331. }
  332. }
  333. /*
  334. * i left these in so that we could use the same
  335. * driver on several other platforms (in principle).
  336. * the processor on which it was originally developed
  337. * had an IO MMU and thus another address space.
  338. * it's nothing to do with USB as such.
  339. */
  340. ulong
  341. va2hcva(void *va)
  342. {
  343. if(va == nil)
  344. return 0;
  345. return PADDR(va);
  346. }
  347. void *
  348. hcva2va(ulong hcva)
  349. {
  350. if(hcva == 0)
  351. return nil;
  352. return KADDR(hcva);
  353. }
  354. void *
  355. va2ucva(void *va)
  356. {
  357. return va;
  358. }
  359. void *
  360. hcva2ucva(ulong hcva)
  361. {
  362. if(hcva == 0)
  363. return nil;
  364. if(hcva & 0xf0000000){
  365. iprint("hcva2ucva: bad 0x%lux, called from 0x%lux\n",
  366. hcva, getcallerpc(&hcva));
  367. return nil;
  368. }
  369. return KADDR(hcva);
  370. }
  371. #define IOCACHED 0
  372. #define invalidatedcacheva(va)
  373. #define dcclean(p, n)
  374. static void
  375. EDinit(ED *ed, int mps, int f, int k, int s, int d, int en, int fa,
  376. TD *tail, TD *head, int c, int h, ED *next)
  377. {
  378. /* check nothing is running? */
  379. ed->ctrl = (mps & ED_MPS_MASK) << ED_MPS_SHIFT
  380. | (f & 1) << 15
  381. | (k & 1) << 14
  382. | (s & ED_S_MASK) << ED_S_SHIFT
  383. | (d & 3) << 11 /* 00 is obtained from TD (used here) */
  384. | (en & 0xf) << 7
  385. | (fa & 0x7f);
  386. ed->tail = va2hcva(tail) & ~0xF;
  387. ed->head = (va2hcva(head) & ~0xF)
  388. | (c & ED_C_MASK) << ED_C_SHIFT
  389. | (h & ED_H_MASK) << ED_H_SHIFT;
  390. ed->next = va2hcva(next) & ~0xF;
  391. }
  392. static void
  393. EDsetS(ED *ed, int s)
  394. {
  395. XIPRINT("EDsetS: %s speed\n", s == Lowspeed ? "low" : "high");
  396. if(s == Lowspeed)
  397. ed->ctrl |= 1 << ED_S_SHIFT;
  398. else
  399. ed->ctrl &= ~(1 << ED_S_SHIFT);
  400. }
  401. static void
  402. EDsetMPS(ED *ed, int mps)
  403. {
  404. ed->ctrl = (ed->ctrl & ~(ED_MPS_MASK << ED_MPS_SHIFT)) |
  405. (mps & ED_MPS_MASK) << ED_MPS_SHIFT;
  406. }
  407. static void
  408. EDsetC(ED *ed, int c)
  409. {
  410. ed->head = (ed->head & ~(ED_C_MASK << ED_C_SHIFT)) |
  411. (c & ED_C_MASK) << ED_C_SHIFT;
  412. }
  413. static void
  414. EDsetH(ED *ed, int h)
  415. {
  416. ed->head = (ed->head & ~(ED_H_MASK << ED_H_SHIFT)) |
  417. (h & ED_H_MASK) << ED_H_SHIFT;
  418. }
  419. static int
  420. EDgetH(ED *ed)
  421. {
  422. return (ed->head >> ED_H_SHIFT) & ED_H_MASK;
  423. }
  424. static int
  425. EDgetC(ED *ed)
  426. {
  427. return (ed->head >> ED_C_SHIFT) & ED_C_MASK;
  428. }
  429. static void
  430. EDsetnext(ED *ed, void *va)
  431. {
  432. ed->next = va2hcva(va) & ~0xF;
  433. }
  434. static ED *
  435. EDgetnext(ED *ed)
  436. {
  437. return hcva2ucva(ed->next & ~0xF);
  438. }
  439. static void
  440. EDsettail(ED *ed, void *va)
  441. {
  442. ed->tail = va2hcva(va) & ~0xF;
  443. }
  444. static TD *
  445. EDgettail(ED *ed)
  446. {
  447. return hcva2ucva(ed->tail & ~0xF);
  448. }
  449. static void
  450. EDsethead(ED *ed, void *va)
  451. {
  452. ed->head = (ed->head & 0xf) | (va2hcva(va) & ~0xF);
  453. }
  454. static TD *
  455. EDgethead(ED *ed)
  456. {
  457. return hcva2ucva(ed->head & ~0xF);
  458. }
  459. static ED *
  460. EDalloc(Ctlr *ub)
  461. {
  462. ED *t;
  463. qlock(&ub->ed);
  464. t = ub->ed.free;
  465. if(t == nil){
  466. qunlock(&ub->ed);
  467. return nil;
  468. }
  469. ub->ed.free = (ED *)t->next;
  470. ub->ed.alloced++;
  471. if (0)
  472. print("%d endpoints allocated\n", ub->ed.alloced);
  473. qunlock(&ub->ed);
  474. t->next = 0;
  475. return t;
  476. }
  477. void
  478. TDsetnexttd(TD *td, TD *va)
  479. {
  480. td->nexttd = va2hcva(va) & ~0xF;
  481. }
  482. TD *
  483. TDgetnexttd(TD *td)
  484. {
  485. return hcva2ucva(td->nexttd & ~0xF);
  486. }
  487. void
  488. OHCIsetControlHeadED(OHCI *ohci, ED *va)
  489. {
  490. ohci->ctlheaded = va2hcva(va) & ~0xF;
  491. }
  492. ED *
  493. OHCIgetControlHeadED(OHCI *ohci)
  494. {
  495. return hcva2ucva(ohci->ctlheaded);
  496. }
  497. void
  498. OHCIsetBulkHeadED(OHCI *ohci, ED *va)
  499. {
  500. ohci->bulkheaded = va2hcva(va) & ~0xF;
  501. }
  502. ED *
  503. OHCIgetBulkHeadED(OHCI *ohci)
  504. {
  505. return hcva2ucva(ohci->bulkheaded);
  506. }
  507. static TD *
  508. TDalloc(Ctlr *ub, Endpt *ep, int musthave) /* alloctd */
  509. {
  510. TD *t;
  511. Endptx *epx;
  512. for(;;){
  513. ilock(ub);
  514. t = ub->td.free;
  515. if(t)
  516. break;
  517. iunlock(ub);
  518. if(up == nil){
  519. if(musthave)
  520. panic("TDalloc: out of descs");
  521. return nil;
  522. }
  523. tsleep(&up->sleep, return0, 0, 100);
  524. }
  525. ub->td.free = t->next;
  526. epx = ep->private;
  527. epx->ntd++;
  528. ub->td.alloced++;
  529. iunlock(ub);
  530. memset(t, 0, sizeof(TD));
  531. t->ep = ep;
  532. return t;
  533. }
  534. /* call under ilock */
  535. static void
  536. TDfree(Ctlr *ub, TD *t) /* freetd */
  537. {
  538. Endptx *epx;
  539. if(t == 0)
  540. return;
  541. if(t->ep){
  542. epx = t->ep->private;
  543. epx->ntd--;
  544. } else
  545. t->ep = nil; /* redundant? */
  546. t->bp = nil;
  547. t->next = ub->td.free;
  548. ub->td.free = t;
  549. ub->td.alloced--;
  550. }
  551. static void
  552. EDfree(Ctlr *ub, ED *t)
  553. {
  554. TD *td, *next;
  555. if(t == 0)
  556. return;
  557. qlock(&ub->ed);
  558. t->next = (ulong)ub->ed.free;
  559. ub->ed.free = t;
  560. ub->ed.alloced--;
  561. if (0)
  562. print("%d endpoints allocated\n", ub->ed.alloced);
  563. ilock(ub);
  564. for(td = EDgethead(t); td; td = next){
  565. next = TDgetnexttd(td);
  566. TDfree(ub, td);
  567. }
  568. iunlock(ub);
  569. EDsethead(t, 0);
  570. EDsettail(t, 0);
  571. qunlock(&ub->ed);
  572. }
  573. static void
  574. waitSOF(Ctlr *ub)
  575. {
  576. /*
  577. * wait for SOF - interlock with interrupt handler so
  578. * done queue processed first.
  579. */
  580. int frame = ub->uchcca->framenumber & 0x3f;
  581. do {
  582. delay(2);
  583. } while(frame == (ub->uchcca->framenumber & 0x3f));
  584. }
  585. static void
  586. dumptd(TD *td, char *s)
  587. {
  588. int i;
  589. Endpt *ep;
  590. ep = td->ep;
  591. print("\t%s: 0x%.8lux ctrl 0x%.8lux cbp 0x%.8lux "
  592. "nexttd 0x%.8lux be 0x%.8lux, flags %lux\n",
  593. s, td, td->ctrl, td->cbp, td->nexttd, td->be, td->flags);
  594. if(ep->epmode != Isomode){
  595. print("\t\tbytes: %ld\n", td->be + 1 - td->cbp);
  596. return;
  597. }
  598. print("\t\t0x%ux 0x%ux 0x%ux 0x%ux 0x%ux 0x%ux 0x%ux 0x%ux\n",
  599. td->offsets[0], td->offsets[1], td->offsets[2], td->offsets[3],
  600. td->offsets[4], td->offsets[5], td->offsets[6], td->offsets[7]);
  601. print("\t\tbytes:");
  602. for(i = 0; i < td->ctrl >> 24 & 0x7; i++)
  603. print(" %d", (td->offsets[i+1]-td->offsets[i])&0xfff);
  604. print(" %ld\n", (td->be + 1 - td->offsets[i]) & 0xfff);
  605. }
  606. static void
  607. dumped(ED *ed)
  608. {
  609. TD *tailp, *td;
  610. tailp = EDgettail(ed);
  611. td = EDgethead(ed);
  612. print("dumpED 0x%lux: ctrl 0x%lux tail 0x%lux head 0x%lux next 0x%lux\n",
  613. ed, ed->ctrl, ed->tail, ed->head, ed->next);
  614. if(tailp == td)
  615. return;
  616. do {
  617. dumptd(td, "td");
  618. } while((td = TDgetnexttd(td)) != tailp);
  619. }
  620. static void
  621. dumpstatus(Ctlr *ub)
  622. {
  623. ED *ed;
  624. print("dumpstatus 0x%lux, frame 0x%ux:\n", ub, ub->uchcca->framenumber);
  625. print("control 0x%lux, cmdstat 0x%lux, intrsts 0x%lux\n",
  626. ub->base->control, ub->base->cmdsts, ub->base->intrsts);
  627. print("Control:\n");
  628. for(ed = OHCIgetControlHeadED(ub->base); ed; ed = EDgetnext(ed))
  629. dumped(ed);
  630. print("Bulk:\n");
  631. for(ed = OHCIgetBulkHeadED(ub->base); ed; ed = EDgetnext(ed))
  632. dumped(ed);
  633. print("Iso:\n");
  634. for(ed = ub->tree->root[0]; ed; ed = EDgetnext(ed))
  635. dumped(ed);
  636. print("frame 0x%ux:\n", ub->uchcca->framenumber);
  637. }
  638. /*
  639. * halt the ED and free input or output transfer descs
  640. * called when the relevant lock in the enclosing Endpt is held
  641. */
  642. static void
  643. EDcancel(Ctlr *ub, ED *ed, int dirin)
  644. {
  645. int tddir, iso, n;
  646. TD *tailp, *headp, *td, *prev, *next;
  647. Endpt *ep;
  648. if(ed == nil)
  649. return;
  650. /* halt ED if not already halted */
  651. if(EDgetH(ed) != 1){
  652. EDsetH(ed, 1);
  653. waitSOF(ub);
  654. }
  655. SET(tddir);
  656. if((iso = ed->ctrl & ED_F_BIT) != 0)
  657. switch((ed->ctrl >> 11) & 0x3){
  658. default:
  659. panic("ED iso direction unset");
  660. case Otokin: tddir = Dirin; break;
  661. case Otokout: tddir = Dirout; break;
  662. }
  663. /* can now clean up TD list of ED */
  664. tailp = EDgettail(ed);
  665. headp = EDgethead(ed);
  666. n = 0;
  667. prev = nil;
  668. td = headp;
  669. while(td != tailp){
  670. ep = td->ep;
  671. if(iso == 0)
  672. switch((td->ctrl >> TD_DP_SHIFT) & TD_DP_MASK){
  673. default:
  674. panic("TD direction unset");
  675. case Otoksetup: tddir = Dirout; break;
  676. case Otokin: tddir = Dirin; break;
  677. case Otokout: tddir = Dirout; break;
  678. }
  679. else if(usbhdebug || ep->debug)
  680. print("EDcancel: buffered: %d, bytes %ld\n",
  681. ep->buffered, td->bytes);
  682. next = TDgetnexttd(td);
  683. if(dirin == 2 || dirin == tddir){
  684. XEPRINT("%d/%d: EDcancel %d\n", ep->dev->x, ep->x, tddir);
  685. /* Remove this sucker */
  686. ep->buffered -= td->bytes;
  687. if(ep->buffered < 0)
  688. ep->buffered = 0;
  689. ilock(ub);
  690. ep->dir[tddir].queued--;
  691. if(tddir == Dirout){
  692. freeb(td->bp);
  693. td->bp = nil;
  694. }
  695. if(prev)
  696. TDsetnexttd(prev, next);
  697. else
  698. EDsethead(ed, next);
  699. TDfree(ub, td);
  700. n++;
  701. iunlock(ub);
  702. }else{
  703. XEPRINT("%d/%d: EDcancel skip %d\n", ep->dev->x, ep->x,
  704. tddir);
  705. prev = td;
  706. }
  707. td = next;
  708. }
  709. XPRINT("EDcancel: %d\n", n);
  710. }
  711. static void
  712. eptactivate(Ctlr *ub, Endpt *ep)
  713. {
  714. Endptx *epx;
  715. qlock(&ub->activends);
  716. if(ep->active == 0){
  717. epx = ep->private;
  718. XEPRINT("%d/%d: activate\n", ep->dev->x, ep->x);
  719. ep->active = 1;
  720. /*
  721. * set the right speed
  722. */
  723. EDsetS(epx->ed, ep->dev->speed);
  724. switch(ep->epmode){
  725. case Ctlmode:
  726. /*
  727. * chain the two descs together, and
  728. * bind to beginning of control queue
  729. */
  730. EDsetnext(epx->ed, OHCIgetControlHeadED(ub->base));
  731. OHCIsetControlHeadED(ub->base, epx->ed);
  732. /*
  733. * prompt controller to absorb new queue on next pass
  734. */
  735. ub->base->cmdsts |= Clf;
  736. XEPRINT("%d/%d: activated in control queue\n",
  737. ep->dev->x, ep->x);
  738. break;
  739. case Bulkmode:
  740. EDsetnext(epx->ed, OHCIgetBulkHeadED(ub->base));
  741. OHCIsetBulkHeadED(ub->base, epx->ed);
  742. ub->base->cmdsts |= Blf;
  743. XEPRINT("%d/%d: activated %s in bulk input queue\n",
  744. ep->dev->x, ep->x, ousbmode[ep->mode]);
  745. break;
  746. case Isomode:
  747. if(ep->mode != OWRITE)
  748. schedendpt(ub, ep, Dirin);
  749. if(ep->mode != OREAD)
  750. schedendpt(ub, ep, Dirout);
  751. ep->buffered = 0;
  752. ep->partial = 0;
  753. break;
  754. case Intrmode:
  755. if(ep->mode != OWRITE)
  756. schedendpt(ub, ep, Dirin);
  757. if(ep->mode != OREAD)
  758. schedendpt(ub, ep, Dirout);
  759. break;
  760. case Nomode:
  761. break;
  762. default:
  763. panic("eptactivate: wierd epmode %d\n", ep->epmode);
  764. }
  765. ep->dir[Dirin].xdone = ep->dir[Dirin].xstarted = 0;
  766. ep->dir[Dirout].xdone = ep->dir[Dirout].xstarted = 0;
  767. ep->activef = ub->activends.f;
  768. ub->activends.f = ep;
  769. }
  770. qunlock(&ub->activends);
  771. }
  772. static void
  773. EDpullfrombulk(Ctlr *ub, ED *ed)
  774. {
  775. ED *this, *prev, *next;
  776. this = OHCIgetBulkHeadED(ub->base);
  777. ub->base->bulkcurred = 0;
  778. prev = nil;
  779. while(this != nil && this != ed){
  780. prev = this;
  781. this = EDgetnext(this);
  782. }
  783. if(this == nil){
  784. print("EDpullfrombulk: not found\n");
  785. return;
  786. }
  787. next = EDgetnext(this);
  788. if(prev == nil)
  789. OHCIsetBulkHeadED(ub->base, next);
  790. else
  791. EDsetnext(prev, next);
  792. EDsetnext(ed, nil); /* wipe out next field */
  793. }
  794. static void
  795. EDpullfromctl(Ctlr *ub, ED *ed)
  796. {
  797. ED *this, *prev, *next;
  798. this = OHCIgetControlHeadED(ub->base);
  799. ub->base->ctlcurred = 0;
  800. prev = nil;
  801. while(this != nil && this != ed){
  802. prev = this;
  803. this = EDgetnext(this);
  804. }
  805. if(this == nil)
  806. panic("EDpullfromctl: not found\n");
  807. next = EDgetnext(this);
  808. if(prev == nil)
  809. OHCIsetControlHeadED(ub->base, next);
  810. else
  811. EDsetnext(prev, next);
  812. EDsetnext(ed, nil); /* wipe out next field */
  813. }
  814. static void
  815. eptdeactivate(Ctlr *ub, Endpt *ep)
  816. {
  817. ulong ctrl;
  818. Endpt **l;
  819. Endptx *epx;
  820. /* could be O(1) but not worth it yet */
  821. qlock(&ub->activends);
  822. if(ep->active){
  823. epx = ep->private;
  824. XEPRINT("ohci: eptdeactivate %d/%d\n", ep->dev->x, ep->x);
  825. ep->active = 0;
  826. for(l = &ub->activends.f; *l != ep; l = &(*l)->activef)
  827. if(*l == nil){
  828. qunlock(&ub->activends);
  829. panic("usb eptdeactivate");
  830. }
  831. *l = ep->activef;
  832. /* pull it from the appropriate queue */
  833. ctrl = ub->base->control;
  834. switch(ep->epmode){
  835. case Ctlmode:
  836. if(ctrl & Cle){
  837. ub->base->control &= ~Cle;
  838. waitSOF(ub);
  839. }
  840. EDpullfromctl(ub, epx->ed);
  841. if(ctrl & Cle){
  842. ub->base->control |= Cle;
  843. /*
  844. * don't fill it if there is nothing in it -
  845. * shouldn't be necessary according to the
  846. * spec., but practice is different
  847. */
  848. if(OHCIgetControlHeadED(ub->base))
  849. ub->base->cmdsts |= Clf;
  850. }
  851. break;
  852. case Bulkmode:
  853. if(ctrl & Ble){
  854. ub->base->control &= ~Ble;
  855. waitSOF(ub);
  856. }
  857. EDpullfrombulk(ub, epx->ed);
  858. if(ctrl & Ble){
  859. ub->base->control |= Ble;
  860. /*
  861. * don't fill it if there is nothing in it -
  862. * shouldn't be necessary according to the
  863. * spec., but practice is different
  864. */
  865. if(OHCIgetBulkHeadED(ub->base))
  866. ub->base->cmdsts |= Blf;
  867. }
  868. break;
  869. case Intrmode:
  870. case Isomode:
  871. if(ep->mode != OWRITE)
  872. unschedendpt(ub, ep, Dirin);
  873. if(ep->mode != OREAD)
  874. unschedendpt(ub, ep, Dirout);
  875. waitSOF(ub);
  876. break;
  877. case Nomode:
  878. break;
  879. default:
  880. panic("eptdeactivate: wierd in.epmode %d\n",
  881. ep->epmode);
  882. }
  883. }
  884. qunlock(&ub->activends);
  885. }
  886. static void
  887. kickappropriatequeue(Ctlr *ub, Endpt *ep, int)
  888. {
  889. switch(ep->epmode){
  890. case Nomode:
  891. break;
  892. case Ctlmode:
  893. ub->base->cmdsts |= Clf;
  894. break;
  895. case Bulkmode:
  896. ub->base->cmdsts |= Blf;
  897. break;
  898. case Intrmode:
  899. case Isomode:
  900. /* no kicking required */
  901. break;
  902. default:
  903. panic("wierd epmode %d\n", ep->epmode);
  904. }
  905. }
  906. static void
  907. eptenable(Ctlr *ub, Endpt *ep, int dirin)
  908. {
  909. ED *ed;
  910. Endptx *epx;
  911. epx = ep->private;
  912. ed = epx->ed;
  913. if(EDgetH(ed) == 1){
  914. EDsetH(ed, 0);
  915. kickappropriatequeue(ub, ep, dirin);
  916. if(ep->epmode == Isomode || ep->epmode == Intrmode)
  917. waitSOF(ub);
  918. }
  919. }
  920. /*
  921. * return smallest power of 2 >= n
  922. */
  923. static int
  924. flog2(int n)
  925. {
  926. int i;
  927. for(i = 0; (1 << i) < n; i++)
  928. ;
  929. return i;
  930. }
  931. /*
  932. * return smallest power of 2 <= n
  933. */
  934. static int
  935. flog2lower(int n)
  936. {
  937. int i;
  938. for(i = 0; (1 << (i + 1)) <= n; i++)
  939. ;
  940. return i;
  941. }
  942. static int
  943. pickschedq(QTree *qt, int pollms, ulong bw, ulong limit)
  944. {
  945. int i, j, d, upperb, q;
  946. ulong best, worst, total;
  947. d = flog2lower(pollms);
  948. if(d > qt->depth)
  949. d = qt->depth;
  950. q = -1;
  951. worst = 0;
  952. best = ~0;
  953. upperb = (1 << (d+1)) - 1;
  954. for(i = (1 << d) - 1; i < upperb; i++){
  955. total = qt->bw[0];
  956. for(j = i; j > 0; j = (j - 1) / 2)
  957. total += qt->bw[j];
  958. if(total < best){
  959. best = total;
  960. q = i;
  961. }
  962. if(total > worst)
  963. worst = total;
  964. }
  965. if(worst + bw >= limit)
  966. return -1;
  967. return q;
  968. }
  969. static int
  970. schedendpt(Ctlr *ub, Endpt *ep, int dirin)
  971. {
  972. int q;
  973. ED *ed;
  974. Endptx *epx;
  975. epx = ep->private;
  976. qlock(ub->tree);
  977. /* TO DO: bus bandwidth limit */
  978. q = pickschedq(ub->tree, ep->pollms, ep->bw, ~0);
  979. XEPRINT("schedendpt, dir %d Q index %d, ms %d, bw %ld\n",
  980. dirin, q, ep->pollms, ep->bw);
  981. if(q < 0){
  982. qunlock(ub->tree);
  983. return -1;
  984. }
  985. ub->tree->bw[q] += ep->bw;
  986. ed = ub->tree->root[q];
  987. ep->sched = q;
  988. EDsetnext(epx->ed, EDgetnext(ed));
  989. EDsetnext(ed, epx->ed);
  990. XEPRINT("%d/%d: sched on q %d pollms %d\n",
  991. ep->dev->x, ep->x, q, ep->pollms);
  992. qunlock(ub->tree);
  993. return 0;
  994. }
  995. static void
  996. unschedendpt(Ctlr *ub, Endpt *ep, int dirin)
  997. {
  998. int q;
  999. ED *prev, *this, *next;
  1000. Endptx *epx;
  1001. epx = ep->private;
  1002. if((q = ep->sched) < 0)
  1003. return;
  1004. qlock(ub->tree);
  1005. ub->tree->bw[q] -= ep->bw;
  1006. prev = ub->tree->root[q];
  1007. this = EDgetnext(prev);
  1008. while(this != nil && this != epx->ed){
  1009. prev = this;
  1010. this = EDgetnext(this);
  1011. }
  1012. if(this == nil)
  1013. print("unschedendpt %d %d: not found\n", dirin, q);
  1014. else{
  1015. next = EDgetnext(this);
  1016. EDsetnext(prev, next);
  1017. }
  1018. qunlock(ub->tree);
  1019. }
  1020. /* at entry, *e is partly populated */
  1021. static void
  1022. epalloc(Usbhost *uh, Endpt *ep)
  1023. {
  1024. int id;
  1025. Endptx *epx;
  1026. Ctlr *ctlr;
  1027. Udev *d;
  1028. TD *dtd;
  1029. XEPRINT("ohci: epalloc from devusb\n");
  1030. ctlr = uh->ctlr;
  1031. id = ep->id;
  1032. d = ep->dev;
  1033. epx = malloc(sizeof(Endptx));
  1034. memset(epx, 0, sizeof(Endptx));
  1035. ep->private = epx;
  1036. dtd = nil;
  1037. if(waserror()){
  1038. XEPRINT("ohci: epalloc error\n");
  1039. EDfree(ctlr, epx->ed);
  1040. epx->ed = nil;
  1041. TDfree(ctlr, dtd);
  1042. nexterror();
  1043. }
  1044. if(epx->ed)
  1045. error("usb: already allocated");
  1046. if((epx->ed = EDalloc(ctlr)) == nil)
  1047. error(Enomem);
  1048. ep->bw = 1; /* all looks the same currently */
  1049. if((dtd = TDalloc(ctlr, ep, 0)) == nil)
  1050. error(Enomem);
  1051. EDinit(epx->ed, ep->maxpkt, 0, 0, 0, 0, id, d->id, dtd, dtd, 0, 0, 0);
  1052. XEPRINT("ohci: epalloc done\n");
  1053. poperror();
  1054. }
  1055. static void
  1056. epfree(Usbhost *uh, Endpt *ep)
  1057. {
  1058. Endptx *epx;
  1059. Ctlr *ctlr;
  1060. epx = ep->private;
  1061. ctlr = uh->ctlr;
  1062. XEPRINT("ohci: epfree %d/%d from devusb\n", ep->dev->x, ep->x);
  1063. if(ep->active)
  1064. panic("epfree: active");
  1065. EDfree(ctlr, epx->ed);
  1066. epx->ed = nil;
  1067. free(epx);
  1068. ep->private = nil;
  1069. }
  1070. static void
  1071. epopen(Usbhost *uh, Endpt *ep)
  1072. {
  1073. Ctlr *ctlr;
  1074. XEPRINT("ohci: epopen %d/%d from devusb\n", ep->dev->x, ep->x);
  1075. ctlr = uh->ctlr;
  1076. if((ep->epmode == Isomode || ep->epmode == Intrmode) && ep->active)
  1077. error("already open");
  1078. eptactivate(ctlr, ep);
  1079. }
  1080. static int
  1081. setfrnum(Ctlr *ub, Endpt *ep)
  1082. {
  1083. short frnum, d;
  1084. static int adj;
  1085. /* adjust frnum as necessary... */
  1086. frnum = ub->base->fmnumber + (ep->buffered*1000)/ep->bw;
  1087. d = frnum - ep->frnum;
  1088. if(d < -100 || d > 100){
  1089. /* We'd play in the past */
  1090. if(0 && d > 1000)
  1091. /* We're more than a second off: */
  1092. print("d %d, done %d, started %d, buffered %d\n", d,
  1093. ep->dir[Dirout].xdone, ep->dir[Dirout].xstarted,
  1094. ep->buffered);
  1095. if(ep->dir[Dirout].xdone == ep->dir[Dirout].xstarted)
  1096. ep->buffered = adj = 0;
  1097. if(0 && (adj++ & 0xff) == 0)
  1098. print("adj %d %d\n", d, ep->buffered);
  1099. ep->frnum = ub->base->fmnumber + 10 + (ep->buffered*1000)/ep->bw;
  1100. ep->partial = 0;
  1101. return 1;
  1102. }
  1103. return 0;
  1104. }
  1105. static int
  1106. ceptdone(void *arg)
  1107. {
  1108. Endpt *ep;
  1109. ep = arg;
  1110. return ep->dir[Dirout].xdone - ep->dir[Dirout].xstarted >= 0
  1111. || ep->dir[Dirout].err;
  1112. }
  1113. static void
  1114. epclose(Usbhost *uh, Endpt *ep)
  1115. {
  1116. Ctlr *ctlr;
  1117. int xdone, part;
  1118. Endptx *epx;
  1119. XEPRINT("ohci: epclose %d/%d from devusb, %d buffered\n",
  1120. ep->dev->x, ep->x, ep->buffered);
  1121. ctlr = uh->ctlr;
  1122. epx = ep->private;
  1123. if(ep->epmode == Isomode && ep->active){
  1124. qlock(&ep->wlock);
  1125. if(ep->partial && setfrnum(ctlr, ep) == 0){
  1126. part = ep->partial;
  1127. memset(ep->bpartial->wp, 0, ep->maxpkt - ep->partial);
  1128. ep->bpartial->wp = ep->bpartial->rp + ep->maxpkt;
  1129. qtd(uh->ctlr, ep, Dirout, nil, ep->bpartial->rp,
  1130. ep->bpartial->wp, Otokout, TD_FLAGS_LAST);
  1131. XEPRINT("epclose: wrote partial block %d\n", part);
  1132. ep->partial = 0;
  1133. }
  1134. qunlock(&ep->wlock);
  1135. XEPRINT("epclose: wait for outstanding TDs, xdone %d"
  1136. ", xstarted %d, buffered %d, queued %d\n",
  1137. ep->dir[Dirout].xdone, ep->dir[Dirout].xstarted,
  1138. ep->buffered, ep->dir[Dirout].queued);
  1139. while(ep->dir[Dirout].err == nil
  1140. && (xdone = ep->dir[Dirout].xdone) - ep->dir[Dirout].xstarted < 0){
  1141. tsleep(&ep->dir[Dirout].rend, ceptdone, ep, 500);
  1142. if(xdone == ep->dir[Dirout].xdone){
  1143. print("no progress\n");
  1144. break;
  1145. }
  1146. }
  1147. if(ep->dir[Dirout].err)
  1148. XEPRINT("error: %s\n", ep->dir[Dirout].err);
  1149. if(ep->buffered)
  1150. XEPRINT("epclose: done waiting, xdone %d, xstarted %d, "
  1151. "buffered %d, queued %d\n",
  1152. ep->dir[Dirout].xdone, ep->dir[Dirout].xstarted,
  1153. ep->buffered, ep->dir[Dirout].queued);
  1154. }
  1155. lock(epx);
  1156. EDcancel(ctlr, epx->ed, 2);
  1157. unlock(epx);
  1158. if(ep->epmode == Isomode && ep->buffered)
  1159. XEPRINT("epclose: after cancelling, xdone %d, xstarted %d"
  1160. ", buffered %d, queued %d\n",
  1161. ep->dir[Dirout].xdone, ep->dir[Dirout].xstarted,
  1162. ep->buffered, ep->dir[Dirout].queued);
  1163. eptdeactivate(ctlr, ep);
  1164. }
  1165. static void
  1166. epmaxpkt(Usbhost *, Endpt *ep)
  1167. {
  1168. Endptx *epx;
  1169. epx = ep->private;
  1170. XEPRINT("ohci: epmaxpkt %d/%d: %d\n",
  1171. ep->dev->x, ep->x, ep->maxpkt);
  1172. EDsetMPS(epx->ed, ep->maxpkt);
  1173. }
  1174. static void
  1175. epmode(Usbhost *uh, Endpt *ep)
  1176. {
  1177. int tok, reactivate;
  1178. Ctlr *ctlr;
  1179. Endptx *epx;
  1180. epx = ep->private;
  1181. ctlr = uh->ctlr;
  1182. XEPRINT("ohci: epmode %d/%d %s → %s\n",
  1183. ep->dev->x, ep->x, usbmode[ep->epmode], usbmode[ep->epnewmode]);
  1184. reactivate = 0;
  1185. if(ep->epnewmode != ep->epmode)
  1186. if(reactivate = ep->active){
  1187. XEPRINT("ohci: epmode %d/%d: already open\n",
  1188. ep->dev->x, ep->x);
  1189. eptdeactivate(ctlr, ep);
  1190. }
  1191. EDsetS(epx->ed, ep->dev->speed);
  1192. switch(ep->epnewmode){
  1193. default:
  1194. panic("devusb is sick");
  1195. case Intrmode:
  1196. // ep->debug++;
  1197. ep->bw = ep->maxpkt*1000/ep->pollms; /* bytes/sec */
  1198. XEPRINT("ohci: epmode %d/%d %s, intr: maxpkt %d, pollms %d, bw %ld\n",
  1199. ep->dev->x, ep->x, ousbmode[ep->mode],
  1200. ep->maxpkt, ep->pollms, ep->bw);
  1201. break;
  1202. case Isomode:
  1203. // ep->debug++;
  1204. ep->rem = 999;
  1205. switch(ep->mode){
  1206. default:
  1207. panic("ep mode");
  1208. case ORDWR:
  1209. error("iso unidirectional only");
  1210. case OREAD:
  1211. tok = Otokin;
  1212. error("iso read not implemented");
  1213. break;
  1214. case OWRITE:
  1215. tok = Otokout;
  1216. break;
  1217. }
  1218. XEPRINT("ohci: epmode %d/%d %s, iso: maxpkt %d, pollms %d, hz %d, samp %d\n",
  1219. ep->dev->x, ep->x, ousbmode[ep->mode],
  1220. ep->maxpkt, ep->pollms, ep->hz, ep->samplesz);
  1221. ep->bw = ep->hz * ep->samplesz; /* bytes/sec */
  1222. /* Use Iso TDs: */
  1223. epx->ed->ctrl |= ED_F_BIT;
  1224. /* Set direction in ED, no room in an Iso TD for this */
  1225. epx->ed->ctrl &= ~(ED_D_MASK << ED_D_SHIFT);
  1226. epx->ed->ctrl |= tok << ED_D_SHIFT;
  1227. break;
  1228. case Bulkmode:
  1229. // ep->debug++;
  1230. /*
  1231. * Each Bulk device gets a queue head hanging off the
  1232. * bulk queue head
  1233. */
  1234. break;
  1235. case Ctlmode:
  1236. break;
  1237. }
  1238. ep->epmode = ep->epnewmode;
  1239. epmaxpkt(uh, ep);
  1240. if(reactivate){
  1241. XEPRINT("ohci: epmode %d/%d: reactivate\n", ep->dev->x, ep->x);
  1242. eptactivate(ctlr, ep);
  1243. }
  1244. }
  1245. static long
  1246. qtd(Ctlr *ub, Endpt *ep, int dirin , Block *bp, uchar *base, uchar *limit,
  1247. int pid, ulong flags)
  1248. {
  1249. int fc, mps;
  1250. ulong x;
  1251. uchar *p;
  1252. ED *ed;
  1253. Endptx *epx;
  1254. TD *dummytd, *td;
  1255. epx = ep->private;
  1256. ed = epx->ed;
  1257. td = hcva2ucva(ed->tail);
  1258. td->flags = flags;
  1259. if(ep->epmode == Isomode){
  1260. x = va2hcva(base);
  1261. td->cbp = x & ~0xfff;
  1262. x &= 0xfff;
  1263. p = base;
  1264. setfrnum(ub, ep);
  1265. td->ctrl = ep->frnum & 0xffff;
  1266. fc = 0;
  1267. for(;;){
  1268. /* Calculate number of samples in next packet */
  1269. mps = (ep->hz + ep->rem)/1000;
  1270. /* rem is the partial sample left over */
  1271. ep->rem += ep->hz - 1000*mps;
  1272. mps *= ep->samplesz;
  1273. if(mps > ep->maxpkt)
  1274. panic("Packet size");
  1275. if(ep->partial == 0 && mps > limit - p){
  1276. /* Save this data for later ... */
  1277. ep->partial = limit - p;
  1278. if(fc-- == 0)
  1279. return p - base; /* No TD */
  1280. /* We do have a TD, send this one off normally */
  1281. td->flags |= TD_FLAGS_LAST;
  1282. break;
  1283. }else if(mps >= limit - p){
  1284. td->flags |= TD_FLAGS_LAST;
  1285. mps = limit - p;
  1286. ep->partial = 0;
  1287. }
  1288. td->offsets[fc] = 0xe000 | x;
  1289. x += mps;
  1290. p += mps;
  1291. ep->frnum++;
  1292. if(fc == 7 || limit - p == 0)
  1293. break;
  1294. fc++;
  1295. }
  1296. td->ctrl |= fc << 24;
  1297. }else{
  1298. td->cbp = va2hcva(base);
  1299. td->ctrl = (pid & TD_DP_MASK) << TD_DP_SHIFT;
  1300. p = base;
  1301. mps = 0x2000 - ((ulong)p & 0xfff);
  1302. if(mps > ep->maxpkt)
  1303. mps = ep->maxpkt;
  1304. if(mps >= limit - p){
  1305. mps = limit - base;
  1306. td->flags |= TD_FLAGS_LAST;
  1307. }
  1308. p += mps;
  1309. }
  1310. td->be = va2hcva(p == nil? nil: p - 1);
  1311. td->ep = ep;
  1312. td->bytes = p - base;
  1313. ep->buffered += td->bytes;
  1314. td->bp = bp;
  1315. if(td->flags & TD_FLAGS_LAST)
  1316. ep->dir[dirin].xstarted++;
  1317. if(dirin == Dirout && bp)
  1318. _xinc(&bp->ref);
  1319. dummytd = TDalloc(ub, ep, 1);
  1320. TDsetnexttd(td, dummytd);
  1321. ep->dir[dirin].queued++;
  1322. EDsettail(ed, dummytd);
  1323. if(usbhdebug || ep->debug)
  1324. dumptd(td, "qtd: before");
  1325. kickappropriatequeue(ub, ep, dirin);
  1326. return p - base;
  1327. }
  1328. Block*
  1329. allocrcvb(long size)
  1330. {
  1331. Block *b;
  1332. int asize;
  1333. asize = ROUND(size, dcls) + dcls - 1;
  1334. /*
  1335. * allocate enough to align rp to dcls, and have an integral number
  1336. * of cache lines in the buffer
  1337. */
  1338. while(waserror())
  1339. tsleep(&up->sleep, return0, 0, 100);
  1340. b = allocb(asize);
  1341. poperror();
  1342. /*
  1343. * align the rp and wp
  1344. */
  1345. b->rp = b->wp = (uchar *)ROUND((ulong)b->rp, dcls);
  1346. /*
  1347. * invalidate the cache lines which enclose the buffer
  1348. */
  1349. if(IOCACHED){
  1350. uchar *p;
  1351. p = b->rp;
  1352. while(size > 0){
  1353. invalidatedcacheva((ulong)p);
  1354. p += dcls;
  1355. size -= dcls;
  1356. }
  1357. }
  1358. return b;
  1359. }
  1360. /*
  1361. * build the periodic scheduling tree:
  1362. * framesize must be a multiple of the tree size
  1363. */
  1364. static QTree *
  1365. mkqhtree(Ctlr *ub)
  1366. {
  1367. int i, n, d, o, leaf0, depth;
  1368. ED **tree;
  1369. QTree *qt;
  1370. depth = flog2(32);
  1371. n = (1 << (depth+1)) - 1;
  1372. qt = mallocz(sizeof(*qt), 1);
  1373. if(qt == nil)
  1374. return nil;
  1375. qt->nel = n;
  1376. qt->depth = depth;
  1377. qt->bw = mallocz(n * sizeof(qt->bw), 1);
  1378. if(qt->bw == nil){
  1379. free(qt);
  1380. return nil;
  1381. }
  1382. tree = mallocz(n * sizeof(ED *), 1);
  1383. if(tree == nil){
  1384. free(qt->bw);
  1385. free(qt);
  1386. return nil;
  1387. }
  1388. for(i = 0; i < n; i++)
  1389. if((tree[i] = EDalloc(ub)) == nil)
  1390. break;
  1391. if(i < n){
  1392. int j;
  1393. for(j = 0; j < i; j++)
  1394. EDfree(ub, tree[j]);
  1395. free(tree);
  1396. free(qt->bw);
  1397. free(qt);
  1398. return nil;
  1399. }
  1400. qt->root = tree;
  1401. EDinit(qt->root[0], 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  1402. for(i = 1; i < n; i++)
  1403. EDinit(tree[i], 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, tree[(i-1)/2]);
  1404. /* distribute leaves evenly round the frame list */
  1405. leaf0 = n / 2;
  1406. for(i = 0; i < 32; i++){
  1407. o = 0;
  1408. for(d = 0; d < depth; d++){
  1409. o <<= 1;
  1410. if(i & (1 << d))
  1411. o |= 1;
  1412. }
  1413. if(leaf0 + o >= n){
  1414. print("leaf0=%d o=%d i=%d n=%d\n", leaf0, o, i, n);
  1415. break;
  1416. }
  1417. ub->uchcca->intrtable[i] = va2hcva(tree[leaf0 + o]);
  1418. }
  1419. return qt;
  1420. }
  1421. static void
  1422. portreset(Usbhost *uh, int port)
  1423. {
  1424. Ctlr *ctlr;
  1425. XIPRINT("ohci: portreset(port %d) from devusb\n", port);
  1426. ctlr = uh->ctlr;
  1427. /* should check that device not being configured on other port? */
  1428. qlock(&ctlr->resetl);
  1429. if(waserror()){
  1430. qunlock(&ctlr->resetl);
  1431. nexterror();
  1432. }
  1433. ilock(ctlr);
  1434. ctlr->base->rhportsts[port - 1] = Spp | Spr;
  1435. while((ctlr->base->rhportsts[port - 1] & Prsc) == 0){
  1436. iunlock(ctlr);
  1437. XIPRINT("ohci: portreset, wait for reset complete\n");
  1438. ilock(ctlr);
  1439. }
  1440. ctlr->base->rhportsts[port - 1] = Prsc;
  1441. iunlock(ctlr);
  1442. poperror();
  1443. qunlock(&ctlr->resetl);
  1444. }
  1445. static void
  1446. portenable(Usbhost *uh, int port, int on)
  1447. {
  1448. Ctlr *ctlr;
  1449. XIPRINT("ohci: portenable(port %d, on %d) from devusb\n", port, on);
  1450. ctlr = uh->ctlr;
  1451. /* should check that device not being configured on other port? */
  1452. qlock(&ctlr->resetl);
  1453. if(waserror()){
  1454. qunlock(&ctlr->resetl);
  1455. nexterror();
  1456. }
  1457. ilock(ctlr);
  1458. if(on)
  1459. ctlr->base->rhportsts[port - 1] = Spe | Spp;
  1460. else
  1461. ctlr->base->rhportsts[port - 1] = Cpe;
  1462. iunlock(ctlr);
  1463. poperror();
  1464. qunlock(&ctlr->resetl);
  1465. }
  1466. static int
  1467. getportstatus(Ctlr *ub, int port)
  1468. {
  1469. int v;
  1470. ulong ohcistatus;
  1471. ohcistatus = ub->base->rhportsts[port - 1];
  1472. v = 0;
  1473. if(ohcistatus & Ccs)
  1474. v |= DevicePresent;
  1475. if(ohcistatus & Pes)
  1476. v |= PortEnable;
  1477. if(ohcistatus & Pss)
  1478. v |= Suspend;
  1479. if(ohcistatus & Prs)
  1480. v |= PortReset;
  1481. else {
  1482. /* port is not in reset; these potential writes are ok */
  1483. if(ohcistatus & Csc){
  1484. /* TODO: could notify usbd equivalent here */
  1485. v |= ConnectStatusChange;
  1486. ub->base->rhportsts[port - 1] = Csc;
  1487. }
  1488. if(ohcistatus & Pesc){
  1489. /* TODO: could notify usbd equivalent here */
  1490. v |= PortEnableChange;
  1491. ub->base->rhportsts[port - 1] = Pesc;
  1492. }
  1493. }
  1494. if(ohcistatus & Lsda)
  1495. v |= SlowDevice;
  1496. if(ohcistatus & Ccs)
  1497. XIPRINT("portstatus(%d) = OHCI 0x%.8lux UHCI 0x%.8ux\n",
  1498. port, ohcistatus, v);
  1499. return v;
  1500. }
  1501. /* print any interesting stuff here for debugging purposes */
  1502. static void
  1503. usbdebug(Usbhost *uh, char *s, char *se)
  1504. {
  1505. Udev *dev;
  1506. Endpt *ep;
  1507. int n, i, j;
  1508. n = 0;
  1509. for(i = 0; i < MaxUsbDev; i++)
  1510. if(uh->dev[i])
  1511. n++;
  1512. s = seprint(s, se, "OHCI, %d devices\n", n);
  1513. for(i = 0; i < MaxUsbDev; i++){
  1514. if((dev = uh->dev[i]) == nil)
  1515. continue;
  1516. s = seprint(s, se, "dev 0x%6.6lux, %d epts\n", dev->csp, dev->npt);
  1517. for(j = 0; j < nelem(dev->ep); j++){
  1518. if((ep = dev->ep[j]) == nil)
  1519. continue;
  1520. if(ep->epmode >= 0 && ep->epmode < Nmodes)
  1521. s = seprint(s, se, "ept %d/%d: %s 0x%6.6lux "
  1522. "maxpkt %d %s\n",
  1523. dev->x, ep->x, usbmode[ep->epmode],
  1524. ep->csp, ep->maxpkt, ep->active ? "active" : "idle");
  1525. else{
  1526. s = seprint(s, se, "ept %d/%d: bad mode 0x%6.6lux\n",
  1527. dev->x, ep->x, ep->csp);
  1528. continue;
  1529. }
  1530. switch(ep->epmode){
  1531. case Nomode:
  1532. break;
  1533. case Ctlmode:
  1534. break;
  1535. case Bulkmode:
  1536. break;
  1537. case Intrmode:
  1538. s = seprint(s, se, "\t%d ms\n",
  1539. ep->pollms);
  1540. break;
  1541. case Isomode:
  1542. s = seprint(s, se, "\t%d ms, remain %d, "
  1543. "partial %d, buffered %d, "
  1544. "xdone %d, xstarted %d, err %s\n",
  1545. ep->pollms, ep->remain, ep->partial,
  1546. ep->buffered,
  1547. ep->dir[ep->mode == OREAD].xdone,
  1548. ep->dir[ep->mode == OREAD].xstarted,
  1549. ep->dir[ep->mode == OREAD].err
  1550. ? ep->dir[ep->mode == OREAD].err : "no");
  1551. break;
  1552. }
  1553. }
  1554. }
  1555. }
  1556. /* this is called several times every few seconds, possibly due to usbd */
  1557. static void
  1558. portinfo(Usbhost *uh, char *s, char *se)
  1559. {
  1560. int x, i, j;
  1561. Ctlr *ctlr;
  1562. XIPRINT("ohci: portinfo from devusb\n");
  1563. ctlr = uh->ctlr;
  1564. for(i = 1; i <= ctlr->nports; i++){
  1565. ilock(ctlr);
  1566. x = getportstatus(ctlr, i);
  1567. iunlock(ctlr);
  1568. s = seprint(s, se, "%d %ux", i, x);
  1569. for(j = 0; j < nelem(portstatus); j++)
  1570. if((x & portstatus[j].bit) != 0)
  1571. s = seprint(s, se, " %s", portstatus[j].name);
  1572. s = seprint(s, se, "\n");
  1573. }
  1574. }
  1575. void
  1576. interrupt(Ureg *, void *arg)
  1577. {
  1578. int dirin, cc;
  1579. ulong ctrl, status;
  1580. uchar *p;
  1581. Block *bp;
  1582. Ctlr *ub;
  1583. Endpt *ep;
  1584. Endptx *epx;
  1585. TD *donetd, *nexttd;
  1586. Usbhost *eh;
  1587. XIPRINT("ohci: interrupt\n");
  1588. eh = arg;
  1589. ub = eh->ctlr;
  1590. status = ub->base->intrsts;
  1591. status &= ub->base->intrenable;
  1592. status &= Oc | Rhsc | Fno
  1593. | Ue
  1594. | Rd | Sf | Wdh
  1595. | So;
  1596. if(status & Wdh){
  1597. /* LSb of donehead has bit that says there are other interrupts */
  1598. donetd = hcva2ucva(ub->uchcca->donehead & ~0xf);
  1599. XIPRINT("donetd 0x%.8lux\n", donetd);
  1600. }else
  1601. donetd = 0;
  1602. ub->base->intrsts = status;
  1603. status &= ~Wdh;
  1604. while(donetd){
  1605. ctrl = donetd->ctrl;
  1606. ep = donetd->ep;
  1607. bp = donetd->bp;
  1608. donetd->bp = nil;
  1609. epx = ep->private;
  1610. ohciinterrupts[ep->epmode]++;
  1611. dirin = ((ctrl >> TD_DP_SHIFT) & TD_DP_MASK) == Otokin;
  1612. ep->buffered -= donetd->bytes;
  1613. if(ep->epmode == Isomode){
  1614. dirin = Dirout;
  1615. if(ep->buffered < 0){
  1616. print("intr: buffered %d bytes %ld\n",
  1617. ep->buffered, donetd->bytes);
  1618. ep->buffered = 0;
  1619. }
  1620. }
  1621. cc = (ctrl >> TD_CC_SHIFT) & TD_CC_MASK;
  1622. if((usbhdebug || ep->debug) && (cc != 0 && cc != 9)){
  1623. print("%d/%d: cc %d frnum 0x%lux\n",
  1624. ep->dev->x, ep->x, cc, ub->base->fmnumber);
  1625. dumptd(donetd, "after");
  1626. }
  1627. switch(cc){
  1628. case 8: /* Overrun, Not an error */
  1629. epx->overruns++;
  1630. /* fall through to no error code */
  1631. case 0: /* noerror */
  1632. if((donetd->flags & TD_FLAGS_LAST) == 0)
  1633. break;
  1634. if(dirin){
  1635. if(bp){
  1636. p = hcva2va(donetd->be + 1);
  1637. if(p < bp->wp)
  1638. print("interrupt: bp: rp 0x%lux"
  1639. ", wp 0x%lux→0x%lux\n",
  1640. bp->rp, bp->wp, p);
  1641. bp->wp = p;
  1642. }
  1643. }
  1644. ep->dir[dirin].xdone++;
  1645. wakeup(&ep->dir[dirin].rend);
  1646. break;
  1647. case 9: /* underrun */
  1648. if(bp){
  1649. p = hcva2va(donetd->cbp);
  1650. XEIPRINT("interrupt: bp: rp 0x%lux, wp "
  1651. "0x%lux→0x%lux\n", bp->rp, bp->wp, p);
  1652. bp->wp = p;
  1653. }
  1654. if((donetd->flags & TD_FLAGS_LAST) == 0){
  1655. XEIPRINT("Underrun\n");
  1656. ep->dir[dirin].err = Eunderrun;
  1657. }
  1658. ep->dir[dirin].xdone++;
  1659. wakeup(&ep->dir[dirin].rend);
  1660. break;
  1661. case 1: /* CRC */
  1662. ep->dir[dirin].err = "CRC error";
  1663. goto error;
  1664. case 2: /* Bitstuff */
  1665. ep->dir[dirin].err = "Bitstuff error";
  1666. goto error;
  1667. case 3:
  1668. ep->dir[dirin].err = "data toggle mismatch";
  1669. goto error;
  1670. case 4: /* Stall */
  1671. ep->dir[dirin].err = Estalled;
  1672. goto error;
  1673. case 5: /* No response */
  1674. ep->dir[dirin].err = "No response";
  1675. goto error;
  1676. case 6: /* PIDcheck */
  1677. ep->dir[dirin].err = "PIDcheck";
  1678. goto error;
  1679. case 7: /* UnexpectedPID */
  1680. ep->dir[dirin].err = "badPID";
  1681. goto error;
  1682. error:
  1683. XEPRINT("fail %d (%lud)\n", cc,
  1684. (ctrl >> TD_EC_SHIFT) & TD_EC_MASK);
  1685. ep->dir[dirin].xdone++;
  1686. wakeup(&ep->dir[dirin].rend);
  1687. break;
  1688. default:
  1689. panic("cc %ud unimplemented\n", cc);
  1690. }
  1691. ep->dir[dirin].queued--;
  1692. /* Clean up blocks used for transfers */
  1693. if(dirin == Dirout)
  1694. freeb(bp);
  1695. nexttd = TDgetnexttd(donetd);
  1696. TDfree(ub, donetd);
  1697. donetd = nexttd;
  1698. }
  1699. if(status & Sf){
  1700. if (0)
  1701. XIPRINT(("sof!!\n"));
  1702. // wakeup(&ub->sofr); /* sofr doesn't exist anywhere! */
  1703. status &= ~Sf;
  1704. }
  1705. if(status & Ue){
  1706. ulong curred;
  1707. // usbhdbg(); /* TODO */
  1708. curred = ub->base->periodcurred;
  1709. print("usbh: unrecoverable error frame 0x%.8lux ed 0x%.8lux, "
  1710. "ints %d %d %d %d\n",
  1711. ub->base->fmnumber, curred,
  1712. ohciinterrupts[1], ohciinterrupts[2],
  1713. ohciinterrupts[3], ohciinterrupts[4]);
  1714. if(curred)
  1715. dumped(hcva2ucva(curred));
  1716. }
  1717. if(status)
  1718. IPRINT(("interrupt: unhandled interrupt 0x%.8lux\n", status));
  1719. }
  1720. static void
  1721. usbhattach(Ctlr *ub) /* TODO: is unused now, but it fiddles ctlr */
  1722. {
  1723. ulong ctrl;
  1724. if(ub == nil || ub->base == 0)
  1725. error(Enodev);
  1726. ctrl = ub->base->control;
  1727. if((ctrl & HcfsMask) != HcfsOperational){
  1728. ctrl = (ctrl & ~HcfsMask) | HcfsOperational;
  1729. ub->base->control = ctrl;
  1730. ub->base->rhsts = Sgp;
  1731. }
  1732. }
  1733. static int
  1734. reptdone(void *arg)
  1735. {
  1736. Endpt *ep;
  1737. ep = arg;
  1738. return ep->dir[Dirin].err
  1739. /* Expression crafted to deal with wrap around: */
  1740. || ep->dir[Dirin].xdone - ep->dir[Dirin].xstarted >= 0;
  1741. }
  1742. Block *
  1743. breadusbh(Ctlr *ub, Endpt *ep, long n) /* guts of read() */
  1744. {
  1745. long in, l;
  1746. uchar *p;
  1747. Block *bp;
  1748. Endptx *epx;
  1749. epx = ep->private;
  1750. qlock(&ep->rlock);
  1751. EDsetC(epx->ed, ep->rdata01);
  1752. XEPRINT("breadusbh(%d/%d, %ld, dt %d)\n", ep->dev->x, ep->x, n, ep->rdata01);
  1753. eptenable(ub, ep, Dirin);
  1754. if(waserror()){
  1755. EDcancel(ub, epx->ed, Dirin);
  1756. ep->dir[Dirin].err = nil;
  1757. qunlock(&ep->rlock);
  1758. nexterror();
  1759. }
  1760. if(ep->dir[Dirin].err != nil)
  1761. error("usb: can't happen");
  1762. bp = allocrcvb(n);
  1763. in = n;
  1764. if(in > bp->lim - bp->wp){
  1765. print("usb: read larger than block\n");
  1766. in = bp->lim - bp->wp;
  1767. }
  1768. p = bp->rp;
  1769. do{
  1770. l = qtd(ub, ep, Dirin, bp, p, p+in, Otokin, 0);
  1771. p += l;
  1772. in -= l;
  1773. }while(in > 0);
  1774. sleep(&ep->dir[Dirin].rend, reptdone, ep);
  1775. if(ep->dir[Dirin].err){
  1776. EDcancel(ub, epx->ed, Dirin);
  1777. if(ep->dir[Dirin].err == Eunderrun)
  1778. ep->dir[Dirin].err = nil;
  1779. else
  1780. error(ep->dir[Dirin].err);
  1781. }
  1782. XEPRINT("breadusbh(%d/%d, %ld) returned %ld\n", ep->dev->x, ep->x, n,
  1783. BLEN(bp));
  1784. poperror();
  1785. qunlock(&ep->rlock);
  1786. ep->rdata01 = EDgetC(epx->ed);
  1787. return bp;
  1788. }
  1789. static long
  1790. read(Usbhost *uh, Endpt *ep, void *a, long n, vlong off) /* TODO off */
  1791. {
  1792. long l;
  1793. Block *bp;
  1794. Ctlr *ub;
  1795. XEPRINT("ohci: read from devusb\n");
  1796. USED(off);
  1797. ub = uh->ctlr;
  1798. XEPRINT("%d/%d: read 0x%.8lux %ld\n", ep->dev->x, ep->x, a, n);
  1799. bp = breadusbh(ub, ep, n);
  1800. l = BLEN(bp);
  1801. memmove(a, bp->rp, l);
  1802. printdata(bp->rp, 1, l);
  1803. XEPRINT("ohci: read %ld\n\n", l);
  1804. freeb(bp);
  1805. return l;
  1806. }
  1807. static int
  1808. weptdone(void *arg)
  1809. {
  1810. Endpt *ep;
  1811. ep = arg;
  1812. /*
  1813. * success when all operations are done or when less than
  1814. * a second is buffered in iso connections
  1815. */
  1816. return ep->dir[Dirout].xdone - ep->dir[Dirout].xstarted >= 0
  1817. || (ep->epmode == Isomode && ep->buffered <= ep->bw)
  1818. || ep->dir[Dirout].err;
  1819. }
  1820. /* TODO: honour off */
  1821. static long
  1822. write(Usbhost *uh, Endpt *ep, void *a, long n, vlong off, int tok)
  1823. {
  1824. long m;
  1825. short frnum;
  1826. uchar *p = a;
  1827. Block *b;
  1828. Ctlr *ub;
  1829. Endptx *epx;
  1830. XEPRINT("ohci: write(addr %p, bytes %ld, off %lld, tok %d) from devusb\n",
  1831. a, n, off, tok);
  1832. epx = ep->private;
  1833. ub = uh->ctlr;
  1834. qlock(&ep->wlock);
  1835. XEPRINT("%d/%d: write 0x%.8lux %ld %s\n", ep->dev->x, ep->x, a, n,
  1836. tok == Otoksetup? "setup": "out");
  1837. if(ep->dir[Dirout].xdone - ep->dir[Dirout].xstarted > 0){
  1838. print("done > started, %d %d\n",
  1839. ep->dir[Dirout].xdone, ep->dir[Dirout].xstarted);
  1840. ep->dir[Dirout].xdone = ep->dir[Dirout].xstarted;
  1841. }
  1842. if(waserror()){
  1843. lock(epx);
  1844. EDcancel(ub, epx->ed, Dirout);
  1845. unlock(epx);
  1846. ep->dir[Dirout].err = nil;
  1847. qunlock(&ep->wlock);
  1848. nexterror();
  1849. }
  1850. eptenable(ub, ep, Dirout);
  1851. EDsetC(epx->ed, ep->wdata01);
  1852. if(ep->dir[Dirout].err)
  1853. error(ep->dir[Dirout].err);
  1854. if((m = n) == 0 || p == nil)
  1855. qtd(ub, ep, Dirout, 0, 0, 0, tok, TD_FLAGS_LAST);
  1856. else{
  1857. b = allocb(m+ep->partial);
  1858. if(ep->partial){
  1859. memmove(b->wp, ep->bpartial->rp, ep->partial);
  1860. b->wp += ep->partial;
  1861. ep->partial = 0;
  1862. }
  1863. validaddr((uintptr)p, m, 0); /* DEBUG */
  1864. memmove(b->wp, a, m);
  1865. b->wp += m;
  1866. printdata(b->rp, 1, m);
  1867. m = BLEN(b);
  1868. dcclean(b->rp, m);
  1869. if(ep->epmode == Isomode && ep->buffered <= ep->bw<<1){
  1870. sleep(&ep->dir[Dirout].rend, weptdone, ep);
  1871. if(ep->dir[Dirout].err)
  1872. error(ep->dir[Dirout].err);
  1873. }
  1874. while(m > 0){
  1875. int l;
  1876. l = qtd(ub, ep, Dirout, b, b->rp, b->wp, tok, 0);
  1877. b->rp += l;
  1878. m -= l;
  1879. tok = Otokout;
  1880. if(ep->partial){
  1881. /* We have some data to save */
  1882. if(ep->bpartial == nil)
  1883. ep->bpartial = allocb(ep->maxpkt);
  1884. if(ep->partial != m)
  1885. print("curious: %d != %ld\n",
  1886. ep->partial, m);
  1887. memmove(ep->bpartial->rp, b->rp, ep->partial);
  1888. ep->bpartial->wp = ep->bpartial->rp + ep->partial;
  1889. break;
  1890. }
  1891. }
  1892. freeb(b); /* qtd calls incref; this undoes the one too many */
  1893. }
  1894. if(ep->epmode != Isomode){
  1895. sleep(&ep->dir[Dirout].rend, weptdone, ep);
  1896. if(ep->dir[Dirout].err)
  1897. error(ep->dir[Dirout].err);
  1898. }else if(0 && (frnum = ep->frnum - ub->base->fmnumber) < 0)
  1899. print("too late %d\n", frnum);
  1900. poperror();
  1901. qunlock(&ep->wlock);
  1902. XEPRINT("ohci: wrote %ld\n\n", n);
  1903. ep->wdata01 = EDgetC(epx->ed);
  1904. return n;
  1905. }
  1906. static void
  1907. init(Usbhost*)
  1908. {
  1909. XIPRINT("ohci: init from devusb\n");
  1910. }
  1911. static void
  1912. scanpci(void)
  1913. {
  1914. ulong mem;
  1915. Ctlr *ctlr;
  1916. Pcidev *p;
  1917. static int already = 0;
  1918. if(already)
  1919. return;
  1920. already = 1;
  1921. p = nil;
  1922. while(p = pcimatch(p, 0, 0)) {
  1923. /*
  1924. * Find OHCI controllers (Programming Interface = 0x10).
  1925. */
  1926. if(p->ccrb != Pcibcserial || p->ccru != Pciscusb ||
  1927. p->ccrp != 0x10)
  1928. continue;
  1929. mem = p->mem[0].bar & ~0x0F;
  1930. XPRINT("usbohci: %x/%x port 0x%lux size 0x%x irq %d\n",
  1931. p->vid, p->did, mem, p->mem[0].size, p->intl);
  1932. if(mem == 0){
  1933. print("usbohci: failed to map registers\n");
  1934. continue;
  1935. }
  1936. if(p->intl == 0xFF || p->intl == 0) {
  1937. print("usbohci: no irq assigned for port %#lux\n", mem);
  1938. continue;
  1939. }
  1940. ctlr = malloc(sizeof(Ctlr));
  1941. ctlr->pcidev = p;
  1942. ctlr->base = vmap(mem, p->mem[0].size);
  1943. XPRINT("scanpci: ctlr 0x%lux, base 0x%lux\n", ctlr, ctlr->base);
  1944. pcisetbme(p);
  1945. pcisetpms(p, 0);
  1946. if(ctlrhead != nil)
  1947. ctlrtail->next = ctlr;
  1948. else
  1949. ctlrhead = ctlr;
  1950. ctlrtail = ctlr;
  1951. }
  1952. }
  1953. static int
  1954. reset(Usbhost *uh)
  1955. {
  1956. int i, linesize;
  1957. ulong io, fminterval, ctrl;
  1958. Ctlr *ctlr;
  1959. HCCA *atmp;
  1960. OHCI *ohci;
  1961. Pcidev *p;
  1962. QTree *qt;
  1963. /*
  1964. * data cache line size; probably doesn't matter on pc
  1965. * except that it must be a power of 2 for xspanalloc.
  1966. */
  1967. dcls = 32;
  1968. scanpci();
  1969. /*
  1970. * Any adapter matches if no uh->port is supplied,
  1971. * otherwise the ports must match.
  1972. */
  1973. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  1974. if(ctlr->active)
  1975. continue;
  1976. if(uh->port == 0 || uh->port == (uintptr)ctlr->base){
  1977. ctlr->active = 1;
  1978. break;
  1979. }
  1980. }
  1981. if(ctlr == nil)
  1982. return -1;
  1983. io = (uintptr)ctlr->base; /* TODO: correct? */
  1984. ohci = ctlr->base;
  1985. XPRINT("OHCI ctlr 0x%lux, base 0x%lux\n", ctlr, ohci);
  1986. p = ctlr->pcidev;
  1987. uh->ctlr = ctlr;
  1988. uh->port = io;
  1989. uh->irq = p->intl;
  1990. uh->tbdf = p->tbdf;
  1991. XPRINT("OHCI revision %ld.%ld\n", (ohci->revision >> 4) & 0xf,
  1992. ohci->revision & 0xf);
  1993. XPRINT("Host revision %ld.%ld\n", (ohci->hostrevision >> 4) & 0xf,
  1994. ohci->hostrevision & 0xf);
  1995. ctlr->nports = ohci->rhdesca & 0xff;
  1996. XPRINT("HcControl 0x%.8lux, %d ports\n", ohci->control, ctlr->nports);
  1997. delay(100); /* anything greater than 50 should ensure reset is done */
  1998. if(ohci->control == ~0){
  1999. ctlrhead = nil;
  2000. return -1;
  2001. }
  2002. /*
  2003. * usually enter here in reset, wait till its through,
  2004. * then do our own so we are on known timing conditions.
  2005. */
  2006. ohci->control = 0;
  2007. delay(100);
  2008. fminterval = ohci->fminterval;
  2009. /* legacy support register: turn off lunacy mode */
  2010. pcicfgw16(p, 0xc0, 0x2000);
  2011. /*
  2012. * transfer descs need at least 16 byte alignment, but
  2013. * align to dcache line size since the access will always be uncached.
  2014. * linesize must be a power of 2 for xspanalloc.
  2015. */
  2016. linesize = dcls;
  2017. if(linesize < 0x20)
  2018. linesize = 0x20;
  2019. ctlr->td.pool = va2ucva(xspanalloc(Ntd * sizeof(TD), linesize, 0));
  2020. if(ctlr->td.pool == nil)
  2021. panic("usbohci: no memory for TD pool");
  2022. for(i = Ntd - 1; --i >= 0;){
  2023. ctlr->td.pool[i].next = ctlr->td.free;
  2024. ctlr->td.free = &ctlr->td.pool[i];
  2025. }
  2026. ctlr->td.alloced = 0;
  2027. ctlr->ed.pool = va2ucva(xspanalloc(Ned*sizeof(ED), linesize, 0));
  2028. if(ctlr->ed.pool == nil)
  2029. panic("usbohci: no memory for ED pool");
  2030. for(i = Ned - 1; --i >= 0;){
  2031. ctlr->ed.pool[i].next = (ulong)ctlr->ed.free;
  2032. ctlr->ed.free = &ctlr->ed.pool[i];
  2033. }
  2034. ctlr->ed.alloced = 0;
  2035. atmp = xspanalloc(sizeof(HCCA), 256, 0);
  2036. if(atmp == nil)
  2037. panic("usbhreset: no memory for HCCA");
  2038. memset(atmp, 0, sizeof(*atmp));
  2039. ctlr->uchcca = atmp;
  2040. qt = mkqhtree(ctlr);
  2041. if(qt == nil){
  2042. panic("usb: can't allocate scheduling tree");
  2043. return -1;
  2044. }
  2045. ctlr->tree = qt;
  2046. ctlr->base = ohci;
  2047. /* time to move to rest then suspend mode. */
  2048. ohci->cmdsts = 1; /* reset the block */
  2049. while(ohci->cmdsts == 1)
  2050. continue; /* wait till reset complete, OHCI says 10us max. */
  2051. /*
  2052. * now that soft reset is done we are in suspend state.
  2053. * Setup registers which take in suspend state
  2054. * (will only be here for 2ms).
  2055. */
  2056. ohci->hcca = va2hcva(ctlr->uchcca);
  2057. OHCIsetControlHeadED(ctlr->base, 0);
  2058. ctlr->base->ctlcurred = 0;
  2059. OHCIsetBulkHeadED(ctlr->base, 0);
  2060. ctlr->base->bulkcurred = 0;
  2061. ohci->intrenable = Mie | Wdh | Ue;
  2062. ohci->control |= Cle | Ble | Ple | Ie | HcfsOperational;
  2063. /* set frame after operational */
  2064. ohci->fminterval = (fminterval &
  2065. ~(HcFmIntvl_FSMaxpack_MASK << HcFmIntvl_FSMaxpack_SHIFT)) |
  2066. 5120 << HcFmIntvl_FSMaxpack_SHIFT;
  2067. ohci->rhdesca = 1 << 9;
  2068. for(i = 0; i < ctlr->nports; i++)
  2069. ohci->rhportsts[i] = Spp | Spr;
  2070. delay(100);
  2071. ctrl = ohci->control;
  2072. if((ctrl & HcfsMask) != HcfsOperational){
  2073. XIPRINT("ohci: reset, take ctlr out of Suspend\n");
  2074. ctrl = (ctrl & ~HcfsMask) | HcfsOperational;
  2075. ohci->control = ctrl;
  2076. ohci->rhsts = Sgp;
  2077. }
  2078. p = ctlr->pcidev;
  2079. ctlr->irq = p->intl;
  2080. ctlr->tbdf = p->tbdf;
  2081. /*
  2082. * Linkage to the generic USB driver.
  2083. */
  2084. uh->init = init;
  2085. uh->interrupt = interrupt;
  2086. uh->debug = usbdebug;
  2087. uh->portinfo = portinfo;
  2088. uh->portreset = portreset;
  2089. uh->portenable = portenable;
  2090. uh->epalloc = epalloc;
  2091. uh->epfree = epfree;
  2092. uh->epopen = epopen;
  2093. uh->epclose = epclose;
  2094. uh->epmode = epmode;
  2095. uh->epmaxpkt = epmaxpkt;
  2096. uh->read = read;
  2097. uh->write = write;
  2098. uh->tokin = Otokin;
  2099. uh->tokout = Otokout;
  2100. uh->toksetup = Otoksetup;
  2101. return 0;
  2102. }
  2103. void
  2104. usbohcilink(void)
  2105. {
  2106. addusbtype("ohci", reset);
  2107. }