sdiahci.c 28 KB

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  1. /*
  2. * intel/amd ahci (advanced host controller interface) sata controller
  3. * bootstrap driver
  4. * copyright © 2007, 2008 coraid, inc.
  5. */
  6. #include "u.h"
  7. #include "lib.h"
  8. #include "mem.h"
  9. #include "dat.h"
  10. #include "fns.h"
  11. #include "io.h"
  12. #include "error.h"
  13. #include "sd.h"
  14. #include "ahci.h"
  15. #define dprint(...) if(debug == 1) print(__VA_ARGS__); else USED(debug)
  16. #define idprint(...) if(prid == 1) print(__VA_ARGS__); else USED(prid)
  17. #define aprint(...) if(datapi == 1) print(__VA_ARGS__); else USED(datapi)
  18. enum {
  19. NCtlr = 2,
  20. NCtlrdrv= 8,
  21. NDrive = NCtlr*NCtlrdrv,
  22. Read = 0,
  23. Write
  24. };
  25. /* pci space configurtion */
  26. enum {
  27. Pmap = 0x90,
  28. Ppcs = 0x91,
  29. Prev = 0xa8,
  30. };
  31. enum {
  32. Tesb,
  33. Tich,
  34. Tsb600,
  35. Tunk,
  36. };
  37. #define Intel(x) ((x)->pci->vid == 0x8086)
  38. static char *tname[] = {
  39. "63xxesb",
  40. "ich",
  41. "sb600",
  42. "unk",
  43. };
  44. enum {
  45. Dnull,
  46. Dmissing,
  47. Dnew,
  48. Dready,
  49. Derror,
  50. Dreset,
  51. Doffline,
  52. Dportreset,
  53. Dlast
  54. };
  55. static char *diskstates[Dlast] = {
  56. "null",
  57. "missing",
  58. "new",
  59. "ready",
  60. "error",
  61. "reset",
  62. "offline",
  63. "portreset",
  64. };
  65. extern SDifc sdiahciifc;
  66. typedef struct Ctlr Ctlr;
  67. enum {
  68. DMautoneg,
  69. DMsatai,
  70. DMsataii,
  71. };
  72. static char *modename[] = {
  73. "auto",
  74. "satai",
  75. "sataii",
  76. };
  77. typedef struct {
  78. Lock;
  79. Ctlr *ctlr;
  80. SDunit *unit;
  81. char name[10];
  82. Aport *port;
  83. Aportm portm;
  84. Aportc portc; /* redundant ptr to port and portm. */
  85. uchar mediachange;
  86. uchar state;
  87. uchar smartrs;
  88. uvlong sectors;
  89. ulong intick;
  90. int wait;
  91. uchar mode; /* DMautoneg, satai or sataii. */
  92. uchar active;
  93. char serial[20+1];
  94. char firmware[8+1];
  95. char model[40+1];
  96. ushort info[0x200];
  97. int driveno; /* ctlr*NCtlrdrv + unit */
  98. int portno; /* ctlr port # != drive # when not all ports enabled. */
  99. } Drive;
  100. struct Ctlr {
  101. Lock;
  102. int type;
  103. int enabled;
  104. SDev *sdev;
  105. Pcidev *pci;
  106. uchar *mmio;
  107. ulong *lmmio;
  108. Ahba *hba;
  109. Drive rawdrive[NCtlrdrv];
  110. Drive* drive[NCtlrdrv];
  111. int ndrive;
  112. int mport;
  113. };
  114. static Ctlr iactlr[NCtlr];
  115. static SDev sdevs[NCtlr];
  116. static int niactlr;
  117. static int prid = 0;
  118. static int datapi = 0;
  119. static char stab[] = {
  120. [0] 'i', 'm',
  121. [8] 't', 'c', 'p', 'e',
  122. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  123. };
  124. static void
  125. serrstr(ulong r, char *s, char *e)
  126. {
  127. int i;
  128. e -= 3;
  129. for(i = 0; i < nelem(stab) && s < e; i++)
  130. if((r & (1<<i)) && stab[i]){
  131. *s++ = stab[i];
  132. if(SerrBad & (1<<i))
  133. *s++ = '*';
  134. }
  135. *s = 0;
  136. }
  137. static char ntab[] = "0123456789abcdef";
  138. static void
  139. preg(uchar *reg, int n)
  140. {
  141. int i;
  142. char buf[25*3+1], *e;
  143. e = buf;
  144. for(i = 0; i < n; i++){
  145. *e++ = ntab[reg[i] >> 4];
  146. *e++ = ntab[reg[i] & 0xf];
  147. *e++ = ' ';
  148. }
  149. *e++ = '\n';
  150. *e = 0;
  151. dprint(buf);
  152. }
  153. static void
  154. dreg(char *s, Aport *p)
  155. {
  156. dprint("%stask=%lux; cmd=%lux; ci=%lux; is=%lux\n",
  157. s, p->task, p->cmd, p->ci, p->isr);
  158. }
  159. static void
  160. esleep(int ms)
  161. {
  162. delay(ms);
  163. }
  164. typedef struct {
  165. Aport *p;
  166. int i;
  167. } Asleep;
  168. static int
  169. ahciclear(void *v)
  170. {
  171. Asleep *s;
  172. s = v;
  173. return (s->p->ci & s->i) == 0;
  174. }
  175. static void
  176. aesleep(Aportm *, Asleep *a, int ms)
  177. {
  178. ulong start;
  179. start = m->ticks;
  180. while((a->p->ci & a->i) != 0)
  181. if(TK2MS(m->ticks-start) >= ms)
  182. break;
  183. }
  184. static int
  185. ahciwait(Aportc *c, int ms)
  186. {
  187. Aport *p;
  188. Asleep as;
  189. p = c->p;
  190. p->ci = 1;
  191. as.p = p;
  192. as.i = 1;
  193. aesleep(c->m, &as, ms);
  194. if((p->task & 1) == 0 && p->ci == 0)
  195. return 0;
  196. dreg("ahciwait timeout ", c->p);
  197. return -1;
  198. }
  199. static int
  200. setfeatures(Aportc *pc, uchar f)
  201. {
  202. uchar *c;
  203. Actab *t;
  204. Alist *l;
  205. t = pc->m->ctab;
  206. c = t->cfis;
  207. memset(c, 0, 0x20);
  208. c[0] = 0x27;
  209. c[1] = 0x80;
  210. c[2] = 0xef;
  211. c[3] = f;
  212. c[7] = 0xa0; /* obsolete device bits */
  213. l = pc->m->list;
  214. l->flags = Lwrite|0x5;
  215. l->len = 0;
  216. l->ctab = PCIWADDR(t);
  217. l->ctabhi = 0;
  218. return ahciwait(pc, 3*1000);
  219. }
  220. static int
  221. setudmamode(Aportc *pc, uchar f)
  222. {
  223. uchar *c;
  224. Actab *t;
  225. Alist *l;
  226. t = pc->m->ctab;
  227. c = t->cfis;
  228. memset(c, 0, 0x20);
  229. c[0] = 0x27;
  230. c[1] = 0x80;
  231. c[2] = 0xef;
  232. c[3] = 3; /* set transfer mode */
  233. c[7] = 0xa0; /* obsolete device bits */
  234. c[12] = 0x40 | f; /* sector count */
  235. l = pc->m->list;
  236. l->flags = Lwrite | 0x5;
  237. l->len = 0;
  238. l->ctab = PCIWADDR(t);
  239. l->ctabhi = 0;
  240. return ahciwait(pc, 3*1000);
  241. }
  242. static void
  243. asleep(int ms)
  244. {
  245. delay(ms);
  246. }
  247. static int
  248. ahciportreset(Aportc *c)
  249. {
  250. ulong *cmd, i;
  251. Aport *p;
  252. p = c->p;
  253. cmd = &p->cmd;
  254. *cmd &= ~(Afre|Ast);
  255. for(i = 0; i < 500; i += 25){
  256. if((*cmd & Acr) == 0)
  257. break;
  258. asleep(25);
  259. }
  260. p->sctl = 1 | (p->sctl & ~7);
  261. delay(1);
  262. p->sctl &= ~7;
  263. return 0;
  264. }
  265. static ushort
  266. gbit16(void *a)
  267. {
  268. uchar *i;
  269. i = a;
  270. return i[1]<<8 | i[0];
  271. }
  272. static ulong
  273. gbit32(void *a)
  274. {
  275. ulong j;
  276. uchar *i;
  277. i = a;
  278. j = i[3] << 24;
  279. j |= i[2] << 16;
  280. j |= i[1] << 8;
  281. j |= i[0];
  282. return j;
  283. }
  284. static uvlong
  285. gbit64(void *a)
  286. {
  287. uchar *i;
  288. i = a;
  289. return (uvlong) gbit32(i+4)<<32 | gbit32(a);
  290. }
  291. static int
  292. ahciidentify0(Aportc *pc, void *id, int atapi)
  293. {
  294. uchar *c;
  295. Actab *t;
  296. Alist *l;
  297. Aprdt *p;
  298. static uchar tab[] = { 0xec, 0xa1 };
  299. t = pc->m->ctab;
  300. c = t->cfis;
  301. memset(c, 0, 0x20);
  302. c[0] = 0x27;
  303. c[1] = 0x80;
  304. c[2] = tab[atapi];
  305. c[7] = 0xa0; /* obsolete device bits */
  306. l = pc->m->list;
  307. l->flags = 1<<16 | 0x5;
  308. l->len = 0;
  309. l->ctab = PCIWADDR(t);
  310. l->ctabhi = 0;
  311. memset(id, 0, 0x100);
  312. p = &t->prdt;
  313. p->dba = PCIWADDR(id);
  314. p->dbahi = 0;
  315. p->count = 1<<31 | (0x200-2) | 1;
  316. return ahciwait(pc, 3*1000);
  317. }
  318. static vlong
  319. ahciidentify(Aportc *pc, ushort *id)
  320. {
  321. int i, sig;
  322. vlong s;
  323. Aportm *m;
  324. m = pc->m;
  325. m->feat = 0;
  326. m->smart = 0;
  327. i = 0;
  328. sig = pc->p->sig >> 16;
  329. if(sig == 0xeb14){
  330. m->feat |= Datapi;
  331. i = 1;
  332. }
  333. if(ahciidentify0(pc, id, i) == -1)
  334. return -1;
  335. i = gbit16(id+83) | gbit16(id+86);
  336. if(i & (1<<10)){
  337. m->feat |= Dllba;
  338. s = gbit64(id+100);
  339. }else
  340. s = gbit32(id+60);
  341. if(m->feat & Datapi){
  342. i = gbit16(id+0);
  343. if(i & 1)
  344. m->feat |= Datapi16;
  345. }
  346. i = gbit16(id+83);
  347. if((i>>14) != 1)
  348. return s;
  349. if(i & (1<<3))
  350. m->feat |= Dpower;
  351. i = gbit16(id+82);
  352. if(i & 1)
  353. m->feat |= Dsmart;
  354. if(i & (1<<14))
  355. m->feat |= Dnop;
  356. return s;
  357. }
  358. static int
  359. ahciquiet(Aport *a)
  360. {
  361. ulong *p, i;
  362. p = &a->cmd;
  363. *p &= ~Ast;
  364. for(i = 0; i < 500; i += 50){
  365. if((*p & Acr) == 0)
  366. goto stop;
  367. asleep(50);
  368. }
  369. return -1;
  370. stop:
  371. if((a->task & (ASdrq|ASbsy)) == 0){
  372. *p |= Ast;
  373. return 0;
  374. }
  375. *p |= Aclo;
  376. for(i = 0; i < 500; i += 50){
  377. if((*p & Aclo) == 0)
  378. goto stop1;
  379. asleep(50);
  380. }
  381. return -1;
  382. stop1:
  383. /* extra check */
  384. dprint("clo clear %lx\n", a->task);
  385. if(a->task & ASbsy)
  386. return -1;
  387. *p |= Ast;
  388. return 0;
  389. }
  390. static int
  391. ahciidle(Aport *port)
  392. {
  393. ulong *p, i, r;
  394. p = &port->cmd;
  395. if((*p & Arun) == 0)
  396. return 0;
  397. *p &= ~Ast;
  398. r = 0;
  399. for(i = 0; i < 500; i += 25){
  400. if((*p & Acr) == 0)
  401. goto stop;
  402. asleep(25);
  403. }
  404. r = -1;
  405. stop:
  406. if((*p & Afre) == 0)
  407. return r;
  408. *p &= ~Afre;
  409. for(i = 0; i < 500; i += 25){
  410. if((*p & Afre) == 0)
  411. return 0;
  412. asleep(25);
  413. }
  414. return -1;
  415. }
  416. /*
  417. * §6.2.2.1 first part; comreset handled by reset disk.
  418. * - remainder is handled by configdisk.
  419. * - ahcirecover is a quick recovery from a failed command.
  420. */
  421. int
  422. ahciswreset(Aportc *pc)
  423. {
  424. int i;
  425. i = ahciidle(pc->p);
  426. pc->p->cmd |= Afre;
  427. if(i == -1)
  428. return -1;
  429. if(pc->p->task & (ASdrq|ASbsy))
  430. return -1;
  431. return 0;
  432. }
  433. int
  434. ahcirecover(Aportc *pc)
  435. {
  436. ahciswreset(pc);
  437. pc->p->cmd |= Ast;
  438. if(setudmamode(pc, 5) == -1)
  439. return -1;
  440. return 0;
  441. }
  442. static void*
  443. malign(int size, int align)
  444. {
  445. void *v;
  446. v = xspanalloc(size, align, 0);
  447. memset(v, 0, size);
  448. return v;
  449. }
  450. static void
  451. setupfis(Afis *f)
  452. {
  453. f->base = malign(0x100, 0x100);
  454. f->d = f->base + 0;
  455. f->p = f->base + 0x20;
  456. f->r = f->base + 0x40;
  457. f->u = f->base + 0x60;
  458. f->devicebits = (ulong*)(f->base + 0x58);
  459. }
  460. static void
  461. ahciwakeup(Aport *p)
  462. {
  463. ushort s;
  464. s = p->sstatus;
  465. if((s & 0x700) != 0x600)
  466. return;
  467. if((s & 7) != 1){
  468. print("ahci: slumbering drive unwakeable %ux\n", s);
  469. return;
  470. }
  471. p->sctl = 3*Aipm | 0*Aspd | Adet;
  472. delay(1);
  473. p->sctl &= ~7;
  474. // iprint("ahci: wake %ux -> %ux\n", s, p->sstatus);
  475. }
  476. static int
  477. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  478. {
  479. Aportm *m;
  480. Aport *p;
  481. p = c->p;
  482. m = c->m;
  483. if(m->list == 0){
  484. setupfis(&m->fis);
  485. m->list = malign(sizeof *m->list, 1024);
  486. m->ctab = malign(sizeof *m->ctab, 128);
  487. }
  488. if(p->sstatus & 3 && h->cap & Hsss){
  489. dprint("configdrive: spinning up ... [%lux]\n", p->sstatus);
  490. p->cmd |= Apod|Asud;
  491. asleep(1400);
  492. }
  493. p->serror = SerrAll;
  494. p->list = PCIWADDR(m->list);
  495. p->listhi = 0;
  496. p->fis = PCIWADDR(m->fis.base);
  497. p->fishi = 0;
  498. p->cmd |= Afre | Ast;
  499. if((p->sstatus & 0x707) == 0x601) /* drive coming up in slumbering? */
  500. ahciwakeup(p);
  501. /* disable power managment sequence from book. */
  502. p->sctl = (3*Aipm) | (mode*Aspd) | (0*Adet);
  503. p->cmd &= ~Aalpe;
  504. p->ie = IEM;
  505. return 0;
  506. }
  507. static int
  508. ahcienable(Ahba *h)
  509. {
  510. h->ghc |= Hie;
  511. return 0;
  512. }
  513. static int
  514. ahcidisable(Ahba *h)
  515. {
  516. h->ghc &= ~Hie;
  517. return 0;
  518. }
  519. static int
  520. countbits(ulong u)
  521. {
  522. int i, n;
  523. n = 0;
  524. for(i = 0; i < 32; i++)
  525. if(u & (1<<i))
  526. n++;
  527. return n;
  528. }
  529. static int
  530. ahciconf(Ctlr *c)
  531. {
  532. ulong u;
  533. Ahba *h;
  534. static int count;
  535. h = c->hba = (Ahba*)c->mmio;
  536. u = h->cap;
  537. if((u & Hsam) == 0)
  538. h->ghc |= Hae;
  539. print("ahci%d port %#p: hba sss %ld; ncs %ld; coal %ld; mports %ld; "
  540. "led %ld; clo %ld; ems %ld;\n", count++, h,
  541. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  542. (u>>24) & 1, (u>>6) & 1);
  543. return countbits(h->pi);
  544. }
  545. static int
  546. ahcihbareset(Ahba *h)
  547. {
  548. int wait;
  549. h->ghc |= 1;
  550. for(wait = 0; wait < 1000; wait += 100){
  551. if(h->ghc == 0)
  552. return 0;
  553. delay(100);
  554. }
  555. return -1;
  556. }
  557. static void
  558. idmove(char *p, ushort *a, int n)
  559. {
  560. int i;
  561. char *op, *e;
  562. op = p;
  563. for(i = 0; i < n/2; i++){
  564. *p++ = a[i] >> 8;
  565. *p++ = a[i];
  566. }
  567. *p = 0;
  568. while(p > op && *--p == ' ')
  569. *p = 0;
  570. e = p;
  571. for (p = op; *p == ' '; p++)
  572. ;
  573. memmove(op, p, n - (e - p));
  574. }
  575. static int
  576. identify(Drive *d)
  577. {
  578. ushort *id;
  579. vlong osectors, s;
  580. uchar oserial[21];
  581. SDunit *u;
  582. id = d->info;
  583. s = ahciidentify(&d->portc, id);
  584. if(s == -1){
  585. d->state = Derror;
  586. return -1;
  587. }
  588. osectors = d->sectors;
  589. memmove(oserial, d->serial, sizeof d->serial);
  590. d->sectors = s;
  591. d->smartrs = 0;
  592. idmove(d->serial, id+10, 20);
  593. idmove(d->firmware, id+23, 8);
  594. idmove(d->model, id+27, 40);
  595. u = d->unit;
  596. memset(u->inquiry, 0, sizeof u->inquiry);
  597. u->inquiry[2] = 2;
  598. u->inquiry[3] = 2;
  599. u->inquiry[4] = sizeof u->inquiry - 4;
  600. memmove(u->inquiry+8, d->model, 40);
  601. if(osectors != s || memcmp(oserial, d->serial, sizeof oserial)){
  602. d->mediachange = 1;
  603. u->sectors = 0;
  604. }
  605. return 0;
  606. }
  607. static void
  608. clearci(Aport *p)
  609. {
  610. if((p->cmd & Ast) == 0)
  611. return;
  612. p->cmd &= ~Ast;
  613. p->cmd |= Ast;
  614. }
  615. static void
  616. updatedrive(Drive *d)
  617. {
  618. ulong cause, serr, s0, pr, ewake;
  619. char *name;
  620. Aport *p;
  621. static ulong last;
  622. pr = 1;
  623. ewake = 0;
  624. p = d->port;
  625. cause = p->isr;
  626. serr = p->serror;
  627. p->isr = cause;
  628. name = "??";
  629. if(d->unit && d->unit->name)
  630. name = d->unit->name;
  631. if(p->ci == 0){
  632. d->portm.flag |= Fdone;
  633. pr = 0;
  634. }else if(cause & Adps)
  635. pr = 0;
  636. if(cause&Ifatal){
  637. ewake = 1;
  638. dprint("Fatal\n");
  639. }
  640. if(cause & Adhrs){
  641. if(p->task & (1<<5|1)){
  642. dprint("Adhrs cause %lux serr %lux task %lux\n",
  643. cause, serr, p->task);
  644. d->portm.flag |= Ferror;
  645. ewake = 1;
  646. }
  647. pr = 0;
  648. }
  649. if(pr)
  650. dprint("%s: upd %lux ta %lux\n", name, cause, p->task);
  651. if(cause & (Aprcs|Aifs)){
  652. s0 = d->state;
  653. switch(p->sstatus & 7){
  654. case 0:
  655. d->state = Dmissing;
  656. break;
  657. case 1:
  658. if((p->sstatus & 0x700) == 0x600)
  659. d->state = Dnew;
  660. else
  661. d->state = Derror;
  662. break;
  663. case 3:
  664. /* power mgnt crap for surprise removal */
  665. p->ie |= Aprcs | Apcs; /* is this required? */
  666. d->state = Dreset;
  667. break;
  668. case 4:
  669. d->state = Doffline;
  670. break;
  671. }
  672. dprint("%s: %s → %s [Apcrs] %lux\n", name, diskstates[s0],
  673. diskstates[d->state], p->sstatus);
  674. if(s0 == Dready && d->state != Dready)
  675. idprint("%s: pulled\n", name);
  676. if(d->state != Dready)
  677. d->portm.flag |= Ferror;
  678. ewake = 1;
  679. }
  680. p->serror = serr;
  681. if(ewake)
  682. clearci(p);
  683. last = cause;
  684. }
  685. static void
  686. pstatus(Drive *d, ulong s)
  687. {
  688. /*
  689. * bogus code because the first interrupt is currently dropped.
  690. * likely my fault. serror may be cleared at the wrong time.
  691. */
  692. switch(s){
  693. case 0:
  694. d->state = Dmissing;
  695. break;
  696. case 2:
  697. case 3:
  698. d->wait = 0;
  699. d->state = Dnew;
  700. break;
  701. case 4:
  702. d->state = Doffline;
  703. break;
  704. case 6:
  705. d->state = Dnew;
  706. break;
  707. }
  708. }
  709. static int
  710. configdrive(Drive *d)
  711. {
  712. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  713. return -1;
  714. ilock(d);
  715. pstatus(d, d->port->sstatus & 7);
  716. iunlock(d);
  717. return 0;
  718. }
  719. static void
  720. resetdisk(Drive *d)
  721. {
  722. uint state, det, stat;
  723. Aport *p;
  724. p = d->port;
  725. det = p->sctl & 7;
  726. stat = p->sstatus & 7;
  727. state = (p->cmd>>28) & 0xf;
  728. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  729. if(stat != 3){
  730. ilock(d);
  731. d->state = Dportreset;
  732. iunlock(d);
  733. return;
  734. }
  735. ilock(d);
  736. state = d->state;
  737. if(d->state != Dready || d->state != Dnew)
  738. d->portm.flag |= Ferror;
  739. clearci(p); /* satisfy sleep condition. */
  740. iunlock(d);
  741. qlock(&d->portm);
  742. if(p->cmd & Ast && ahciswreset(&d->portc) == -1){
  743. ilock(d);
  744. d->state = Dportreset; /* get a bigger stick. */
  745. iunlock(d);
  746. } else {
  747. ilock(d);
  748. d->state = Dmissing;
  749. iunlock(d);
  750. configdrive(d);
  751. }
  752. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  753. qunlock(&d->portm);
  754. }
  755. static int
  756. newdrive(Drive *d)
  757. {
  758. char *name, *s;
  759. Aportc *c;
  760. Aportm *m;
  761. c = &d->portc;
  762. m = &d->portm;
  763. name = d->unit->name;
  764. if(name == 0)
  765. name = "??";
  766. if(d->port->task == 0x80)
  767. return -1;
  768. qlock(c->m);
  769. if(setudmamode(c, 5) == -1){
  770. dprint("%s: can't set udma mode\n", name);
  771. goto lose;
  772. }
  773. if(identify(d) == -1){
  774. dprint("%s: identify failure\n", name);
  775. goto lose;
  776. }
  777. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  778. m->feat &= ~Dpower;
  779. if(ahcirecover(c) == -1)
  780. goto lose;
  781. }
  782. if (d->sectors == 0) {
  783. idprint("%s: no sectors\n", d->unit->name);
  784. goto lose;
  785. }
  786. ilock(d);
  787. d->state = Dready;
  788. iunlock(d);
  789. qunlock(c->m);
  790. s = "";
  791. if(m->feat & Dllba)
  792. s = "L";
  793. idprint("%s: %sLBA %,llud sectors\n", d->unit->name, s, d->sectors);
  794. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  795. d->mediachange? "[mediachange]": "");
  796. return 0;
  797. lose:
  798. qunlock(&d->portm);
  799. return -1;
  800. }
  801. enum {
  802. Nms = 256,
  803. Mphywait = 2*1024/Nms - 1,
  804. Midwait = 16*1024/Nms - 1,
  805. Mcomrwait = 64*1024/Nms - 1,
  806. };
  807. static void
  808. westerndigitalhung(Drive *d)
  809. {
  810. if((d->portm.feat & Datapi) == 0 && d->active &&
  811. TK2MS(m->ticks - d->intick) > 5000){
  812. dprint("%s: drive hung; resetting [%lux] ci=%lx\n",
  813. d->unit->name, d->port->task, d->port->ci);
  814. d->state = Dreset;
  815. }
  816. }
  817. static ushort olds[NCtlr*NCtlrdrv];
  818. static int
  819. doportreset(Drive *d)
  820. {
  821. int i;
  822. i = -1;
  823. qlock(&d->portm);
  824. if(ahciportreset(&d->portc) == -1)
  825. dprint("ahciportreset fails\n");
  826. else
  827. i = 0;
  828. qunlock(&d->portm);
  829. dprint("portreset → %s [task %lux]\n", diskstates[d->state],
  830. d->port->task);
  831. return i;
  832. }
  833. static void
  834. checkdrive(Drive *d, int i)
  835. {
  836. ushort s;
  837. char *name;
  838. ilock(d);
  839. name = d->unit->name;
  840. s = d->port->sstatus;
  841. if(s != olds[i]){
  842. dprint("%s: status: %#ux -> %#ux: %s\n", name, olds[i],
  843. s, diskstates[d->state]);
  844. olds[i] = s;
  845. d->wait = 0;
  846. }
  847. westerndigitalhung(d);
  848. switch(d->state){
  849. case Dnull:
  850. break;
  851. case Dmissing:
  852. case Dnew:
  853. switch(s & 0x107){
  854. case 1:
  855. ahciwakeup(d->port);
  856. case 0:
  857. break;
  858. default:
  859. dprint("%s: unknown status %04ux\n", name, s);
  860. case 0x100:
  861. if(++d->wait&Mphywait)
  862. break;
  863. reset:
  864. if(++d->mode > DMsataii)
  865. d->mode = 0;
  866. if(d->mode == DMsatai){
  867. d->state = Dportreset;
  868. goto portreset;
  869. }
  870. dprint("%s: reset; new mode %s\n", name,
  871. modename[d->mode]);
  872. iunlock(d);
  873. resetdisk(d);
  874. ilock(d);
  875. break;
  876. case 0x103:
  877. if((++d->wait&Midwait) == 0){
  878. dprint("%s: slow reset %#ux task=%#lux; %d\n",
  879. name, s, d->port->task, d->wait);
  880. goto reset;
  881. }
  882. s = d->port->task&0xff;
  883. if(s == 0x7f || ((d->port->sig>>16) != 0xeb14 &&
  884. (s & ~0x17) != (1<<6)))
  885. break;
  886. iunlock(d);
  887. newdrive(d);
  888. ilock(d);
  889. break;
  890. }
  891. break;
  892. case Doffline:
  893. if(d->wait++ & Mcomrwait)
  894. break;
  895. case Derror:
  896. case Dreset:
  897. dprint("%s: reset [%s]: mode %d; status %#ux\n",
  898. name, diskstates[d->state], d->mode, s);
  899. iunlock(d);
  900. resetdisk(d);
  901. ilock(d);
  902. break;
  903. case Dportreset:
  904. portreset:
  905. if(d->wait++ & 0xff && (s & 0x100) == 0)
  906. break;
  907. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  908. name, diskstates[d->state], d->mode, s);
  909. d->portm.flag |= Ferror;
  910. clearci(d->port);
  911. if((s & 7) == 0){
  912. d->state = Dmissing;
  913. break;
  914. }
  915. iunlock(d);
  916. doportreset(d);
  917. ilock(d);
  918. break;
  919. }
  920. iunlock(d);
  921. }
  922. static void
  923. iainterrupt(Ureg*, void *a)
  924. {
  925. int i;
  926. ulong cause, m;
  927. Ctlr *c;
  928. Drive *d;
  929. c = a;
  930. ilock(c);
  931. cause = c->hba->isr;
  932. for(i = 0; i < c->mport; i++){
  933. m = 1 << i;
  934. if((cause & m) == 0)
  935. continue;
  936. d = c->rawdrive + i;
  937. ilock(d);
  938. if(d->port->isr && c->hba->pi & m)
  939. updatedrive(d);
  940. c->hba->isr = m;
  941. iunlock(d);
  942. }
  943. iunlock(c);
  944. }
  945. static int
  946. iaverify(SDunit *u)
  947. {
  948. int i;
  949. Ctlr *c;
  950. Drive *d;
  951. c = u->dev->ctlr;
  952. d = c->drive[u->subno];
  953. ilock(c);
  954. ilock(d);
  955. d->unit = u;
  956. iunlock(d);
  957. iunlock(c);
  958. for(i = 0; i < 10; i++){
  959. checkdrive(d, d->driveno);
  960. switch(d->state){
  961. case Dmissing:
  962. if(d->port->sstatus & 0x733)
  963. break;
  964. /* fall through */
  965. case Dnull:
  966. case Dready:
  967. case Doffline:
  968. print("sdiahci: drive %d in state %s after %d resets\n",
  969. d->driveno, diskstates[d->state], i);
  970. return 1;
  971. }
  972. delay(100);
  973. }
  974. print("sdiahci: drive %d won't come up; in state %s after %d resets\n",
  975. d->driveno, diskstates[d->state], i);
  976. return 1;
  977. }
  978. static int
  979. iaenable(SDev *s)
  980. {
  981. Ctlr *c;
  982. c = s->ctlr;
  983. ilock(c);
  984. if(!c->enabled) {
  985. if(c->ndrive == 0)
  986. panic("iaenable: zero s->ctlr->ndrive");
  987. pcisetbme(c->pci);
  988. setvec(c->pci->intl+VectorPIC, iainterrupt, c);
  989. /* supposed to squelch leftover interrupts here. */
  990. ahcienable(c->hba);
  991. c->enabled = 1;
  992. }
  993. iunlock(c);
  994. return 1;
  995. }
  996. static int
  997. iadisable(SDev *s)
  998. {
  999. Ctlr *c;
  1000. c = s->ctlr;
  1001. ilock(c);
  1002. ahcidisable(c->hba);
  1003. // intrdisable(c->irq, iainterrupt, c, c->tbdf, name);
  1004. c->enabled = 0;
  1005. iunlock(c);
  1006. return 1;
  1007. }
  1008. static int
  1009. iaonline(SDunit *unit)
  1010. {
  1011. int r;
  1012. Ctlr *c;
  1013. Drive *d;
  1014. c = unit->dev->ctlr;
  1015. d = c->drive[unit->subno];
  1016. r = 0;
  1017. if(d->portm.feat & Datapi && d->mediachange){
  1018. r = scsionline(unit);
  1019. if(r > 0)
  1020. d->mediachange = 0;
  1021. return r;
  1022. }
  1023. ilock(d);
  1024. if(d->mediachange){
  1025. r = 2;
  1026. d->mediachange = 0;
  1027. /* devsd resets this after online is called; why? */
  1028. unit->sectors = d->sectors;
  1029. unit->secsize = 512;
  1030. } else if(d->state == Dready)
  1031. r = 1;
  1032. iunlock(d);
  1033. return r;
  1034. }
  1035. /* returns locked list! */
  1036. static Alist*
  1037. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1038. {
  1039. uchar *c, acmd, dir, llba;
  1040. Alist *l;
  1041. Actab *t;
  1042. Aprdt *p;
  1043. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35 };
  1044. dir = *cmd != 0x28;
  1045. llba = m->feat & Dllba? 1: 0;
  1046. acmd = tab[dir][llba];
  1047. qlock(m);
  1048. l = m->list;
  1049. t = m->ctab;
  1050. c = t->cfis;
  1051. c[0] = 0x27;
  1052. c[1] = 0x80;
  1053. c[2] = acmd;
  1054. c[3] = 0;
  1055. c[4] = lba; /* sector lba low 7:0 */
  1056. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1057. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1058. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1059. if(llba == 0)
  1060. c[7] |= (lba>>24) & 7;
  1061. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1062. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1063. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1064. c[11] = 0; /* features (exp); */
  1065. c[12] = n; /* sector count */
  1066. c[13] = n >> 8; /* sector count (exp) */
  1067. c[14] = 0; /* r */
  1068. c[15] = 0; /* control */
  1069. *(ulong*)(c+16) = 0;
  1070. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1071. if(dir == Write)
  1072. l->flags |= Lwrite;
  1073. l->len = 0;
  1074. l->ctab = PCIWADDR(t);
  1075. l->ctabhi = 0;
  1076. p = &t->prdt;
  1077. p->dba = PCIWADDR(data);
  1078. p->dbahi = 0;
  1079. p->count = 1<<31 | (512*n - 2) | 1;
  1080. return l;
  1081. }
  1082. static Alist*
  1083. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1084. {
  1085. int fill, len;
  1086. uchar *c;
  1087. Actab *t;
  1088. Alist *l;
  1089. Aprdt *p;
  1090. qlock(m);
  1091. l = m->list;
  1092. t = m->ctab;
  1093. c = t->cfis;
  1094. fill = m->feat & Datapi16? 16: 12;
  1095. if((len = r->clen) > fill)
  1096. len = fill;
  1097. memmove(t->atapi, r->cmd, len);
  1098. memset(t->atapi + len, 0, fill - len);
  1099. c[0] = 0x27;
  1100. c[1] = 0x80;
  1101. c[2] = 0xa0;
  1102. if(n != 0)
  1103. c[3] = 1; /* dma */
  1104. else
  1105. c[3] = 0; /* features (exp); */
  1106. c[4] = 0; /* sector lba low 7:0 */
  1107. c[5] = n; /* cylinder low lba mid 15:8 */
  1108. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1109. c[7] = 0xa0; /* obsolete device bits */
  1110. *(ulong*)(c+8) = 0;
  1111. *(ulong*)(c+12) = 0;
  1112. *(ulong*)(c+16) = 0;
  1113. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1114. if(r->write != 0 && data)
  1115. l->flags |= Lwrite;
  1116. l->len = 0;
  1117. l->ctab = PCIWADDR(t);
  1118. l->ctabhi = 0;
  1119. if(data == 0)
  1120. return l;
  1121. p = &t->prdt;
  1122. p->dba = PCIWADDR(data);
  1123. p->dbahi = 0;
  1124. p->count = 1<<31 | (n - 2) | 1;
  1125. return l;
  1126. }
  1127. static int
  1128. waitready(Drive *d)
  1129. {
  1130. ulong s, t, i;
  1131. for(i = 0; i < 120; i++){
  1132. ilock(d);
  1133. s = d->port->sstatus;
  1134. t = d->port->task;
  1135. iunlock(d);
  1136. if((s & 0x100) == 0)
  1137. return -1;
  1138. if(d->state == Dready && (s & 7) == 3)
  1139. return 0;
  1140. if((i + 1) % 30 == 0)
  1141. print("%s: waitready: [%s] task=%lux sstat=%lux\n",
  1142. d->unit->name, diskstates[d->state], t, s);
  1143. esleep(1000);
  1144. }
  1145. print("%s: not responding; offline\n", d->unit->name);
  1146. ilock(d);
  1147. d->state = Doffline;
  1148. iunlock(d);
  1149. return -1;
  1150. }
  1151. static int
  1152. iariopkt(SDreq *r, Drive *d)
  1153. {
  1154. int n, count, try, max, flag, task;
  1155. char *name;
  1156. uchar *cmd, *data;
  1157. Aport *p;
  1158. Asleep as;
  1159. cmd = r->cmd;
  1160. name = d->unit->name;
  1161. p = d->port;
  1162. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1163. r->dlen, r->data);
  1164. // if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1165. // return sdmodesense(r, cmd, d->info, sizeof d->info);
  1166. r->rlen = 0;
  1167. count = r->dlen;
  1168. max = 65536;
  1169. try = 0;
  1170. retry:
  1171. if(waitready(d) == -1)
  1172. return SDeio;
  1173. data = r->data;
  1174. n = count;
  1175. if(n > max)
  1176. n = max;
  1177. d->active++;
  1178. ahcibuildpkt(&d->portm, r, data, n);
  1179. ilock(d);
  1180. d->portm.flag = 0;
  1181. iunlock(d);
  1182. p->ci = 1;
  1183. as.p = p;
  1184. as.i = 1;
  1185. d->intick = m->ticks;
  1186. while(ahciclear(&as) == 0)
  1187. ;
  1188. if (d->port == nil)
  1189. panic("iariopkt: nil d->port");
  1190. ilock(d);
  1191. flag = d->portm.flag;
  1192. task = d->port->task;
  1193. iunlock(d);
  1194. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1195. d->port->ci = 0;
  1196. ahcirecover(&d->portc);
  1197. task = d->port->task;
  1198. }
  1199. d->active--;
  1200. qunlock(&d->portm);
  1201. if(flag == 0){
  1202. if(++try == 10){
  1203. print("%s: bad disk\n", name);
  1204. r->status = SDcheck;
  1205. return SDcheck;
  1206. }
  1207. print("%s: retry\n", name);
  1208. esleep(1000);
  1209. goto retry;
  1210. }
  1211. if(flag & Ferror){
  1212. if((task & Eidnf) == 0)
  1213. print("%s: i/o error %ux\n", name, task);
  1214. r->status = SDcheck;
  1215. return SDcheck;
  1216. }
  1217. data += n;
  1218. r->rlen = data - (uchar*)r->data;
  1219. r->status = SDok;
  1220. return SDok;
  1221. }
  1222. static int
  1223. iario(SDreq *r)
  1224. {
  1225. int n, count, max, flag, task;
  1226. vlong lba;
  1227. char *name;
  1228. uchar *cmd, *data;
  1229. Aport *p;
  1230. Asleep as;
  1231. Ctlr *c;
  1232. Drive *d;
  1233. SDunit *unit;
  1234. unit = r->unit;
  1235. c = unit->dev->ctlr;
  1236. d = c->drive[unit->subno];
  1237. if(d->portm.feat & Datapi)
  1238. return iariopkt(r, d);
  1239. cmd = r->cmd;
  1240. name = d->unit->name;
  1241. p = d->port;
  1242. // if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1243. // r->status = i;
  1244. // return i;
  1245. // }
  1246. if(*cmd != 0x28 && *cmd != 0x2a){
  1247. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1248. r->status = SDcheck;
  1249. return SDcheck;
  1250. }
  1251. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1252. count = cmd[7]<<8 | cmd[8];
  1253. if(r->data == nil)
  1254. return SDok;
  1255. if (unit->secsize <= 0)
  1256. unit->secsize = 512;
  1257. if(r->dlen < count * unit->secsize)
  1258. count = r->dlen / unit->secsize;
  1259. max = 128;
  1260. if(waitready(d) == -1)
  1261. return SDeio;
  1262. data = r->data;
  1263. while(count > 0){
  1264. n = count;
  1265. if(n > max)
  1266. n = max;
  1267. d->active++;
  1268. ahcibuild(&d->portm, cmd, data, n, lba);
  1269. ilock(d);
  1270. d->portm.flag = 0;
  1271. iunlock(d);
  1272. p->ci = 1;
  1273. as.p = p;
  1274. as.i = 1;
  1275. d->intick = m->ticks;
  1276. while(ahciclear(&as) == 0)
  1277. ;
  1278. if (d->port == nil)
  1279. panic("iario: nil d->port");
  1280. ilock(d);
  1281. flag = d->portm.flag;
  1282. task = d->port->task;
  1283. iunlock(d);
  1284. if(task & (Efatal<<8) ||
  1285. task & (ASbsy|ASdrq) && d->state == Dready){
  1286. d->port->ci = 0;
  1287. ahcirecover(&d->portc);
  1288. task = d->port->task;
  1289. }
  1290. d->active--;
  1291. qunlock(&d->portm);
  1292. if(flag == 0 || flag & Ferror){
  1293. print("%s: i/o error %ux @%lld\n", name, task, lba);
  1294. r->status = SDeio;
  1295. return SDeio;
  1296. }
  1297. count -= n;
  1298. lba += n;
  1299. data += n * unit->secsize;
  1300. }
  1301. r->rlen = data - (uchar*)r->data;
  1302. r->status = SDok;
  1303. return SDok;
  1304. }
  1305. /*
  1306. * configure drives 0-5 as ahci sata (c.f. errata)
  1307. */
  1308. static int
  1309. iaahcimode(Pcidev *p)
  1310. {
  1311. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91),
  1312. pcicfgr8(p, 92), pcicfgr8(p, 93));
  1313. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1314. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1315. return 0;
  1316. }
  1317. static void
  1318. iasetupahci(Ctlr *c)
  1319. {
  1320. /* disable cmd block decoding. */
  1321. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1322. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1323. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1324. c->lmmio[0xc/4] = (1<<6) - 1; /* five ports (supposedly ro pi reg) */
  1325. /* enable ahci mode; from ich9 datasheet */
  1326. pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
  1327. }
  1328. static int
  1329. didtype(Pcidev *p)
  1330. {
  1331. switch(p->vid){
  1332. case 0x8086:
  1333. if((p->did & 0xfffc) == 0x2680)
  1334. return Tesb;
  1335. /*
  1336. * 0x27c4 is the intel 82801 in compatibility (not sata) mode.
  1337. * ich7 is 82801g[bh]m?.
  1338. */
  1339. if ((p->did & 0xfeff) == 0x2829 || /* ich8 */
  1340. (p->did & 0xfffe) == 0x2922 || /* ich9 */
  1341. (p->did & 0xfffe) == 0x27c4 /* || p->did == 0x27c0 */ ) /* ich7 */
  1342. return Tich;
  1343. break;
  1344. case 0x1002:
  1345. if(p->did == 0x4380)
  1346. return Tsb600;
  1347. break;
  1348. }
  1349. if(p->ccrb == Pcibcstore && p->ccru == 6 && p->ccrp == 1)
  1350. return Tunk;
  1351. return -1;
  1352. }
  1353. static SDev*
  1354. iapnp(void)
  1355. {
  1356. int i, n, nunit, type;
  1357. ulong io;
  1358. Ctlr *c;
  1359. Drive *d;
  1360. Pcidev *p;
  1361. SDev *head, *tail, *s;
  1362. static int done;
  1363. if (done || getconf("*noahciload") != nil)
  1364. return nil;
  1365. done = 1;
  1366. memset(olds, 0xff, sizeof olds);
  1367. p = nil;
  1368. head = tail = nil;
  1369. loop:
  1370. while((p = pcimatch(p, 0, 0)) != nil){
  1371. if((type = didtype(p)) == -1)
  1372. continue;
  1373. if(niactlr == NCtlr){
  1374. print("iapnp: %s: too many controllers\n", tname[type]);
  1375. break;
  1376. }
  1377. c = iactlr + niactlr;
  1378. s = sdevs + niactlr;
  1379. memset(c, 0, sizeof *c);
  1380. memset(s, 0, sizeof *s);
  1381. c->pci = p;
  1382. c->type = type;
  1383. io = p->mem[Abar].bar & ~0xf;
  1384. io = upamalloc(io, p->mem[Abar].size, 0);
  1385. if(io == 0){
  1386. print("%s: address %#lux in use, did %#ux\n",
  1387. tname[c->type], io, p->did);
  1388. continue;
  1389. }
  1390. /* ugly hack: get this in compatibility mode; see memory.c:271 */
  1391. if(p->mem[Abar].bar == 0) {
  1392. print("%s: did %#ux has zero bar\n", tname[c->type],
  1393. p->did);
  1394. continue;
  1395. }
  1396. if(io == 0x40000000) {
  1397. print("%s: did %#ux is in non-sata mode. bar %#lux\n",
  1398. tname[c->type], p->did, p->mem[Abar].bar);
  1399. continue;
  1400. }
  1401. c->mmio = KADDR(io);
  1402. c->lmmio = (ulong*)c->mmio;
  1403. if(Intel(c) && p->did != 0x2681)
  1404. iasetupahci(c);
  1405. nunit = ahciconf(c);
  1406. // ahcihbareset((Ahba*)c->mmio);
  1407. if(Intel(c) && iaahcimode(p) == -1)
  1408. break;
  1409. if(nunit < 1){
  1410. // vunmap(c->mmio, p->mem[Abar].size);
  1411. continue;
  1412. }
  1413. niactlr++;
  1414. i = (c->hba->cap>>21) & 1;
  1415. print("%s: sata-%s with %d ports\n", tname[c->type],
  1416. "I\0II"+i*2, nunit);
  1417. s->ifc = &sdiahciifc;
  1418. s->ctlr = c;
  1419. s->nunit = nunit;
  1420. s->idno = 'E';
  1421. c->sdev = s;
  1422. c->ndrive = nunit;
  1423. c->mport = c->hba->cap & 0x1f;
  1424. /* map the drives -- they don't all need to be enabled. */
  1425. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1426. n = 0;
  1427. for(i = 0; i < NCtlrdrv; i++) {
  1428. d = c->rawdrive+i;
  1429. d->portno = i;
  1430. d->driveno = -1;
  1431. d->sectors = 0;
  1432. d->ctlr = c;
  1433. if((c->hba->pi & (1<<i)) == 0)
  1434. continue;
  1435. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1436. d->portc.p = d->port;
  1437. d->portc.m = &d->portm;
  1438. d->driveno = n++;
  1439. c->drive[d->driveno] = d;
  1440. }
  1441. for(i = 0; i < n; i++)
  1442. if(ahciidle(c->drive[i]->port) == -1){
  1443. print("%s: port %d wedged; abort\n",
  1444. tname[c->type], i);
  1445. goto loop;
  1446. }
  1447. for(i = 0; i < n; i++){
  1448. c->drive[i]->mode = DMsatai;
  1449. configdrive(c->drive[i]);
  1450. }
  1451. if(head)
  1452. tail->next = s;
  1453. else
  1454. head = s;
  1455. tail = s;
  1456. }
  1457. return head;
  1458. }
  1459. static SDev*
  1460. iaid(SDev* sdev)
  1461. {
  1462. int i;
  1463. Ctlr *c;
  1464. for(; sdev; sdev = sdev->next){
  1465. if(sdev->ifc != &sdiahciifc)
  1466. continue;
  1467. c = sdev->ctlr;
  1468. for(i = 0; i < NCtlr; i++)
  1469. if(c == iactlr + i)
  1470. sdev->idno = 'E' + i;
  1471. }
  1472. return nil;
  1473. }
  1474. SDifc sdiahciifc = {
  1475. "iahci",
  1476. iapnp,
  1477. nil, /* legacy */
  1478. iaid,
  1479. iaenable,
  1480. iadisable,
  1481. iaverify,
  1482. iaonline,
  1483. iario,
  1484. nil,
  1485. nil,
  1486. scsibio,
  1487. };