etherigbe.c 40 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737
  1. /*
  2. * bootstrap driver for
  3. * Intel RS-82543GC Gigabit Ethernet Controller
  4. * as found on the Intel PRO/1000[FT] Server Adapter.
  5. * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt
  6. * is made to handle the older chip although it should be possible.
  7. *
  8. * updated just enough to cope with the
  9. * Intel 8254[0347]NN Gigabit Ethernet Controller
  10. * as found on the Intel PRO/1000 series of adapters:
  11. * 82540EM Intel PRO/1000 MT
  12. * 82543GC Intel PRO/1000 T
  13. * 82544EI Intel PRO/1000 XT
  14. * 82547EI built-in
  15. *
  16. * The datasheet is not very clear about running on a big-endian system
  17. * and this driver assumes little-endian throughout.
  18. * To do:
  19. * GMII/MII
  20. * check recovery from receive no buffers condition
  21. * automatic ett adjustment
  22. */
  23. #include "u.h"
  24. #include "lib.h"
  25. #include "mem.h"
  26. #include "dat.h"
  27. #include "fns.h"
  28. #include "io.h"
  29. #include "etherif.h"
  30. #include "ethermii.h"
  31. enum {
  32. Debug = 0, /* mostly for X60 debugging */
  33. };
  34. enum {
  35. i82542 = (0x1000<<16)|0x8086,
  36. i82543gc = (0x1004<<16)|0x8086,
  37. i82544ei = (0x1008<<16)|0x8086,
  38. i82540em = (0x100E<<16)|0x8086,
  39. i82546eb = (0x1010<<16)|0x8086,
  40. i82547ei = (0x1019<<16)|0x8086,
  41. i82540eplp = (0x101E<<16)|0x8086,
  42. i82547gi = (0x1075<<16)|0x8086,
  43. i82541gi = (0x1076<<16)|0x8086,
  44. i82541gi2 = (0x1077<<16)|0x8086,
  45. i82546gb = (0x1079<<16)|0x8086,
  46. i82541pi = (0x107c<<16)|0x8086,
  47. };
  48. /* compatibility with cpu kernels */
  49. #define iallocb allocb
  50. #ifndef CACHELINESZ
  51. #define CACHELINESZ 32 /* pentium & later */
  52. #endif
  53. /* from pci.c */
  54. enum
  55. { /* command register (pcidev->pcr) */
  56. IOen = (1<<0),
  57. MEMen = (1<<1),
  58. MASen = (1<<2),
  59. MemWrInv = (1<<4),
  60. PErrEn = (1<<6),
  61. SErrEn = (1<<8),
  62. };
  63. enum {
  64. Ctrl = 0x00000000, /* Device Control */
  65. Status = 0x00000008, /* Device Status */
  66. Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
  67. Ctrlext = 0x00000018, /* Extended Device Control */
  68. Mdic = 0x00000020, /* MDI Control */
  69. Fcal = 0x00000028, /* Flow Control Address Low */
  70. Fcah = 0x0000002C, /* Flow Control Address High */
  71. Fct = 0x00000030, /* Flow Control Type */
  72. Icr = 0x000000C0, /* Interrupt Cause Read */
  73. Ics = 0x000000C8, /* Interrupt Cause Set */
  74. Ims = 0x000000D0, /* Interrupt Mask Set/Read */
  75. Imc = 0x000000D8, /* Interrupt mask Clear */
  76. Rctl = 0x00000100, /* Receive Control */
  77. Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
  78. Txcw = 0x00000178, /* Transmit Configuration Word */
  79. Tctl = 0x00000400, /* Transmit Control */
  80. Tipg = 0x00000410, /* Transmit IPG */
  81. Tbt = 0x00000448, /* Transmit Burst Timer */
  82. Ait = 0x00000458, /* Adaptive IFS Throttle */
  83. Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
  84. Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
  85. Rdbal = 0x00002800, /* Rdesc Base Address Low */
  86. Rdbah = 0x00002804, /* Rdesc Base Address High */
  87. Rdlen = 0x00002808, /* Receive Descriptor Length */
  88. Rdh = 0x00002810, /* Receive Descriptor Head */
  89. Rdt = 0x00002818, /* Receive Descriptor Tail */
  90. Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
  91. Rxdctl = 0x00002828, /* Receive Descriptor Control */
  92. Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
  93. Txdmac = 0x00003000, /* Transfer DMA Control */
  94. Ett = 0x00003008, /* Early Transmit Control */
  95. Tdbal = 0x00003800, /* Tdesc Base Address Low */
  96. Tdbah = 0x00003804, /* Tdesc Base Address High */
  97. Tdlen = 0x00003808, /* Transmit Descriptor Length */
  98. Tdh = 0x00003810, /* Transmit Descriptor Head */
  99. Tdt = 0x00003818, /* Transmit Descriptor Tail */
  100. Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
  101. Txdctl = 0x00003828, /* Transmit Descriptor Control */
  102. Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
  103. Statistics = 0x00004000, /* Start of Statistics Area */
  104. Gorcl = 0x88/4, /* Good Octets Received Count */
  105. Gotcl = 0x90/4, /* Good Octets Transmitted Count */
  106. Torl = 0xC0/4, /* Total Octets Received */
  107. Totl = 0xC8/4, /* Total Octets Transmitted */
  108. Nstatistics = 64,
  109. Rxcsum = 0x00005000, /* Receive Checksum Control */
  110. Mta = 0x00005200, /* Multicast Table Array */
  111. Ral = 0x00005400, /* Receive Address Low */
  112. Rah = 0x00005404, /* Receive Address High */
  113. Manc = 0x00005820, /* Management Control */
  114. };
  115. enum { /* Ctrl */
  116. Bem = 0x00000002, /* Big Endian Mode */
  117. Prior = 0x00000004, /* Priority on the PCI bus */
  118. Lrst = 0x00000008, /* Link Reset */
  119. Asde = 0x00000020, /* Auto-Speed Detection Enable */
  120. Slu = 0x00000040, /* Set Link Up */
  121. Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
  122. SspeedMASK = 0x00000300, /* Speed Selection */
  123. SspeedSHIFT = 8,
  124. Sspeed10 = 0x00000000, /* 10Mb/s */
  125. Sspeed100 = 0x00000100, /* 100Mb/s */
  126. Sspeed1000 = 0x00000200, /* 1000Mb/s */
  127. Frcspd = 0x00000800, /* Force Speed */
  128. Frcdplx = 0x00001000, /* Force Duplex */
  129. SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
  130. SwdpinsloSHIFT = 18,
  131. SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
  132. SwdpioloSHIFT = 22,
  133. Devrst = 0x04000000, /* Device Reset */
  134. Rfce = 0x08000000, /* Receive Flow Control Enable */
  135. Tfce = 0x10000000, /* Transmit Flow Control Enable */
  136. Vme = 0x40000000, /* VLAN Mode Enable */
  137. };
  138. enum { /* Status */
  139. Lu = 0x00000002, /* Link Up */
  140. Tckok = 0x00000004, /* Transmit clock is running */
  141. Rbcok = 0x00000008, /* Receive clock is running */
  142. Txoff = 0x00000010, /* Transmission Paused */
  143. Tbimode = 0x00000020, /* TBI Mode Indication */
  144. SpeedMASK = 0x000000C0,
  145. Speed10 = 0x00000000, /* 10Mb/s */
  146. Speed100 = 0x00000040, /* 100Mb/s */
  147. Speed1000 = 0x00000080, /* 1000Mb/s */
  148. Mtxckok = 0x00000400, /* MTX clock is running */
  149. Pci66 = 0x00000800, /* PCI Bus speed indication */
  150. Bus64 = 0x00001000, /* PCI Bus width indication */
  151. };
  152. enum { /* Ctrl and Status */
  153. Fd = 0x00000001, /* Full-Duplex */
  154. AsdvMASK = 0x00000300,
  155. Asdv10 = 0x00000000, /* 10Mb/s */
  156. Asdv100 = 0x00000100, /* 100Mb/s */
  157. Asdv1000 = 0x00000200, /* 1000Mb/s */
  158. };
  159. enum { /* Eecd */
  160. Sk = 0x00000001, /* Clock input to the EEPROM */
  161. Cs = 0x00000002, /* Chip Select */
  162. Di = 0x00000004, /* Data Input to the EEPROM */
  163. Do = 0x00000008, /* Data Output from the EEPROM */
  164. Areq = 0x00000040, /* EEPROM Access Request */
  165. Agnt = 0x00000080, /* EEPROM Access Grant */
  166. Eepresent = 0x00000100, /* EEPROM Present */
  167. Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
  168. Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */
  169. Spi = 0x00002000, /* EEPROM is SPI not Microwire */
  170. };
  171. enum { /* Ctrlext */
  172. Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
  173. SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
  174. SwdpinshiSHIFT = 4,
  175. SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
  176. SwdpiohiSHIFT = 8,
  177. Asdchk = 0x00001000, /* ASD Check */
  178. Eerst = 0x00002000, /* EEPROM Reset */
  179. Ips = 0x00004000, /* Invert Power State */
  180. Spdbyps = 0x00008000, /* Speed Select Bypass */
  181. };
  182. enum { /* EEPROM content offsets */
  183. Ea = 0x00, /* Ethernet Address */
  184. Cf = 0x03, /* Compatibility Field */
  185. Pba = 0x08, /* Printed Board Assembly number */
  186. Icw1 = 0x0A, /* Initialization Control Word 1 */
  187. Sid = 0x0B, /* Subsystem ID */
  188. Svid = 0x0C, /* Subsystem Vendor ID */
  189. Did = 0x0D, /* Device ID */
  190. Vid = 0x0E, /* Vendor ID */
  191. Icw2 = 0x0F, /* Initialization Control Word 2 */
  192. };
  193. enum { /* Mdic */
  194. MDIdMASK = 0x0000FFFF, /* Data */
  195. MDIdSHIFT = 0,
  196. MDIrMASK = 0x001F0000, /* PHY Register Address */
  197. MDIrSHIFT = 16,
  198. MDIpMASK = 0x03E00000, /* PHY Address */
  199. MDIpSHIFT = 21,
  200. MDIwop = 0x04000000, /* Write Operation */
  201. MDIrop = 0x08000000, /* Read Operation */
  202. MDIready = 0x10000000, /* End of Transaction */
  203. MDIie = 0x20000000, /* Interrupt Enable */
  204. MDIe = 0x40000000, /* Error */
  205. };
  206. enum { /* Icr, Ics, Ims, Imc */
  207. Txdw = 0x00000001, /* Transmit Descriptor Written Back */
  208. Txqe = 0x00000002, /* Transmit Queue Empty */
  209. Lsc = 0x00000004, /* Link Status Change */
  210. Rxseq = 0x00000008, /* Receive Sequence Error */
  211. Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
  212. Rxo = 0x00000040, /* Receiver Overrun */
  213. Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
  214. Mdac = 0x00000200, /* MDIO Access Completed */
  215. Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
  216. Gpi0 = 0x00000800, /* General Purpose Interrupts */
  217. Gpi1 = 0x00001000,
  218. Gpi2 = 0x00002000,
  219. Gpi3 = 0x00004000,
  220. };
  221. /*
  222. * The Mdic register isn't implemented on the 82543GC,
  223. * the software defined pins are used instead.
  224. * These definitions work for the Intel PRO/1000 T Server Adapter.
  225. * The direction pin bits are read from the EEPROM.
  226. */
  227. enum {
  228. Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
  229. Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
  230. Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
  231. Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
  232. Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
  233. Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
  234. };
  235. enum { /* Txcw */
  236. TxcwFd = 0x00000020, /* Full Duplex */
  237. TxcwHd = 0x00000040, /* Half Duplex */
  238. TxcwPauseMASK = 0x00000180, /* Pause */
  239. TxcwPauseSHIFT = 7,
  240. TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
  241. TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
  242. TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
  243. TxcwRfiSHIFT = 12,
  244. TxcwNpr = 0x00008000, /* Next Page Request */
  245. TxcwConfig = 0x40000000, /* Transmit COnfig Control */
  246. TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
  247. };
  248. enum { /* Rctl */
  249. Rrst = 0x00000001, /* Receiver Software Reset */
  250. Ren = 0x00000002, /* Receiver Enable */
  251. Sbp = 0x00000004, /* Store Bad Packets */
  252. Upe = 0x00000008, /* Unicast Promiscuous Enable */
  253. Mpe = 0x00000010, /* Multicast Promiscuous Enable */
  254. Lpe = 0x00000020, /* Long Packet Reception Enable */
  255. LbmMASK = 0x000000C0, /* Loopback Mode */
  256. LbmOFF = 0x00000000, /* No Loopback */
  257. LbmTBI = 0x00000040, /* TBI Loopback */
  258. LbmMII = 0x00000080, /* GMII/MII Loopback */
  259. LbmXCVR = 0x000000C0, /* Transceiver Loopback */
  260. RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
  261. RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
  262. RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
  263. RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
  264. MoMASK = 0x00003000, /* Multicast Offset */
  265. Bam = 0x00008000, /* Broadcast Accept Mode */
  266. BsizeMASK = 0x00030000, /* Receive Buffer Size */
  267. Bsize2048 = 0x00000000,
  268. Bsize1024 = 0x00010000,
  269. Bsize512 = 0x00020000,
  270. Bsize256 = 0x00030000,
  271. Vfe = 0x00040000, /* VLAN Filter Enable */
  272. Cfien = 0x00080000, /* Canonical Form Indicator Enable */
  273. Cfi = 0x00100000, /* Canonical Form Indicator value */
  274. Dpf = 0x00400000, /* Discard Pause Frames */
  275. Pmcf = 0x00800000, /* Pass MAC Control Frames */
  276. Bsex = 0x02000000, /* Buffer Size Extension */
  277. Secrc = 0x04000000, /* Strip CRC from incoming packet */
  278. };
  279. enum { /* Tctl */
  280. Trst = 0x00000001, /* Transmitter Software Reset */
  281. Ten = 0x00000002, /* Transmit Enable */
  282. Psp = 0x00000008, /* Pad Short Packets */
  283. CtMASK = 0x00000FF0, /* Collision Threshold */
  284. CtSHIFT = 4,
  285. ColdMASK = 0x003FF000, /* Collision Distance */
  286. ColdSHIFT = 12,
  287. Swxoff = 0x00400000, /* Sofware XOFF Transmission */
  288. Pbe = 0x00800000, /* Packet Burst Enable */
  289. Rtlc = 0x01000000, /* Re-transmit on Late Collision */
  290. Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
  291. };
  292. enum { /* [RT]xdctl */
  293. PthreshMASK = 0x0000003F, /* Prefetch Threshold */
  294. PthreshSHIFT = 0,
  295. HthreshMASK = 0x00003F00, /* Host Threshold */
  296. HthreshSHIFT = 8,
  297. WthreshMASK = 0x003F0000, /* Writebacj Threshold */
  298. WthreshSHIFT = 16,
  299. Gran = 0x01000000, /* Granularity */
  300. };
  301. enum { /* Rxcsum */
  302. PcssMASK = 0x000000FF, /* Packet Checksum Start */
  303. PcssSHIFT = 0,
  304. Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
  305. Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
  306. };
  307. enum { /* Manc */
  308. Arpen = 0x00002000, /* Enable ARP Request Filtering */
  309. };
  310. typedef struct Rdesc { /* Receive Descriptor */
  311. uint addr[2];
  312. ushort length;
  313. ushort checksum;
  314. uchar status;
  315. uchar errors;
  316. ushort special;
  317. } Rdesc;
  318. enum { /* Rdesc status */
  319. Rdd = 0x01, /* Descriptor Done */
  320. Reop = 0x02, /* End of Packet */
  321. Ixsm = 0x04, /* Ignore Checksum Indication */
  322. Vp = 0x08, /* Packet is 802.1Q (matched VET) */
  323. Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
  324. Ipcs = 0x40, /* IP Checksum Calculated on Packet */
  325. Pif = 0x80, /* Passed in-exact filter */
  326. };
  327. enum { /* Rdesc errors */
  328. Ce = 0x01, /* CRC Error or Alignment Error */
  329. Se = 0x02, /* Symbol Error */
  330. Seq = 0x04, /* Sequence Error */
  331. Cxe = 0x10, /* Carrier Extension Error */
  332. Tcpe = 0x20, /* TCP/UDP Checksum Error */
  333. Ipe = 0x40, /* IP Checksum Error */
  334. Rxe = 0x80, /* RX Data Error */
  335. };
  336. typedef struct Tdesc { /* Legacy+Normal Transmit Descriptor */
  337. uint addr[2];
  338. uint control; /* varies with descriptor type */
  339. uint status; /* varies with descriptor type */
  340. } Tdesc;
  341. enum { /* Tdesc control */
  342. LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
  343. LenSHIFT = 0,
  344. DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
  345. DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
  346. PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
  347. Teop = 0x01000000, /* End of Packet (DD) */
  348. PtypeIP = 0x02000000, /* IP Packet Type (CD) */
  349. Ifcs = 0x02000000, /* Insert FCS (DD) */
  350. Tse = 0x04000000, /* TCP Segmentation Enable */
  351. Rs = 0x08000000, /* Report Status */
  352. Rps = 0x10000000, /* Report Status Sent */
  353. Dext = 0x20000000, /* Descriptor Extension */
  354. Vle = 0x40000000, /* VLAN Packet Enable */
  355. Ide = 0x80000000, /* Interrupt Delay Enable */
  356. };
  357. enum { /* Tdesc status */
  358. Tdd = 0x00000001, /* Descriptor Done */
  359. Ec = 0x00000002, /* Excess Collisions */
  360. Lc = 0x00000004, /* Late Collision */
  361. Tu = 0x00000008, /* Transmit Underrun */
  362. CssMASK = 0x0000FF00, /* Checksum Start Field */
  363. CssSHIFT = 8,
  364. };
  365. enum {
  366. Nrdesc = 32, /* multiple of 8 */
  367. Ntdesc = 8, /* multiple of 8 */
  368. };
  369. typedef struct Ctlr Ctlr;
  370. typedef struct Ctlr {
  371. int port;
  372. Pcidev* pcidev;
  373. Ctlr* next;
  374. int active;
  375. int id;
  376. int cls;
  377. ushort eeprom[0x40];
  378. int* nic;
  379. Lock imlock;
  380. int im; /* interrupt mask */
  381. Mii* mii;
  382. Lock slock;
  383. uint statistics[Nstatistics];
  384. uchar ra[Eaddrlen]; /* receive address */
  385. ulong mta[128]; /* multicast table array */
  386. Rdesc* rdba; /* receive descriptor base address */
  387. Block** rb; /* receive buffers */
  388. int rdh; /* receive descriptor head */
  389. int rdt; /* receive descriptor tail */
  390. Tdesc* tdba; /* transmit descriptor base address */
  391. Lock tdlock;
  392. Block** tb; /* transmit buffers */
  393. int tdh; /* transmit descriptor head */
  394. int tdt; /* transmit descriptor tail */
  395. int ett; /* early transmit threshold */
  396. int txcw;
  397. int fcrtl;
  398. int fcrth;
  399. /* bootstrap goo */
  400. Block* bqhead; /* transmission queue */
  401. Block* bqtail;
  402. } Ctlr;
  403. static Ctlr* ctlrhead;
  404. static Ctlr* ctlrtail;
  405. #define csr32r(c, r) (*((c)->nic+((r)/4)))
  406. #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
  407. static void
  408. igbeim(Ctlr* ctlr, int im)
  409. {
  410. ilock(&ctlr->imlock);
  411. ctlr->im |= im;
  412. csr32w(ctlr, Ims, ctlr->im);
  413. iunlock(&ctlr->imlock);
  414. }
  415. static void
  416. igbeattach(Ether* edev)
  417. {
  418. int ctl;
  419. Ctlr *ctlr;
  420. /*
  421. * To do here:
  422. * one-time stuff;
  423. * start off a kproc for link status change:
  424. * adjust queue length depending on speed;
  425. * flow control.
  426. * more needed here...
  427. */
  428. ctlr = edev->ctlr;
  429. igbeim(ctlr, 0);
  430. ctl = csr32r(ctlr, Rctl)|Ren;
  431. csr32w(ctlr, Rctl, ctl);
  432. ctl = csr32r(ctlr, Tctl)|Ten;
  433. csr32w(ctlr, Tctl, ctl);
  434. }
  435. static char* statistics[Nstatistics] = {
  436. "CRC Error",
  437. "Alignment Error",
  438. "Symbol Error",
  439. "RX Error",
  440. "Missed Packets",
  441. "Single Collision",
  442. "Excessive Collisions",
  443. "Multiple Collision",
  444. "Late Collisions",
  445. nil,
  446. "Collision",
  447. "Transmit Underrun",
  448. "Defer",
  449. "Transmit - No CRS",
  450. "Sequence Error",
  451. "Carrier Extension Error",
  452. "Receive Error Length",
  453. nil,
  454. "XON Received",
  455. "XON Transmitted",
  456. "XOFF Received",
  457. "XOFF Transmitted",
  458. "FC Received Unsupported",
  459. "Packets Received (64 Bytes)",
  460. "Packets Received (65-127 Bytes)",
  461. "Packets Received (128-255 Bytes)",
  462. "Packets Received (256-511 Bytes)",
  463. "Packets Received (512-1023 Bytes)",
  464. "Packets Received (1024-1522 Bytes)",
  465. "Good Packets Received",
  466. "Broadcast Packets Received",
  467. "Multicast Packets Received",
  468. "Good Packets Transmitted",
  469. nil,
  470. "Good Octets Received",
  471. nil,
  472. "Good Octets Transmitted",
  473. nil,
  474. nil,
  475. nil,
  476. "Receive No Buffers",
  477. "Receive Undersize",
  478. "Receive Fragment",
  479. "Receive Oversize",
  480. "Receive Jabber",
  481. nil,
  482. nil,
  483. nil,
  484. "Total Octets Received",
  485. nil,
  486. "Total Octets Transmitted",
  487. nil,
  488. "Total Packets Received",
  489. "Total Packets Transmitted",
  490. "Packets Transmitted (64 Bytes)",
  491. "Packets Transmitted (65-127 Bytes)",
  492. "Packets Transmitted (128-255 Bytes)",
  493. "Packets Transmitted (256-511 Bytes)",
  494. "Packets Transmitted (512-1023 Bytes)",
  495. "Packets Transmitted (1024-1522 Bytes)",
  496. "Multicast Packets Transmitted",
  497. "Broadcast Packets Transmitted",
  498. "TCP Segmentation Context Transmitted",
  499. "TCP Segmentation Context Fail",
  500. };
  501. static void
  502. txstart(Ether *edev)
  503. {
  504. int tdh, tdt, len, olen;
  505. Ctlr *ctlr = edev->ctlr;
  506. Block *bp;
  507. Tdesc *tdesc;
  508. /*
  509. * Try to fill the ring back up, moving buffers from the transmit q.
  510. */
  511. tdh = PREV(ctlr->tdh, Ntdesc);
  512. for(tdt = ctlr->tdt; tdt != tdh; tdt = NEXT(tdt, Ntdesc)){
  513. /* pull off the head of the transmission queue */
  514. if((bp = ctlr->bqhead) == nil) /* was qget(edev->oq) */
  515. break;
  516. ctlr->bqhead = bp->next;
  517. if (ctlr->bqtail == bp)
  518. ctlr->bqtail = nil;
  519. len = olen = BLEN(bp);
  520. /*
  521. * if packet is too short, make it longer rather than relying
  522. * on ethernet interface to pad it and complain so the caller
  523. * will get fixed. I don't think Psp is working right, or it's
  524. * getting cleared.
  525. */
  526. if (len < ETHERMINTU) {
  527. if (bp->rp + ETHERMINTU <= bp->lim)
  528. bp->wp = bp->rp + ETHERMINTU;
  529. else
  530. bp->wp = bp->lim;
  531. len = BLEN(bp);
  532. print("txstart: extended short pkt %d -> %d bytes\n",
  533. olen, len);
  534. }
  535. /* set up a descriptor for it */
  536. tdesc = &ctlr->tdba[tdt];
  537. tdesc->addr[0] = PCIWADDR(bp->rp);
  538. tdesc->addr[1] = 0;
  539. tdesc->control = /* Ide| */ Rs|Dext|Ifcs|Teop|DtypeDD|len;
  540. tdesc->status = 0;
  541. ctlr->tb[tdt] = bp;
  542. }
  543. ctlr->tdt = tdt;
  544. csr32w(ctlr, Tdt, tdt);
  545. igbeim(ctlr, Txdw);
  546. }
  547. static Block *
  548. fromringbuf(Ether *ether)
  549. {
  550. RingBuf *tb = &ether->tb[ether->ti];
  551. Block *bp = allocb(tb->len);
  552. memmove(bp->wp, tb->pkt, tb->len);
  553. memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen);
  554. bp->wp += tb->len;
  555. return bp;
  556. }
  557. static void
  558. igbetransmit(Ether* edev)
  559. {
  560. Block *bp;
  561. Ctlr *ctlr;
  562. Tdesc *tdesc;
  563. RingBuf *tb;
  564. int tdh;
  565. /*
  566. * For now there are no smarts here. Tuning comes later.
  567. */
  568. ctlr = edev->ctlr;
  569. ilock(&ctlr->tdlock);
  570. /*
  571. * Free any completed packets
  572. * - try to get the soft tdh to catch the tdt;
  573. * - if the packet had an underrun bump the threshold
  574. * - the Tu bit doesn't seem to ever be set, perhaps
  575. * because Rs mode is used?
  576. */
  577. tdh = ctlr->tdh;
  578. for(;;){
  579. tdesc = &ctlr->tdba[tdh];
  580. if(!(tdesc->status & Tdd))
  581. break;
  582. if(tdesc->status & Tu){
  583. ctlr->ett++;
  584. csr32w(ctlr, Ett, ctlr->ett);
  585. }
  586. tdesc->status = 0;
  587. if(ctlr->tb[tdh] != nil){
  588. freeb(ctlr->tb[tdh]);
  589. ctlr->tb[tdh] = nil;
  590. }
  591. tdh = NEXT(tdh, Ntdesc);
  592. }
  593. ctlr->tdh = tdh;
  594. /* copy packets from the software RingBuf to the transmission q */
  595. /* from boot ether83815.c */
  596. while((tb = &edev->tb[edev->ti])->owner == Interface){
  597. bp = fromringbuf(edev);
  598. /* put the buffer on the transmit queue */
  599. if(ctlr->bqhead)
  600. ctlr->bqtail->next = bp;
  601. else
  602. ctlr->bqhead = bp;
  603. ctlr->bqtail = bp;
  604. txstart(edev); /* kick transmitter */
  605. tb->owner = Host; /* give descriptor back */
  606. edev->ti = NEXT(edev->ti, edev->ntb);
  607. }
  608. iunlock(&ctlr->tdlock);
  609. }
  610. static void
  611. igbereplenish(Ctlr* ctlr)
  612. {
  613. int rdt;
  614. Block *bp;
  615. Rdesc *rdesc;
  616. rdt = ctlr->rdt;
  617. while(NEXT(rdt, Nrdesc) != ctlr->rdh){
  618. rdesc = &ctlr->rdba[rdt];
  619. if(ctlr->rb[rdt] != nil){
  620. /* nothing to do */
  621. }
  622. else if((bp = iallocb(2048)) != nil){
  623. ctlr->rb[rdt] = bp;
  624. rdesc->addr[0] = PCIWADDR(bp->rp);
  625. rdesc->addr[1] = 0;
  626. }
  627. else
  628. break;
  629. rdesc->status = 0;
  630. rdt = NEXT(rdt, Nrdesc);
  631. }
  632. ctlr->rdt = rdt;
  633. csr32w(ctlr, Rdt, rdt);
  634. }
  635. static void
  636. toringbuf(Ether *ether, Block *bp)
  637. {
  638. RingBuf *rb = &ether->rb[ether->ri];
  639. if (rb->owner == Interface) {
  640. rb->len = BLEN(bp);
  641. memmove(rb->pkt, bp->rp, rb->len);
  642. rb->owner = Host;
  643. ether->ri = NEXT(ether->ri, ether->nrb);
  644. }
  645. /* else no one is expecting packets from the network */
  646. }
  647. static void
  648. igbeinterrupt(Ureg*, void* arg)
  649. {
  650. Block *bp;
  651. Ctlr *ctlr;
  652. Ether *edev;
  653. Rdesc *rdesc;
  654. int icr, im, rdh, txdw = 0;
  655. edev = arg;
  656. ctlr = edev->ctlr;
  657. ilock(&ctlr->imlock);
  658. csr32w(ctlr, Imc, ~0);
  659. im = ctlr->im;
  660. for(icr = csr32r(ctlr, Icr); icr & ctlr->im; icr = csr32r(ctlr, Icr)){
  661. /*
  662. * Link status changed.
  663. */
  664. if(icr & (Rxseq|Lsc)){
  665. /*
  666. * should be more here...
  667. */
  668. }
  669. /*
  670. * Process any received packets.
  671. */
  672. rdh = ctlr->rdh;
  673. for(;;){
  674. rdesc = &ctlr->rdba[rdh];
  675. if(!(rdesc->status & Rdd))
  676. break;
  677. if ((rdesc->status & Reop) && rdesc->errors == 0) {
  678. bp = ctlr->rb[rdh];
  679. ctlr->rb[rdh] = nil;
  680. /*
  681. * it appears that the original 82543 needed
  682. * to have the Ethernet CRC excluded, but that
  683. * the newer chips do not?
  684. */
  685. bp->wp += rdesc->length /* -4 */;
  686. toringbuf(edev, bp);
  687. freeb(bp);
  688. } else if ((rdesc->status & Reop) && rdesc->errors)
  689. print("igbe: input packet error 0x%ux\n",
  690. rdesc->errors);
  691. rdesc->status = 0;
  692. rdh = NEXT(rdh, Nrdesc);
  693. }
  694. ctlr->rdh = rdh;
  695. if(icr & Rxdmt0)
  696. igbereplenish(ctlr);
  697. if(icr & Txdw){
  698. im &= ~Txdw;
  699. txdw++;
  700. }
  701. }
  702. ctlr->im = im;
  703. csr32w(ctlr, Ims, im);
  704. iunlock(&ctlr->imlock);
  705. if(txdw)
  706. igbetransmit(edev);
  707. }
  708. static int
  709. igbeinit(Ether* edev)
  710. {
  711. int csr, i, r, ctrl;
  712. MiiPhy *phy;
  713. Ctlr *ctlr;
  714. ctlr = edev->ctlr;
  715. /*
  716. * Set up the receive addresses.
  717. * There are 16 addresses. The first should be the MAC address.
  718. * The others are cleared and not marked valid (MS bit of Rah).
  719. */
  720. csr = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
  721. csr32w(ctlr, Ral, csr);
  722. csr = 0x80000000|(edev->ea[5]<<8)|edev->ea[4];
  723. csr32w(ctlr, Rah, csr);
  724. for(i = 1; i < 16; i++){
  725. csr32w(ctlr, Ral+i*8, 0);
  726. csr32w(ctlr, Rah+i*8, 0);
  727. }
  728. /*
  729. * Clear the Multicast Table Array.
  730. * It's a 4096 bit vector accessed as 128 32-bit registers.
  731. */
  732. for(i = 0; i < 128; i++)
  733. csr32w(ctlr, Mta+i*4, 0);
  734. /*
  735. * Receive initialisation.
  736. * Mostly defaults from the datasheet, will
  737. * need some tuning for performance:
  738. * Rctl descriptor mimimum threshold size
  739. * discard pause frames
  740. * strip CRC
  741. * Rdtr interrupt delay
  742. * Rxdctl all the thresholds
  743. */
  744. csr32w(ctlr, Rctl, 0);
  745. /*
  746. * Allocate the descriptor ring and load its
  747. * address and length into the NIC.
  748. */
  749. ctlr->rdba = xspanalloc(Nrdesc*sizeof(Rdesc), 128 /* was 16 */, 0);
  750. csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
  751. csr32w(ctlr, Rdbah, 0);
  752. csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc));
  753. /*
  754. * Initialise the ring head and tail pointers and
  755. * populate the ring with Blocks.
  756. * The datasheet says the tail pointer is set to beyond the last
  757. * descriptor hardware can process, which implies the initial
  758. * condition is Rdh == Rdt. However, experience shows Rdt must
  759. * always be 'behind' Rdh; the replenish routine ensures this.
  760. */
  761. ctlr->rdh = 0;
  762. csr32w(ctlr, Rdh, ctlr->rdh);
  763. ctlr->rdt = 0;
  764. csr32w(ctlr, Rdt, ctlr->rdt);
  765. ctlr->rb = malloc(sizeof(Block*)*Nrdesc);
  766. igbereplenish(ctlr);
  767. /*
  768. * Set up Rctl but don't enable receiver (yet).
  769. */
  770. csr32w(ctlr, Rdtr, 0);
  771. switch(ctlr->id){
  772. case i82540em:
  773. case i82540eplp:
  774. case i82541gi:
  775. case i82541gi2:
  776. case i82541pi:
  777. case i82546gb:
  778. case i82546eb:
  779. case i82547gi:
  780. csr32w(ctlr, Radv, 64);
  781. break;
  782. }
  783. csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
  784. /*
  785. * Enable checksum offload.
  786. */
  787. csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
  788. csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
  789. igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
  790. /*
  791. * Transmit initialisation.
  792. * Mostly defaults from the datasheet, will
  793. * need some tuning for performance. The normal mode will
  794. * be full-duplex and things to tune for half-duplex are
  795. * Tctl re-transmit on late collision
  796. * Tipg all IPG times
  797. * Tbt burst timer
  798. * Ait adaptive IFS throttle
  799. * and in general
  800. * Txdmac packet prefetching
  801. * Ett transmit early threshold
  802. * Tidv interrupt delay value
  803. * Txdctl all the thresholds
  804. */
  805. csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT)); /* Fd */
  806. switch(ctlr->id){
  807. default:
  808. r = 6;
  809. break;
  810. case i82543gc:
  811. case i82544ei:
  812. case i82547ei:
  813. case i82540em:
  814. case i82540eplp:
  815. case i82541gi:
  816. case i82541gi2:
  817. case i82541pi:
  818. case i82546gb:
  819. case i82546eb:
  820. case i82547gi:
  821. r = 8;
  822. break;
  823. }
  824. csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
  825. csr32w(ctlr, Ait, 0);
  826. csr32w(ctlr, Txdmac, 0);
  827. csr32w(ctlr, Tidv, 128);
  828. /*
  829. * Allocate the descriptor ring and load its
  830. * address and length into the NIC.
  831. */
  832. ctlr->tdba = xspanalloc(Ntdesc*sizeof(Tdesc), 128 /* was 16 */, 0);
  833. csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
  834. csr32w(ctlr, Tdbah, 0);
  835. csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc));
  836. /*
  837. * Initialise the ring head and tail pointers.
  838. */
  839. ctlr->tdh = 0;
  840. csr32w(ctlr, Tdh, ctlr->tdh);
  841. ctlr->tdt = 0;
  842. csr32w(ctlr, Tdt, ctlr->tdt);
  843. ctlr->tb = malloc(sizeof(Block*)*Ntdesc);
  844. // ctlr->im |= Txqe|Txdw;
  845. r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
  846. switch(ctlr->id){
  847. default:
  848. break;
  849. case i82540em:
  850. case i82540eplp:
  851. case i82547gi:
  852. case i82541pi:
  853. case i82546gb:
  854. case i82546eb:
  855. case i82541gi:
  856. case i82541gi2:
  857. r = csr32r(ctlr, Txdctl);
  858. r &= ~WthreshMASK;
  859. r |= Gran|(4<<WthreshSHIFT);
  860. csr32w(ctlr, Tadv, 64);
  861. break;
  862. }
  863. csr32w(ctlr, Txdctl, r);
  864. r = csr32r(ctlr, Tctl);
  865. r |= Ten;
  866. csr32w(ctlr, Tctl, r);
  867. if(ctlr->mii == nil || ctlr->mii->curphy == nil) {
  868. print("igbe: no mii (yet)\n");
  869. return 0;
  870. }
  871. /* wait for the link to come up */
  872. if (miistatus(ctlr->mii) < 0)
  873. return -1;
  874. print("igbe: phy: ");
  875. phy = ctlr->mii->curphy;
  876. if (phy->fd)
  877. print("full duplex");
  878. else
  879. print("half duplex");
  880. print(", %d Mb/s\n", phy->speed);
  881. /*
  882. * Flow control.
  883. */
  884. ctrl = csr32r(ctlr, Ctrl);
  885. if(phy->rfc)
  886. ctrl |= Rfce;
  887. if(phy->tfc)
  888. ctrl |= Tfce;
  889. csr32w(ctlr, Ctrl, ctrl);
  890. return 0;
  891. }
  892. static int
  893. i82543mdior(Ctlr* ctlr, int n)
  894. {
  895. int ctrl, data, i, r;
  896. /*
  897. * Read n bits from the Management Data I/O Interface.
  898. */
  899. ctrl = csr32r(ctlr, Ctrl);
  900. r = (ctrl & ~Mddo)|Mdco;
  901. data = 0;
  902. for(i = n-1; i >= 0; i--){
  903. if(csr32r(ctlr, Ctrl) & Mdd)
  904. data |= (1<<i);
  905. csr32w(ctlr, Ctrl, Mdc|r);
  906. csr32w(ctlr, Ctrl, r);
  907. }
  908. csr32w(ctlr, Ctrl, ctrl);
  909. return data;
  910. }
  911. static int
  912. i82543mdiow(Ctlr* ctlr, int bits, int n)
  913. {
  914. int ctrl, i, r;
  915. /*
  916. * Write n bits to the Management Data I/O Interface.
  917. */
  918. ctrl = csr32r(ctlr, Ctrl);
  919. r = Mdco|Mddo|ctrl;
  920. for(i = n-1; i >= 0; i--){
  921. if(bits & (1<<i))
  922. r |= Mdd;
  923. else
  924. r &= ~Mdd;
  925. csr32w(ctlr, Ctrl, Mdc|r);
  926. csr32w(ctlr, Ctrl, r);
  927. }
  928. csr32w(ctlr, Ctrl, ctrl);
  929. return 0;
  930. }
  931. static int
  932. i82543miimir(Mii* mii, int pa, int ra)
  933. {
  934. int data;
  935. Ctlr *ctlr;
  936. ctlr = mii->ctlr;
  937. /*
  938. * MII Management Interface Read.
  939. *
  940. * Preamble;
  941. * ST+OP+PHYAD+REGAD;
  942. * TA + 16 data bits.
  943. */
  944. i82543mdiow(ctlr, 0xFFFFFFFF, 32);
  945. i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
  946. data = i82543mdior(ctlr, 18);
  947. if(data & 0x10000)
  948. return -1;
  949. return data & 0xFFFF;
  950. }
  951. static int
  952. i82543miimiw(Mii* mii, int pa, int ra, int data)
  953. {
  954. Ctlr *ctlr;
  955. ctlr = mii->ctlr;
  956. /*
  957. * MII Management Interface Write.
  958. *
  959. * Preamble;
  960. * ST+OP+PHYAD+REGAD+TA + 16 data bits;
  961. * Z.
  962. */
  963. i82543mdiow(ctlr, 0xFFFFFFFF, 32);
  964. data &= 0xFFFF;
  965. data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
  966. i82543mdiow(ctlr, data, 32);
  967. return 0;
  968. }
  969. static int
  970. igbemiimir(Mii* mii, int pa, int ra)
  971. {
  972. Ctlr *ctlr;
  973. int mdic, timo;
  974. ctlr = mii->ctlr;
  975. csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
  976. mdic = 0;
  977. for(timo = 64; timo; timo--){
  978. mdic = csr32r(ctlr, Mdic);
  979. if(mdic & (MDIe|MDIready))
  980. break;
  981. microdelay(1);
  982. }
  983. if((mdic & (MDIe|MDIready)) == MDIready)
  984. return mdic & 0xFFFF;
  985. return -1;
  986. }
  987. static int
  988. igbemiimiw(Mii* mii, int pa, int ra, int data)
  989. {
  990. Ctlr *ctlr;
  991. int mdic, timo;
  992. ctlr = mii->ctlr;
  993. data &= MDIdMASK;
  994. csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
  995. mdic = 0;
  996. for(timo = 64; timo; timo--){
  997. mdic = csr32r(ctlr, Mdic);
  998. if(mdic & (MDIe|MDIready))
  999. break;
  1000. microdelay(1);
  1001. }
  1002. if((mdic & (MDIe|MDIready)) == MDIready)
  1003. return 0;
  1004. return -1;
  1005. }
  1006. static int
  1007. igbemii(Ctlr* ctlr)
  1008. {
  1009. MiiPhy *phy = (MiiPhy *)1;
  1010. int ctrl, p, r;
  1011. USED(phy);
  1012. r = csr32r(ctlr, Status);
  1013. if(r & Tbimode)
  1014. return -1;
  1015. if((ctlr->mii = malloc(sizeof(Mii))) == nil)
  1016. return -1;
  1017. ctlr->mii->ctlr = ctlr;
  1018. ctrl = csr32r(ctlr, Ctrl);
  1019. ctrl |= Slu;
  1020. switch(ctlr->id){
  1021. case i82543gc:
  1022. ctrl |= Frcdplx|Frcspd;
  1023. csr32w(ctlr, Ctrl, ctrl);
  1024. /*
  1025. * The reset pin direction (Mdro) should already
  1026. * be set from the EEPROM load.
  1027. * If it's not set this configuration is unexpected
  1028. * so bail.
  1029. */
  1030. r = csr32r(ctlr, Ctrlext);
  1031. if(!(r & Mdro))
  1032. return -1;
  1033. csr32w(ctlr, Ctrlext, r);
  1034. delay(20);
  1035. r = csr32r(ctlr, Ctrlext);
  1036. r &= ~Mdr;
  1037. csr32w(ctlr, Ctrlext, r);
  1038. delay(20);
  1039. r = csr32r(ctlr, Ctrlext);
  1040. r |= Mdr;
  1041. csr32w(ctlr, Ctrlext, r);
  1042. delay(20);
  1043. ctlr->mii->mir = i82543miimir;
  1044. ctlr->mii->miw = i82543miimiw;
  1045. break;
  1046. case i82544ei:
  1047. case i82547ei:
  1048. case i82540em:
  1049. case i82540eplp:
  1050. case i82547gi:
  1051. case i82541gi:
  1052. case i82541gi2:
  1053. case i82541pi:
  1054. case i82546gb:
  1055. case i82546eb:
  1056. ctrl &= ~(Frcdplx|Frcspd);
  1057. csr32w(ctlr, Ctrl, ctrl);
  1058. ctlr->mii->mir = igbemiimir;
  1059. ctlr->mii->miw = igbemiimiw;
  1060. break;
  1061. default:
  1062. free(ctlr->mii);
  1063. ctlr->mii = nil;
  1064. return -1;
  1065. }
  1066. if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
  1067. if (0)
  1068. print("phy trouble: phy = 0x%lux\n", (ulong)phy);
  1069. free(ctlr->mii);
  1070. ctlr->mii = nil;
  1071. return -1;
  1072. }
  1073. if (Debug)
  1074. print("oui %X phyno %d\n", phy->oui, phy->phyno);
  1075. else
  1076. USED(phy);
  1077. /*
  1078. * 8254X-specific PHY registers not in 802.3:
  1079. * 0x10 PHY specific control
  1080. * 0x14 extended PHY specific control
  1081. * Set appropriate values then reset the PHY to have
  1082. * changes noted.
  1083. */
  1084. switch(ctlr->id){
  1085. case i82547gi:
  1086. case i82541gi:
  1087. case i82541gi2:
  1088. case i82541pi:
  1089. case i82546gb:
  1090. case i82546eb:
  1091. break;
  1092. default:
  1093. r = miimir(ctlr->mii, 16);
  1094. r |= 0x0800; /* assert CRS on Tx */
  1095. r |= 0x0060; /* auto-crossover all speeds */
  1096. r |= 0x0002; /* polarity reversal enabled */
  1097. miimiw(ctlr->mii, 16, r);
  1098. r = miimir(ctlr->mii, 20);
  1099. r |= 0x0070; /* +25MHz clock */
  1100. r &= ~0x0F00;
  1101. r |= 0x0100; /* 1x downshift */
  1102. miimiw(ctlr->mii, 20, r);
  1103. miireset(ctlr->mii);
  1104. break;
  1105. }
  1106. p = 0;
  1107. if(ctlr->txcw & TxcwPs)
  1108. p |= AnaP;
  1109. if(ctlr->txcw & TxcwAs)
  1110. p |= AnaAP;
  1111. miiane(ctlr->mii, ~0, p, ~0);
  1112. return 0;
  1113. }
  1114. static int
  1115. at93c46io(Ctlr* ctlr, char* op, int data)
  1116. {
  1117. char *lp, *p;
  1118. int i, loop, eecd, r;
  1119. eecd = csr32r(ctlr, Eecd);
  1120. r = 0;
  1121. loop = -1;
  1122. lp = nil;
  1123. for(p = op; *p != '\0'; p++){
  1124. switch(*p){
  1125. default:
  1126. return -1;
  1127. case ' ':
  1128. continue;
  1129. case ':': /* start of loop */
  1130. loop = strtol(p+1, &lp, 0)-1;
  1131. lp--;
  1132. if(p == lp)
  1133. loop = 7;
  1134. p = lp;
  1135. continue;
  1136. case ';': /* end of loop */
  1137. if(lp == nil)
  1138. return -1;
  1139. loop--;
  1140. if(loop >= 0)
  1141. p = lp;
  1142. else
  1143. lp = nil;
  1144. continue;
  1145. case 'C': /* assert clock */
  1146. eecd |= Sk;
  1147. break;
  1148. case 'c': /* deassert clock */
  1149. eecd &= ~Sk;
  1150. break;
  1151. case 'D': /* next bit in 'data' byte */
  1152. if(loop < 0)
  1153. return -1;
  1154. if(data & (1<<loop))
  1155. eecd |= Di;
  1156. else
  1157. eecd &= ~Di;
  1158. break;
  1159. case 'O': /* collect data output */
  1160. i = (csr32r(ctlr, Eecd) & Do) != 0;
  1161. if(loop >= 0)
  1162. r |= (i<<loop);
  1163. else
  1164. r = i;
  1165. continue;
  1166. case 'I': /* assert data input */
  1167. eecd |= Di;
  1168. break;
  1169. case 'i': /* deassert data input */
  1170. eecd &= ~Di;
  1171. break;
  1172. case 'S': /* enable chip select */
  1173. eecd |= Cs;
  1174. break;
  1175. case 's': /* disable chip select */
  1176. eecd &= ~Cs;
  1177. break;
  1178. }
  1179. csr32w(ctlr, Eecd, eecd);
  1180. microdelay(50);
  1181. }
  1182. if(loop >= 0)
  1183. return -1;
  1184. return r;
  1185. }
  1186. static int
  1187. at93c46r(Ctlr* ctlr)
  1188. {
  1189. ushort sum;
  1190. char rop[20];
  1191. int addr, areq, bits, data, eecd, i;
  1192. eecd = csr32r(ctlr, Eecd);
  1193. if(eecd & Spi){
  1194. print("igbe: SPI EEPROM access not implemented\n");
  1195. return 0;
  1196. }
  1197. if(eecd & (Eeszaddr|Eesz256))
  1198. bits = 8;
  1199. else
  1200. bits = 6;
  1201. sum = 0;
  1202. switch(ctlr->id){
  1203. default:
  1204. areq = 0;
  1205. break;
  1206. case i82540em:
  1207. case i82540eplp:
  1208. case i82541gi:
  1209. case i82541gi2:
  1210. case i82541pi:
  1211. case i82547gi:
  1212. case i82546gb:
  1213. case i82546eb:
  1214. areq = 1;
  1215. csr32w(ctlr, Eecd, eecd|Areq);
  1216. for(i = 0; i < 1000; i++){
  1217. if((eecd = csr32r(ctlr, Eecd)) & Agnt)
  1218. break;
  1219. microdelay(5);
  1220. }
  1221. if(!(eecd & Agnt)){
  1222. print("igbe: not granted EEPROM access\n");
  1223. goto release;
  1224. }
  1225. break;
  1226. }
  1227. snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
  1228. for(addr = 0; addr < 0x40; addr++){
  1229. /*
  1230. * Read a word at address 'addr' from the Atmel AT93C46
  1231. * 3-Wire Serial EEPROM or compatible. The EEPROM access is
  1232. * controlled by 4 bits in Eecd. See the AT93C46 datasheet
  1233. * for protocol details.
  1234. */
  1235. if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
  1236. print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
  1237. goto release;
  1238. }
  1239. data = at93c46io(ctlr, ":16COc;", 0);
  1240. at93c46io(ctlr, "sic", 0);
  1241. ctlr->eeprom[addr] = data;
  1242. sum += data;
  1243. if (Debug) {
  1244. if(addr && ((addr & 0x07) == 0))
  1245. print("\n");
  1246. print(" %4.4ux", data);
  1247. }
  1248. }
  1249. if (Debug)
  1250. print("\n");
  1251. release:
  1252. if(areq)
  1253. csr32w(ctlr, Eecd, eecd & ~Areq);
  1254. return sum;
  1255. }
  1256. static void
  1257. detach(Ctlr *ctlr)
  1258. {
  1259. int r;
  1260. /*
  1261. * Perform a device reset to get the chip back to the
  1262. * power-on state, followed by an EEPROM reset to read
  1263. * the defaults for some internal registers.
  1264. */
  1265. csr32w(ctlr, Imc, ~0);
  1266. csr32w(ctlr, Rctl, 0);
  1267. csr32w(ctlr, Tctl, 0);
  1268. delay(20);
  1269. csr32w(ctlr, Ctrl, Devrst);
  1270. /* apparently needed on multi-GHz processors to avoid infinite loops */
  1271. delay(1);
  1272. while(csr32r(ctlr, Ctrl) & Devrst)
  1273. ;
  1274. csr32w(ctlr, Ctrlext, Eerst | csr32r(ctlr, Ctrlext));
  1275. delay(1);
  1276. while(csr32r(ctlr, Ctrlext) & Eerst)
  1277. ;
  1278. switch(ctlr->id){
  1279. default:
  1280. break;
  1281. case i82540em:
  1282. case i82540eplp:
  1283. case i82541gi:
  1284. case i82541gi2:
  1285. case i82541pi:
  1286. case i82547gi:
  1287. case i82546gb:
  1288. case i82546eb:
  1289. r = csr32r(ctlr, Manc);
  1290. r &= ~Arpen;
  1291. csr32w(ctlr, Manc, r);
  1292. break;
  1293. }
  1294. csr32w(ctlr, Imc, ~0);
  1295. delay(1);
  1296. while(csr32r(ctlr, Icr))
  1297. ;
  1298. }
  1299. static void
  1300. igbedetach(Ether *edev)
  1301. {
  1302. detach(edev->ctlr);
  1303. }
  1304. static void
  1305. igbeshutdown(Ether* ether)
  1306. {
  1307. print("igbeshutdown\n");
  1308. igbedetach(ether);
  1309. }
  1310. static int
  1311. igbereset(Ctlr* ctlr)
  1312. {
  1313. int ctrl, i, pause, r, swdpio, txcw;
  1314. detach(ctlr);
  1315. /*
  1316. * Read the EEPROM, validate the checksum
  1317. * then get the device back to a power-on state.
  1318. */
  1319. r = at93c46r(ctlr);
  1320. /* zero return means no SPI EEPROM access */
  1321. if (r != 0 && r != 0xBABA){
  1322. print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
  1323. return -1;
  1324. }
  1325. /*
  1326. * Snarf and set up the receive addresses.
  1327. * There are 16 addresses. The first should be the MAC address.
  1328. * The others are cleared and not marked valid (MS bit of Rah).
  1329. */
  1330. if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
  1331. BUSFNO(ctlr->pcidev->tbdf) == 1)
  1332. ctlr->eeprom[Ea+2] += 0x100; /* second interface */
  1333. for(i = Ea; i < Eaddrlen/2; i++){
  1334. if(i == Ea && ctlr->id == i82541gi && ctlr->eeprom[i] == 0xFFFF)
  1335. ctlr->eeprom[i] = 0xD000;
  1336. ctlr->ra[2*i] = ctlr->eeprom[i];
  1337. ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
  1338. }
  1339. /* set mac address of second port */
  1340. r = csr32r(ctlr, Status)>>2;
  1341. ctlr->ra[5] += r & 3; /* ea ctlr[1] = ea ctlr[0]+1 */
  1342. r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
  1343. csr32w(ctlr, Ral, r);
  1344. r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
  1345. csr32w(ctlr, Rah, r);
  1346. for(i = 1; i < 16; i++){
  1347. csr32w(ctlr, Ral+i*8, 0);
  1348. csr32w(ctlr, Rah+i*8, 0);
  1349. }
  1350. /*
  1351. * Clear the Multicast Table Array.
  1352. * It's a 4096 bit vector accessed as 128 32-bit registers.
  1353. */
  1354. memset(ctlr->mta, 0, sizeof(ctlr->mta));
  1355. for(i = 0; i < 128; i++)
  1356. csr32w(ctlr, Mta+i*4, 0);
  1357. /*
  1358. * Just in case the Eerst didn't load the defaults
  1359. * (doesn't appear to fully on the 8243GC), do it manually.
  1360. */
  1361. if (ctlr->id == i82543gc) {
  1362. txcw = csr32r(ctlr, Txcw);
  1363. txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
  1364. ctrl = csr32r(ctlr, Ctrl);
  1365. ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
  1366. if(ctlr->eeprom[Icw1] & 0x0400){
  1367. ctrl |= Fd;
  1368. txcw |= TxcwFd;
  1369. }
  1370. if(ctlr->eeprom[Icw1] & 0x0200)
  1371. ctrl |= Lrst;
  1372. if(ctlr->eeprom[Icw1] & 0x0010)
  1373. ctrl |= Ilos;
  1374. if(ctlr->eeprom[Icw1] & 0x0800)
  1375. ctrl |= Frcspd;
  1376. swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
  1377. ctrl |= swdpio<<SwdpioloSHIFT;
  1378. csr32w(ctlr, Ctrl, ctrl);
  1379. ctrl = csr32r(ctlr, Ctrlext);
  1380. ctrl &= ~(Ips|SwdpiohiMASK);
  1381. swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
  1382. if(ctlr->eeprom[Icw1] & 0x1000)
  1383. ctrl |= Ips;
  1384. ctrl |= swdpio<<SwdpiohiSHIFT;
  1385. csr32w(ctlr, Ctrlext, ctrl);
  1386. if(ctlr->eeprom[Icw2] & 0x0800)
  1387. txcw |= TxcwAne;
  1388. pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
  1389. txcw |= pause<<TxcwPauseSHIFT;
  1390. switch(pause){
  1391. default:
  1392. ctlr->fcrtl = 0x00002000;
  1393. ctlr->fcrth = 0x00004000;
  1394. txcw |= TxcwAs|TxcwPs;
  1395. break;
  1396. case 0:
  1397. ctlr->fcrtl = 0x00002000;
  1398. ctlr->fcrth = 0x00004000;
  1399. break;
  1400. case 2:
  1401. ctlr->fcrtl = 0;
  1402. ctlr->fcrth = 0;
  1403. txcw |= TxcwAs;
  1404. break;
  1405. }
  1406. ctlr->txcw = txcw;
  1407. csr32w(ctlr, Txcw, txcw);
  1408. }
  1409. /*
  1410. * Flow control - values from the datasheet.
  1411. */
  1412. csr32w(ctlr, Fcal, 0x00C28001);
  1413. csr32w(ctlr, Fcah, 0x00000100);
  1414. csr32w(ctlr, Fct, 0x00008808);
  1415. csr32w(ctlr, Fcttv, 0x00000100);
  1416. csr32w(ctlr, Fcrtl, ctlr->fcrtl);
  1417. csr32w(ctlr, Fcrth, ctlr->fcrth);
  1418. ilock(&ctlr->imlock);
  1419. csr32w(ctlr, Imc, ~0);
  1420. ctlr->im = 0; /* was = Lsc, which hangs some controllers */
  1421. csr32w(ctlr, Ims, ctlr->im);
  1422. iunlock(&ctlr->imlock);
  1423. if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0) {
  1424. print("igbe: igbemii failed\n");
  1425. return -1;
  1426. }
  1427. return 0;
  1428. }
  1429. static void
  1430. igbepci(void)
  1431. {
  1432. int port, cls;
  1433. Pcidev *p;
  1434. Ctlr *ctlr;
  1435. static int first = 1;
  1436. if (first)
  1437. first = 0;
  1438. else
  1439. return;
  1440. p = nil;
  1441. while(p = pcimatch(p, 0, 0)){
  1442. if(p->ccrb != 0x02 || p->ccru != 0)
  1443. continue;
  1444. switch((p->did<<16)|p->vid){
  1445. case i82542:
  1446. default:
  1447. continue;
  1448. case (0x1001<<16)|0x8086: /* Intel PRO/1000 F */
  1449. break;
  1450. case i82543gc:
  1451. case i82544ei:
  1452. case i82547ei:
  1453. case i82540em:
  1454. case i82540eplp:
  1455. case i82547gi:
  1456. case i82541gi:
  1457. case i82541gi2:
  1458. case i82541pi:
  1459. case i82546gb:
  1460. case i82546eb:
  1461. break;
  1462. }
  1463. /* the 82547EI is on the CSA bus, whatever that is */
  1464. port = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0);
  1465. if(port == 0){
  1466. print("igbe: can't map %d @ 0x%8.8luX\n",
  1467. p->mem[0].size, p->mem[0].bar);
  1468. continue;
  1469. }
  1470. /*
  1471. * from etherga620.c:
  1472. * If PCI Write-and-Invalidate is enabled set the max write DMA
  1473. * value to the host cache-line size (32 on Pentium or later).
  1474. */
  1475. if(p->pcr & MemWrInv){
  1476. cls = pcicfgr8(p, PciCLS) * 4;
  1477. if(cls != CACHELINESZ)
  1478. pcicfgw8(p, PciCLS, CACHELINESZ/4);
  1479. }
  1480. cls = pcicfgr8(p, PciCLS);
  1481. switch(cls){
  1482. default:
  1483. print("igbe: unexpected CLS - %d bytes\n",
  1484. cls*sizeof(long));
  1485. break;
  1486. case 0x00:
  1487. case 0xFF:
  1488. /* alphapc 164lx returns 0 */
  1489. print("igbe: unusable PciCLS: %d, using %d longs\n",
  1490. cls, CACHELINESZ/sizeof(long));
  1491. cls = CACHELINESZ/sizeof(long);
  1492. pcicfgw8(p, PciCLS, cls);
  1493. break;
  1494. case 0x08:
  1495. case 0x10:
  1496. break;
  1497. }
  1498. ctlr = malloc(sizeof(Ctlr));
  1499. ctlr->port = port;
  1500. ctlr->pcidev = p;
  1501. ctlr->id = (p->did<<16)|p->vid;
  1502. ctlr->cls = cls*4;
  1503. ctlr->nic = KADDR(ctlr->port);
  1504. if (Debug)
  1505. print("status0 %8.8uX\n", csr32r(ctlr, Status));
  1506. if(igbereset(ctlr)){
  1507. free(ctlr);
  1508. continue;
  1509. }
  1510. if (Debug)
  1511. print("status1 %8.8uX\n", csr32r(ctlr, Status));
  1512. pcisetbme(p);
  1513. if(ctlrhead != nil)
  1514. ctlrtail->next = ctlr;
  1515. else
  1516. ctlrhead = ctlr;
  1517. ctlrtail = ctlr;
  1518. }
  1519. }
  1520. int
  1521. igbepnp(Ether* edev)
  1522. {
  1523. int i;
  1524. Ctlr *ctlr;
  1525. uchar ea[Eaddrlen];
  1526. if(ctlrhead == nil)
  1527. igbepci();
  1528. /*
  1529. * Any adapter matches if no edev->port is supplied,
  1530. * otherwise the ports must match.
  1531. */
  1532. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  1533. if(ctlr->active)
  1534. continue;
  1535. if(edev->port == 0 || edev->port == ctlr->port){
  1536. ctlr->active = 1;
  1537. break;
  1538. }
  1539. }
  1540. if(ctlr == nil)
  1541. return -1;
  1542. edev->ctlr = ctlr;
  1543. edev->port = ctlr->port;
  1544. edev->irq = ctlr->pcidev->intl;
  1545. edev->tbdf = ctlr->pcidev->tbdf;
  1546. // edev->mbps = 1000;
  1547. /*
  1548. * Check if the adapter's station address is to be overridden.
  1549. * If not, read it from the EEPROM and set in ether->ea prior to
  1550. * loading the station address in the hardware.
  1551. */
  1552. memset(ea, 0, Eaddrlen);
  1553. if(memcmp(ea, edev->ea, Eaddrlen) == 0){
  1554. for(i = 0; i < Eaddrlen/2; i++){
  1555. edev->ea[2*i] = ctlr->eeprom[i];
  1556. edev->ea[2*i+1] = ctlr->eeprom[i]>>8;
  1557. }
  1558. }
  1559. igbeinit(edev);
  1560. /*
  1561. * Linkage to the generic ethernet driver.
  1562. */
  1563. edev->attach = igbeattach;
  1564. edev->transmit = igbetransmit;
  1565. edev->interrupt = igbeinterrupt;
  1566. edev->detach = igbedetach;
  1567. return 0;
  1568. }