uart.c 1.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869
  1. #include "u.h"
  2. #include "lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. enum
  8. {
  9. /* ctl[0] bits */
  10. Parity= 1<<0,
  11. Even= 1<<1,
  12. Stop2= 1<<2,
  13. Bits8= 1<<3,
  14. SCE= 1<<4, /* synchronous clock enable */
  15. RCE= 1<<5, /* rx on falling edge of clock */
  16. TCE= 1<<6, /* tx on falling edge of clock */
  17. /* ctl[3] bits */
  18. Rena= 1<<0, /* receiver enable */
  19. Tena= 1<<1, /* transmitter enable */
  20. Break= 1<<2, /* force TXD3 low */
  21. Rintena= 1<<3, /* enable receive interrupt */
  22. Tintena= 1<<4, /* enable transmitter interrupt */
  23. Loopback= 1<<5, /* loop back data */
  24. /* data bits */
  25. DEparity= 1<<8, /* parity error */
  26. DEframe= 1<<9, /* framing error */
  27. DEoverrun= 1<<10, /* overrun error */
  28. /* status[0] bits */
  29. Tint= 1<<0, /* transmit fifo half full interrupt */
  30. Rint0= 1<<1, /* receiver fifo 1/3-2/3 full */
  31. Rint1= 1<<2, /* receiver fifo not empty and receiver idle */
  32. Breakstart= 1<<3,
  33. Breakend= 1<<4,
  34. Fifoerror= 1<<5, /* fifo error */
  35. /* status[1] bits */
  36. Tbusy= 1<<0, /* transmitting */
  37. Rnotempty= 1<<1, /* receive fifo not empty */
  38. Tnotfull= 1<<2, /* transmit fifo not full */
  39. ParityError= 1<<3,
  40. FrameError= 1<<4,
  41. Overrun= 1<<5,
  42. };
  43. Uartregs *uart3regs = (Uartregs*)UART3REGS;
  44. /*
  45. * for iprint, just write it
  46. */
  47. void
  48. serialputs(char *str, int n)
  49. {
  50. Uartregs *ur;
  51. ur = uart3regs;
  52. while(n-- > 0){
  53. /* wait for output ready */
  54. while((ur->status[1] & Tnotfull) == 0)
  55. ;
  56. ur->data = *str++;
  57. }
  58. while((ur->status[1] & Tbusy))
  59. ;
  60. }