ether83815.c 23 KB

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  1. /*
  2. * National Semiconductor DP83815
  3. *
  4. * Supports only internal PHY and has been tested on:
  5. * Netgear FA311TX (using Netgear DS108 10/100 hub)
  6. * To do:
  7. * check Ethernet address;
  8. * test autonegotiation on 10 Mbit, and 100 Mbit full duplex;
  9. * external PHY via MII (should be common code for MII);
  10. * thresholds;
  11. * ring sizing;
  12. * physical link changes/disconnect;
  13. * push initialisation back to attach.
  14. *
  15. * C H Forsyth, forsyth@vitanuova.com, 18th June 2001.
  16. */
  17. #include "u.h"
  18. #include "../port/lib.h"
  19. #include "mem.h"
  20. #include "dat.h"
  21. #include "fns.h"
  22. #include "io.h"
  23. #include "../port/error.h"
  24. #include "../port/netif.h"
  25. #include "etherif.h"
  26. #define DEBUG (1)
  27. #define debug if(DEBUG)print
  28. enum {
  29. Nrde = 64,
  30. Ntde = 64,
  31. };
  32. #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
  33. typedef struct Des {
  34. ulong next;
  35. int cmdsts;
  36. ulong addr;
  37. Block* bp;
  38. } Des;
  39. enum { /* cmdsts */
  40. Own = 1<<31, /* set by data producer to hand to consumer */
  41. More = 1<<30, /* more of packet in next descriptor */
  42. Intr = 1<<29, /* interrupt when device is done with it */
  43. Supcrc = 1<<28, /* suppress crc on transmit */
  44. Inccrc = 1<<28, /* crc included on receive (always) */
  45. Ok = 1<<27, /* packet ok */
  46. Size = 0xFFF, /* packet size in bytes */
  47. /* transmit */
  48. Txa = 1<<26, /* transmission aborted */
  49. Tfu = 1<<25, /* transmit fifo underrun */
  50. Crs = 1<<24, /* carrier sense lost */
  51. Td = 1<<23, /* transmission deferred */
  52. Ed = 1<<22, /* excessive deferral */
  53. Owc = 1<<21, /* out of window collision */
  54. Ec = 1<<20, /* excessive collisions */
  55. /* 19-16 collision count */
  56. /* receive */
  57. Rxa = 1<<26, /* receive aborted (same as Rxo) */
  58. Rxo = 1<<25, /* receive overrun */
  59. Dest = 3<<23, /* destination class */
  60. Drej= 0<<23, /* packet was rejected */
  61. Duni= 1<<23, /* unicast */
  62. Dmulti= 2<<23, /* multicast */
  63. Dbroad= 3<<23, /* broadcast */
  64. Long = 1<<22, /* too long packet received */
  65. Runt = 1<<21, /* packet less than 64 bytes */
  66. Ise = 1<<20, /* invalid symbol */
  67. Crce = 1<<19, /* invalid crc */
  68. Fae = 1<<18, /* frame alignment error */
  69. Lbp = 1<<17, /* loopback packet */
  70. Col = 1<<16, /* collision during receive */
  71. };
  72. enum { /* Variants */
  73. Nat83815 = (0x0020<<16)|0x100B,
  74. };
  75. typedef struct Ctlr Ctlr;
  76. typedef struct Ctlr {
  77. int port;
  78. Pcidev* pcidev;
  79. Ctlr* next;
  80. int active;
  81. int id; /* (pcidev->did<<16)|pcidev->vid */
  82. ushort srom[0xB+1];
  83. uchar sromea[Eaddrlen]; /* MAC address */
  84. uchar fd; /* option or auto negotiation */
  85. int mbps;
  86. Lock lock;
  87. Des* rdr; /* receive descriptor ring */
  88. int nrdr; /* size of rdr */
  89. int rdrx; /* index into rdr */
  90. Lock tlock;
  91. Des* tdr; /* transmit descriptor ring */
  92. int ntdr; /* size of tdr */
  93. int tdrh; /* host index into tdr */
  94. int tdri; /* interface index into tdr */
  95. int ntq; /* descriptors active */
  96. int ntqmax;
  97. ulong rxa; /* receive statistics */
  98. ulong rxo;
  99. ulong rlong;
  100. ulong runt;
  101. ulong ise;
  102. ulong crce;
  103. ulong fae;
  104. ulong lbp;
  105. ulong col;
  106. ulong rxsovr;
  107. ulong rxorn;
  108. ulong txa; /* transmit statistics */
  109. ulong tfu;
  110. ulong crs;
  111. ulong td;
  112. ulong ed;
  113. ulong owc;
  114. ulong ec;
  115. ulong txurn;
  116. ulong dperr; /* system errors */
  117. ulong rmabt;
  118. ulong rtabt;
  119. ulong sserr;
  120. ulong rxsover;
  121. } Ctlr;
  122. static Ctlr* ctlrhead;
  123. static Ctlr* ctlrtail;
  124. enum {
  125. /* registers (could memory map) */
  126. Rcr= 0x00, /* command register */
  127. Rst= 1<<8,
  128. Rxr= 1<<5, /* receiver reset */
  129. Txr= 1<<4, /* transmitter reset */
  130. Rxd= 1<<3, /* receiver disable */
  131. Rxe= 1<<2, /* receiver enable */
  132. Txd= 1<<1, /* transmitter disable */
  133. Txe= 1<<0, /* transmitter enable */
  134. Rcfg= 0x04, /* configuration */
  135. Lnksts= 1<<31, /* link good */
  136. Speed100= 1<<30, /* 100 Mb/s link */
  137. Fdup= 1<<29, /* full duplex */
  138. Pol= 1<<28, /* polarity reversal (10baseT) */
  139. Aneg_dn= 1<<27, /* autonegotiation done */
  140. Pint_acen= 1<<17, /* PHY interrupt auto clear enable */
  141. Pause_adv= 1<<16, /* advertise pause during auto neg */
  142. Paneg_ena= 1<<13, /* auto negotiation enable */
  143. Paneg_all= 7<<13, /* auto negotiation enable 10/100 half & full */
  144. Ext_phy= 1<<12, /* enable MII for external PHY */
  145. Phy_rst= 1<<10, /* reset internal PHY */
  146. Phy_dis= 1<<9, /* disable internal PHY (eg, low power) */
  147. Req_alg= 1<<7, /* PCI bus request: set means less aggressive */
  148. Sb= 1<<6, /* single slot back-off not random */
  149. Pow= 1<<5, /* out of window timer selection */
  150. Exd= 1<<4, /* disable excessive deferral timer */
  151. Pesel= 1<<3, /* parity error algorithm selection */
  152. Brom_dis= 1<<2, /* disable boot rom interface */
  153. Bem= 1<<0, /* big-endian mode */
  154. Rmear= 0x08, /* eeprom access */
  155. Mdc= 1<<6, /* MII mangement check */
  156. Mddir= 1<<5, /* MII management direction */
  157. Mdio= 1<<4, /* MII mangement data */
  158. Eesel= 1<<3, /* EEPROM chip select */
  159. Eeclk= 1<<2, /* EEPROM clock */
  160. Eedo= 1<<1, /* EEPROM data out (from chip) */
  161. Eedi= 1<<0, /* EEPROM data in (to chip) */
  162. Rptscr= 0x0C, /* pci test control */
  163. Risr= 0x10, /* interrupt status */
  164. Txrcmp= 1<<25, /* transmit reset complete */
  165. Rxrcmp= 1<<24, /* receiver reset complete */
  166. Dperr= 1<<23, /* detected parity error */
  167. Sserr= 1<<22, /* signalled system error */
  168. Rmabt= 1<<21, /* received master abort */
  169. Rtabt= 1<<20, /* received target abort */
  170. Rxsovr= 1<<16, /* RX status FIFO overrun */
  171. Hiberr= 1<<15, /* high bits error set (OR of 25-16) */
  172. Phy= 1<<14, /* PHY interrupt */
  173. Pme= 1<<13, /* power management event (wake online) */
  174. Swi= 1<<12, /* software interrupt */
  175. Mib= 1<<11, /* MIB service */
  176. Txurn= 1<<10, /* TX underrun */
  177. Txidle= 1<<9, /* TX idle */
  178. Txerr= 1<<8, /* TX packet error */
  179. Txdesc= 1<<7, /* TX descriptor (with Intr bit done) */
  180. Txok= 1<<6, /* TX ok */
  181. Rxorn= 1<<5, /* RX overrun */
  182. Rxidle= 1<<4, /* RX idle */
  183. Rxearly= 1<<3, /* RX early threshold */
  184. Rxerr= 1<<2, /* RX packet error */
  185. Rxdesc= 1<<1, /* RX descriptor (with Intr bit done) */
  186. Rxok= 1<<0, /* RX ok */
  187. Rimr= 0x14, /* interrupt mask */
  188. Rier= 0x18, /* interrupt enable */
  189. Ie= 1<<0, /* interrupt enable */
  190. Rtxdp= 0x20, /* transmit descriptor pointer */
  191. Rtxcfg= 0x24, /* transmit configuration */
  192. Csi= 1<<31, /* carrier sense ignore (needed for full duplex) */
  193. Hbi= 1<<30, /* heartbeat ignore (needed for full duplex) */
  194. Atp= 1<<28, /* automatic padding of runt packets */
  195. Mxdma= 7<<20, /* maximum dma transfer field */
  196. Mxdma32= 4<<20, /* 4x32-bit words (32 bytes) */
  197. Mxdma64= 5<<20, /* 8x32-bit words (64 bytes) */
  198. Flth= 0x3F<<8, /* Tx fill threshold, units of 32 bytes (must be > Mxdma) */
  199. Drth= 0x3F<<0, /* Tx drain threshold (units of 32 bytes) */
  200. Flth128= 4<<8, /* fill at 128 bytes */
  201. Drth512= 16<<0, /* drain at 512 bytes */
  202. Rrxdp= 0x30, /* receive descriptor pointer */
  203. Rrxcfg= 0x34, /* receive configuration */
  204. Atx= 1<<28, /* accept transmit packets (needed for full duplex) */
  205. Rdrth= 0x1F<<1, /* Rx drain threshold (units of 32 bytes) */
  206. Rdrth64= 2<<1, /* drain at 64 bytes */
  207. Rccsr= 0x3C, /* CLKRUN control/status */
  208. Pmests= 1<<15, /* PME status */
  209. Rwcsr= 0x40, /* wake on lan control/status */
  210. Rpcr= 0x44, /* pause control/status */
  211. Rrfcr= 0x48, /* receive filter/match control */
  212. Rfen= 1<<31, /* receive filter enable */
  213. Aab= 1<<30, /* accept all broadcast */
  214. Aam= 1<<29, /* accept all multicast */
  215. Aau= 1<<28, /* accept all unicast */
  216. Apm= 1<<27, /* accept on perfect match */
  217. Apat= 0xF<<23, /* accept on pattern match */
  218. Aarp= 1<<22, /* accept ARP */
  219. Mhen= 1<<21, /* multicast hash enable */
  220. Uhen= 1<<20, /* unicast hash enable */
  221. Ulm= 1<<19, /* U/L bit mask */
  222. /* bits 0-9 are rfaddr */
  223. Rrfdr= 0x4C, /* receive filter/match data */
  224. Rbrar= 0x50, /* boot rom address */
  225. Rbrdr= 0x54, /* boot rom data */
  226. Rsrr= 0x58, /* silicon revision */
  227. Rmibc= 0x5C, /* MIB control */
  228. /* 60-78 MIB data */
  229. /* PHY registers */
  230. Rbmcr= 0x80, /* basic mode configuration */
  231. Reset= 1<<15,
  232. Sel100= 1<<13, /* select 100Mb/sec if no auto neg */
  233. Anena= 1<<12, /* auto negotiation enable */
  234. Anrestart= 1<<9, /* restart auto negotiation */
  235. Selfdx= 1<<8, /* select full duplex if no auto neg */
  236. Rbmsr= 0x84, /* basic mode status */
  237. Ancomp= 1<<5, /* autonegotiation complete */
  238. Rphyidr1= 0x88,
  239. Rphyidr2= 0x8C,
  240. Ranar= 0x90, /* autonegotiation advertisement */
  241. Ranlpar= 0x94, /* autonegotiation link partner ability */
  242. Raner= 0x98, /* autonegotiation expansion */
  243. Rannptr= 0x9C, /* autonegotiation next page TX */
  244. Rphysts= 0xC0, /* PHY status */
  245. Rmicr= 0xC4, /* MII control */
  246. Inten= 1<<1, /* PHY interrupt enable */
  247. Rmisr= 0xC8, /* MII status */
  248. Rfcscr= 0xD0, /* false carrier sense counter */
  249. Rrecr= 0xD4, /* receive error counter */
  250. Rpcsr= 0xD8, /* 100Mb config/status */
  251. Rphycr= 0xE4, /* PHY control */
  252. Rtbscr= 0xE8, /* 10BaseT status/control */
  253. };
  254. /*
  255. * eeprom addresses
  256. * 7 to 9 (16 bit words): mac address, shifted and reversed
  257. */
  258. #define csr32r(c, r) (inl((c)->port+(r)))
  259. #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
  260. #define csr16r(c, r) (ins((c)->port+(r)))
  261. #define csr16w(c, r, l) (outs((c)->port+(r), (ulong)(l)))
  262. static void
  263. dumpcregs(Ctlr *ctlr)
  264. {
  265. int i;
  266. for(i=0; i<=0x5C; i+=4)
  267. print("%2.2ux %8.8lux\n", i, csr32r(ctlr, i));
  268. }
  269. static void
  270. promiscuous(void* arg, int on)
  271. {
  272. Ctlr *ctlr;
  273. ulong w;
  274. ctlr = ((Ether*)arg)->ctlr;
  275. ilock(&ctlr->lock);
  276. w = csr32r(ctlr, Rrfcr);
  277. if(on != ((w&Aau)!=0)){
  278. csr32w(ctlr, Rrfcr, w & ~Rfen);
  279. csr32w(ctlr, Rrfcr, Rfen | (w ^ Aau));
  280. }
  281. iunlock(&ctlr->lock);
  282. }
  283. static void
  284. attach(Ether* ether)
  285. {
  286. Ctlr *ctlr;
  287. ctlr = ether->ctlr;
  288. ilock(&ctlr->lock);
  289. if(0)
  290. dumpcregs(ctlr);
  291. csr32w(ctlr, Rcr, Rxe);
  292. iunlock(&ctlr->lock);
  293. }
  294. static long
  295. ifstat(Ether* ether, void* a, long n, ulong offset)
  296. {
  297. Ctlr *ctlr;
  298. char *buf, *p;
  299. int i, l, len;
  300. ctlr = ether->ctlr;
  301. ether->crcs = ctlr->crce;
  302. ether->frames = ctlr->runt+ctlr->ise+ctlr->rlong+ctlr->fae;
  303. ether->buffs = ctlr->rxorn+ctlr->tfu;
  304. ether->overflows = ctlr->rxsovr;
  305. if(n == 0)
  306. return 0;
  307. p = malloc(READSTR);
  308. l = snprint(p, READSTR, "Rxa: %lud\n", ctlr->rxa);
  309. l += snprint(p+l, READSTR-l, "Rxo: %lud\n", ctlr->rxo);
  310. l += snprint(p+l, READSTR-l, "Rlong: %lud\n", ctlr->rlong);
  311. l += snprint(p+l, READSTR-l, "Runt: %lud\n", ctlr->runt);
  312. l += snprint(p+l, READSTR-l, "Ise: %lud\n", ctlr->ise);
  313. l += snprint(p+l, READSTR-l, "Fae: %lud\n", ctlr->fae);
  314. l += snprint(p+l, READSTR-l, "Lbp: %lud\n", ctlr->lbp);
  315. l += snprint(p+l, READSTR-l, "Tfu: %lud\n", ctlr->tfu);
  316. l += snprint(p+l, READSTR-l, "Txa: %lud\n", ctlr->txa);
  317. l += snprint(p+l, READSTR-l, "CRC Error: %lud\n", ctlr->crce);
  318. l += snprint(p+l, READSTR-l, "Collision Seen: %lud\n", ctlr->col);
  319. l += snprint(p+l, READSTR-l, "Frame Too Long: %lud\n", ctlr->rlong);
  320. l += snprint(p+l, READSTR-l, "Runt Frame: %lud\n", ctlr->runt);
  321. l += snprint(p+l, READSTR-l, "Rx Underflow Error: %lud\n", ctlr->rxorn);
  322. l += snprint(p+l, READSTR-l, "Tx Underrun: %lud\n", ctlr->txurn);
  323. l += snprint(p+l, READSTR-l, "Excessive Collisions: %lud\n", ctlr->ec);
  324. l += snprint(p+l, READSTR-l, "Late Collision: %lud\n", ctlr->owc);
  325. l += snprint(p+l, READSTR-l, "Loss of Carrier: %lud\n", ctlr->crs);
  326. l += snprint(p+l, READSTR-l, "Parity: %lud\n", ctlr->dperr);
  327. l += snprint(p+l, READSTR-l, "Aborts: %lud\n", ctlr->rmabt+ctlr->rtabt);
  328. l += snprint(p+l, READSTR-l, "RX Status overrun: %lud\n", ctlr->rxsover);
  329. snprint(p+l, READSTR-l, "ntqmax: %d\n", ctlr->ntqmax);
  330. ctlr->ntqmax = 0;
  331. buf = a;
  332. len = readstr(offset, buf, n, p);
  333. if(offset > l)
  334. offset -= l;
  335. else
  336. offset = 0;
  337. buf += len;
  338. n -= len;
  339. l = snprint(p, READSTR, "srom:");
  340. for(i = 0; i < nelem(ctlr->srom); i++){
  341. if(i && ((i & 0x0F) == 0))
  342. l += snprint(p+l, READSTR-l, "\n ");
  343. l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->srom[i]);
  344. }
  345. snprint(p+l, READSTR-l, "\n");
  346. len += readstr(offset, buf, n, p);
  347. free(p);
  348. return len;
  349. }
  350. static void
  351. txstart(Ether* ether)
  352. {
  353. Ctlr *ctlr;
  354. Block *bp;
  355. Des *des;
  356. int started;
  357. ctlr = ether->ctlr;
  358. started = 0;
  359. while(ctlr->ntq < ctlr->ntdr-1){
  360. bp = qget(ether->oq);
  361. if(bp == nil)
  362. break;
  363. des = &ctlr->tdr[ctlr->tdrh];
  364. des->bp = bp;
  365. des->addr = PADDR(bp->rp);
  366. ctlr->ntq++;
  367. coherence();
  368. des->cmdsts = Own | BLEN(bp);
  369. ctlr->tdrh = NEXT(ctlr->tdrh, ctlr->ntdr);
  370. started = 1;
  371. }
  372. if(started){
  373. coherence();
  374. csr32w(ctlr, Rcr, Txe); /* prompt */
  375. }
  376. if(ctlr->ntq > ctlr->ntqmax)
  377. ctlr->ntqmax = ctlr->ntq;
  378. }
  379. static void
  380. transmit(Ether* ether)
  381. {
  382. Ctlr *ctlr;
  383. ctlr = ether->ctlr;
  384. ilock(&ctlr->tlock);
  385. txstart(ether);
  386. iunlock(&ctlr->tlock);
  387. }
  388. static void
  389. txrxcfg(Ctlr *ctlr, int txdrth)
  390. {
  391. ulong rx, tx;
  392. rx = csr32r(ctlr, Rrxcfg);
  393. tx = csr32r(ctlr, Rtxcfg);
  394. if(ctlr->fd){
  395. rx |= Atx;
  396. tx |= Csi | Hbi;
  397. }else{
  398. rx &= ~Atx;
  399. tx &= ~(Csi | Hbi);
  400. }
  401. tx &= ~(Mxdma|Drth|Flth);
  402. tx |= Mxdma64 | Flth128 | txdrth;
  403. csr32w(ctlr, Rtxcfg, tx);
  404. rx &= ~(Mxdma|Rdrth);
  405. rx |= Mxdma64 | Rdrth64;
  406. csr32w(ctlr, Rrxcfg, rx);
  407. }
  408. static void
  409. interrupt(Ureg*, void* arg)
  410. {
  411. Ctlr *ctlr;
  412. Ether *ether;
  413. int len, status, cmdsts;
  414. Des *des;
  415. Block *bp;
  416. ether = arg;
  417. ctlr = ether->ctlr;
  418. while((status = csr32r(ctlr, Risr)) != 0){
  419. status &= ~(Pme|Mib);
  420. if(status & Hiberr){
  421. if(status & Rxsovr)
  422. ctlr->rxsover++;
  423. if(status & Sserr)
  424. ctlr->sserr++;
  425. if(status & Dperr)
  426. ctlr->dperr++;
  427. if(status & Rmabt)
  428. ctlr->rmabt++;
  429. if(status & Rtabt)
  430. ctlr->rtabt++;
  431. status &= ~(Hiberr|Txrcmp|Rxrcmp|Rxsovr|Dperr|Sserr|Rmabt|Rtabt);
  432. }
  433. /*
  434. * Received packets.
  435. */
  436. if(status & (Rxdesc|Rxok|Rxerr|Rxearly|Rxorn)){
  437. des = &ctlr->rdr[ctlr->rdrx];
  438. while((cmdsts = des->cmdsts) & Own){
  439. if((cmdsts&Ok) == 0){
  440. if(cmdsts & Rxa)
  441. ctlr->rxa++;
  442. if(cmdsts & Rxo)
  443. ctlr->rxo++;
  444. if(cmdsts & Long)
  445. ctlr->rlong++;
  446. if(cmdsts & Runt)
  447. ctlr->runt++;
  448. if(cmdsts & Ise)
  449. ctlr->ise++;
  450. if(cmdsts & Crce)
  451. ctlr->crce++;
  452. if(cmdsts & Fae)
  453. ctlr->fae++;
  454. if(cmdsts & Lbp)
  455. ctlr->lbp++;
  456. if(cmdsts & Col)
  457. ctlr->col++;
  458. }
  459. else if(bp = iallocb(Rbsz)){
  460. len = (cmdsts&Size)-4;
  461. des->bp->wp = des->bp->rp+len;
  462. etheriq(ether, des->bp, 1);
  463. des->bp = bp;
  464. des->addr = PADDR(bp->rp);
  465. coherence();
  466. }
  467. des->cmdsts = Rbsz;
  468. coherence();
  469. ctlr->rdrx = NEXT(ctlr->rdrx, ctlr->nrdr);
  470. des = &ctlr->rdr[ctlr->rdrx];
  471. }
  472. status &= ~(Rxdesc|Rxok|Rxerr|Rxearly|Rxorn);
  473. }
  474. /*
  475. * Check the transmit side:
  476. * check for Transmit Underflow and Adjust
  477. * the threshold upwards;
  478. * free any transmitted buffers and try to
  479. * top-up the ring.
  480. */
  481. if(status & Txurn){
  482. ctlr->txurn++;
  483. ilock(&ctlr->lock);
  484. /* change threshold */
  485. iunlock(&ctlr->lock);
  486. status &= ~(Txurn);
  487. }
  488. ilock(&ctlr->tlock);
  489. while(ctlr->ntq){
  490. des = &ctlr->tdr[ctlr->tdri];
  491. cmdsts = des->cmdsts;
  492. if(cmdsts & Own)
  493. break;
  494. if((cmdsts & Ok) == 0){
  495. if(cmdsts & Txa)
  496. ctlr->txa++;
  497. if(cmdsts & Tfu)
  498. ctlr->tfu++;
  499. if(cmdsts & Td)
  500. ctlr->td++;
  501. if(cmdsts & Ed)
  502. ctlr->ed++;
  503. if(cmdsts & Owc)
  504. ctlr->owc++;
  505. if(cmdsts & Ec)
  506. ctlr->ec++;
  507. ether->oerrs++;
  508. }
  509. freeb(des->bp);
  510. des->bp = nil;
  511. des->cmdsts = 0;
  512. ctlr->ntq--;
  513. ctlr->tdri = NEXT(ctlr->tdri, ctlr->ntdr);
  514. }
  515. txstart(ether);
  516. iunlock(&ctlr->tlock);
  517. status &= ~(Txurn|Txidle|Txerr|Txdesc|Txok);
  518. /*
  519. * Anything left not catered for?
  520. */
  521. if(status)
  522. print("#l%d: status %8.8uX\n", ether->ctlrno, status);
  523. }
  524. }
  525. static void
  526. ctlrinit(Ether* ether)
  527. {
  528. Ctlr *ctlr;
  529. Des *des, *last;
  530. ctlr = ether->ctlr;
  531. /*
  532. * Allocate and initialise the receive ring;
  533. * allocate and initialise the transmit ring;
  534. * unmask interrupts and start the transmit side
  535. */
  536. ctlr->rdr = malloc(ctlr->nrdr*sizeof(Des));
  537. last = nil;
  538. for(des = ctlr->rdr; des < &ctlr->rdr[ctlr->nrdr]; des++){
  539. des->bp = iallocb(Rbsz);
  540. des->cmdsts = Rbsz;
  541. des->addr = PADDR(des->bp->rp);
  542. if(last != nil)
  543. last->next = PADDR(des);
  544. last = des;
  545. }
  546. ctlr->rdr[ctlr->nrdr-1].next = PADDR(ctlr->rdr);
  547. ctlr->rdrx = 0;
  548. csr32w(ctlr, Rrxdp, PADDR(ctlr->rdr));
  549. ctlr->tdr = xspanalloc(ctlr->ntdr*sizeof(Des), 8*sizeof(ulong), 0);
  550. last = nil;
  551. for(des = ctlr->tdr; des < &ctlr->tdr[ctlr->ntdr]; des++){
  552. des->cmdsts = 0;
  553. des->bp = nil;
  554. des->addr = ~0;
  555. if(last != nil)
  556. last->next = PADDR(des);
  557. last = des;
  558. }
  559. ctlr->tdr[ctlr->ntdr-1].next = PADDR(ctlr->tdr);
  560. ctlr->tdrh = 0;
  561. ctlr->tdri = 0;
  562. csr32w(ctlr, Rtxdp, PADDR(ctlr->tdr));
  563. txrxcfg(ctlr, Drth512);
  564. csr32w(ctlr, Rimr, Dperr|Sserr|Rmabt|Rtabt|Rxsovr|Hiberr|Txurn|Txerr|Txdesc|Txok|Rxorn|Rxerr|Rxdesc|Rxok); /* Phy|Pme|Mib */
  565. csr32r(ctlr, Risr); /* clear status */
  566. csr32w(ctlr, Rier, Ie);
  567. }
  568. static void
  569. eeclk(Ctlr *ctlr, int clk)
  570. {
  571. csr32w(ctlr, Rmear, Eesel | clk);
  572. microdelay(2);
  573. }
  574. static void
  575. eeidle(Ctlr *ctlr)
  576. {
  577. int i;
  578. eeclk(ctlr, 0);
  579. eeclk(ctlr, Eeclk);
  580. for(i=0; i<25; i++){
  581. eeclk(ctlr, 0);
  582. eeclk(ctlr, Eeclk);
  583. }
  584. eeclk(ctlr, 0);
  585. csr32w(ctlr, Rmear, 0);
  586. microdelay(2);
  587. }
  588. static int
  589. eegetw(Ctlr *ctlr, int a)
  590. {
  591. int d, i, w;
  592. eeidle(ctlr);
  593. eeclk(ctlr, 0);
  594. eeclk(ctlr, Eeclk);
  595. d = 0x180 | a;
  596. for(i=0x400; i; i>>=1){
  597. if(d & i)
  598. csr32w(ctlr, Rmear, Eesel|Eedi);
  599. else
  600. csr32w(ctlr, Rmear, Eesel);
  601. eeclk(ctlr, Eeclk);
  602. eeclk(ctlr, 0);
  603. microdelay(2);
  604. }
  605. w = 0;
  606. for(i=0x8000; i; i >>= 1){
  607. eeclk(ctlr, Eeclk);
  608. if(csr32r(ctlr, Rmear) & Eedo)
  609. w |= i;
  610. microdelay(2);
  611. eeclk(ctlr, 0);
  612. }
  613. eeidle(ctlr);
  614. return w;
  615. }
  616. static void
  617. softreset(Ctlr* ctlr, int resetphys)
  618. {
  619. int i, w;
  620. /*
  621. * Soft-reset the controller
  622. */
  623. csr32w(ctlr, Rcr, Rst);
  624. for(i=0;; i++){
  625. if(i > 100)
  626. panic("ns83815: soft reset did not complete");
  627. microdelay(250);
  628. if((csr32r(ctlr, Rcr) & Rst) == 0)
  629. break;
  630. delay(1);
  631. }
  632. csr32w(ctlr, Rccsr, Pmests);
  633. csr32w(ctlr, Rccsr, 0);
  634. csr32w(ctlr, Rcfg, csr32r(ctlr, Rcfg) | Pint_acen);
  635. if(resetphys){
  636. /*
  637. * Soft-reset the PHY
  638. */
  639. csr32w(ctlr, Rbmcr, Reset);
  640. for(i=0;; i++){
  641. if(i > 100)
  642. panic("ns83815: PHY soft reset time out");
  643. if((csr32r(ctlr, Rbmcr) & Reset) == 0)
  644. break;
  645. delay(1);
  646. }
  647. }
  648. /*
  649. * Initialisation values, in sequence (see 4.4 Recommended Registers Configuration)
  650. */
  651. csr16w(ctlr, 0xCC, 0x0001); /* PGSEL */
  652. csr16w(ctlr, 0xE4, 0x189C); /* PMCCSR */
  653. csr16w(ctlr, 0xFC, 0x0000); /* TSTDAT */
  654. csr16w(ctlr, 0xF4, 0x5040); /* DSPCFG */
  655. csr16w(ctlr, 0xF8, 0x008C); /* SDCFG */
  656. /*
  657. * Auto negotiate
  658. */
  659. w = csr16r(ctlr, Rbmsr); /* clear latched bits */
  660. debug("anar: %4.4ux\n", csr16r(ctlr, Ranar));
  661. csr16w(ctlr, Rbmcr, Anena);
  662. if(csr16r(ctlr, Ranar) == 0 || (csr32r(ctlr, Rcfg) & Aneg_dn) == 0){
  663. csr16w(ctlr, Rbmcr, Anena|Anrestart);
  664. for(i=0;; i++){
  665. if(i > 6000){
  666. print("ns83815: auto neg timed out\n");
  667. break;
  668. }
  669. if((w = csr16r(ctlr, Rbmsr)) & Ancomp)
  670. break;
  671. delay(1);
  672. }
  673. debug("%d ms\n", i);
  674. w &= 0xFFFF;
  675. debug("bmsr: %4.4ux\n", w);
  676. }
  677. debug("anar: %4.4ux\n", csr16r(ctlr, Ranar));
  678. debug("anlpar: %4.4ux\n", csr16r(ctlr, Ranlpar));
  679. debug("aner: %4.4ux\n", csr16r(ctlr, Raner));
  680. debug("physts: %4.4ux\n", csr16r(ctlr, Rphysts));
  681. debug("tbscr: %4.4ux\n", csr16r(ctlr, Rtbscr));
  682. }
  683. static int
  684. media(Ether* ether)
  685. {
  686. Ctlr* ctlr;
  687. ulong cfg;
  688. ctlr = ether->ctlr;
  689. cfg = csr32r(ctlr, Rcfg);
  690. ctlr->fd = (cfg & Fdup) != 0;
  691. if(cfg & Speed100)
  692. return 100;
  693. if((cfg & Lnksts) == 0)
  694. return 100; /* no link: use 100 to ensure larger queues */
  695. return 10;
  696. }
  697. static char* mediatable[9] = {
  698. "10BASE-T", /* TP */
  699. "10BASE-2", /* BNC */
  700. "10BASE-5", /* AUI */
  701. "100BASE-TX",
  702. "10BASE-TFD",
  703. "100BASE-TXFD",
  704. "100BASE-T4",
  705. "100BASE-FX",
  706. "100BASE-FXFD",
  707. };
  708. static void
  709. srom(Ctlr* ctlr)
  710. {
  711. int i, j;
  712. for(i = 0; i < nelem(ctlr->srom); i++)
  713. ctlr->srom[i] = eegetw(ctlr, i);
  714. /*
  715. * the MAC address is reversed, straddling word boundaries
  716. */
  717. memset(ctlr->sromea, 0, sizeof(ctlr->sromea));
  718. j = 6*16 + 15;
  719. for(i=0; i<48; i++){
  720. ctlr->sromea[i>>3] |= ((ctlr->srom[j>>4] >> (15-(j&0xF))) & 1) << (i&7);
  721. j++;
  722. }
  723. }
  724. static void
  725. scanpci83815(void)
  726. {
  727. Ctlr *ctlr;
  728. Pcidev *p;
  729. p = nil;
  730. while(p = pcimatch(p, 0, 0)){
  731. if(p->ccrb != 0x02 || p->ccru != 0)
  732. continue;
  733. switch((p->did<<16)|p->vid){
  734. default:
  735. continue;
  736. case Nat83815:
  737. break;
  738. }
  739. /*
  740. * bar[0] is the I/O port register address and
  741. * bar[1] is the memory-mapped register address.
  742. */
  743. ctlr = malloc(sizeof(Ctlr));
  744. ctlr->port = p->mem[0].bar & ~0x01;
  745. ctlr->pcidev = p;
  746. ctlr->id = (p->did<<16)|p->vid;
  747. if(ioalloc(ctlr->port, p->mem[0].size, 0, "ns83815") < 0){
  748. print("ns83815: port 0x%uX in use\n", ctlr->port);
  749. free(ctlr);
  750. continue;
  751. }
  752. softreset(ctlr, 0);
  753. srom(ctlr);
  754. if(ctlrhead != nil)
  755. ctlrtail->next = ctlr;
  756. else
  757. ctlrhead = ctlr;
  758. ctlrtail = ctlr;
  759. }
  760. }
  761. /* multicast already on, don't need to do anything */
  762. static void
  763. multicast(void*, uchar*, int)
  764. {
  765. }
  766. static int
  767. reset(Ether* ether)
  768. {
  769. Ctlr *ctlr;
  770. int i, x;
  771. uchar ea[Eaddrlen];
  772. static int scandone;
  773. if(scandone == 0){
  774. scanpci83815();
  775. scandone = 1;
  776. }
  777. /*
  778. * Any adapter matches if no ether->port is supplied,
  779. * otherwise the ports must match.
  780. */
  781. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  782. if(ctlr->active)
  783. continue;
  784. if(ether->port == 0 || ether->port == ctlr->port){
  785. ctlr->active = 1;
  786. break;
  787. }
  788. }
  789. if(ctlr == nil)
  790. return -1;
  791. ether->ctlr = ctlr;
  792. ether->port = ctlr->port;
  793. ether->irq = ctlr->pcidev->intl;
  794. ether->tbdf = ctlr->pcidev->tbdf;
  795. /*
  796. * Check if the adapter's station address is to be overridden.
  797. * If not, read it from the EEPROM and set in ether->ea prior to
  798. * loading the station address in the hardware.
  799. */
  800. memset(ea, 0, Eaddrlen);
  801. if(memcmp(ea, ether->ea, Eaddrlen) == 0)
  802. memmove(ether->ea, ctlr->sromea, Eaddrlen);
  803. for(i=0; i<Eaddrlen; i+=2){
  804. x = ether->ea[i] | (ether->ea[i+1]<<8);
  805. csr32w(ctlr, Rrfcr, i);
  806. csr32w(ctlr, Rrfdr, x);
  807. }
  808. csr32w(ctlr, Rrfcr, Rfen|Apm|Aab|Aam);
  809. ether->mbps = media(ether);
  810. /*
  811. * Look for a medium override in case there's no autonegotiation
  812. * the autonegotiation fails.
  813. */
  814. for(i = 0; i < ether->nopt; i++){
  815. if(cistrcmp(ether->opt[i], "FD") == 0){
  816. ctlr->fd = 1;
  817. continue;
  818. }
  819. for(x = 0; x < nelem(mediatable); x++){
  820. debug("compare <%s> <%s>\n", mediatable[x],
  821. ether->opt[i]);
  822. if(cistrcmp(mediatable[x], ether->opt[i]) == 0){
  823. if(x != 4 && x >= 3)
  824. ether->mbps = 100;
  825. else
  826. ether->mbps = 10;
  827. switch(x){
  828. default:
  829. ctlr->fd = 0;
  830. break;
  831. case 0x04: /* 10BASE-TFD */
  832. case 0x05: /* 100BASE-TXFD */
  833. case 0x08: /* 100BASE-FXFD */
  834. ctlr->fd = 1;
  835. break;
  836. }
  837. break;
  838. }
  839. }
  840. }
  841. /*
  842. * Initialise descriptor rings, ethernet address.
  843. */
  844. ctlr->nrdr = Nrde;
  845. ctlr->ntdr = Ntde;
  846. pcisetbme(ctlr->pcidev);
  847. ctlrinit(ether);
  848. /*
  849. * Linkage to the generic ethernet driver.
  850. */
  851. ether->attach = attach;
  852. ether->transmit = transmit;
  853. ether->interrupt = interrupt;
  854. ether->ifstat = ifstat;
  855. ether->multicast = multicast;
  856. ether->arg = ether;
  857. ether->promiscuous = promiscuous;
  858. return 0;
  859. }
  860. void
  861. ether83815link(void)
  862. {
  863. addethercard("83815", reset);
  864. }