devpccard.c 38 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916
  1. /*
  2. cardbus and pcmcia (grmph) support.
  3. */
  4. #include "u.h"
  5. #include "../port/lib.h"
  6. #include "mem.h"
  7. #include "dat.h"
  8. #include "fns.h"
  9. #include "../port/error.h"
  10. #include "io.h"
  11. #define DEBUG 0
  12. #pragma varargck type "T" int
  13. #define MAP(x,o) (Rmap + (x)*0x8 + o)
  14. enum {
  15. TI_vid = 0x104c,
  16. TI_1131_did = 0xAC15,
  17. TI_1250_did = 0xAC16,
  18. TI_1450_did = 0xAC1B,
  19. TI_1251A_did = 0xAC1D,
  20. TI_1420_did = 0xAC51,
  21. Ricoh_vid = 0x1180,
  22. Ricoh_475_did = 0x0475,
  23. Ricoh_476_did = 0x0476,
  24. Ricoh_478_did = 0x0478,
  25. O2_vid = 0x1217,
  26. O2_OZ711M3_did = 0x7134,
  27. Nslots = 4, /* Maximum number of CardBus slots to use */
  28. K = 1024,
  29. M = K * K,
  30. LegacyAddr = 0x3e0,
  31. NUMEVENTS = 10,
  32. TI1131xSC = 0x80, // system control
  33. TI122X_SC_INTRTIE = 1 << 29,
  34. TI12xxIM = 0x8c, //
  35. TI1131xCC = 0x91, // card control
  36. TI113X_CC_RIENB = 1 << 7,
  37. TI113X_CC_ZVENABLE = 1 << 6,
  38. TI113X_CC_PCI_IRQ_ENA = 1 << 5,
  39. TI113X_CC_PCI_IREQ = 1 << 4,
  40. TI113X_CC_PCI_CSC = 1 << 3,
  41. TI113X_CC_SPKROUTEN = 1 << 1,
  42. TI113X_CC_IFG = 1 << 0,
  43. TI1131xDC = 0x92, // device control
  44. };
  45. typedef struct Variant Variant;
  46. struct Variant {
  47. ushort vid;
  48. ushort did;
  49. char *name;
  50. };
  51. static Variant variant[] = {
  52. { Ricoh_vid, Ricoh_475_did, "Ricoh 475 PCI/Cardbus bridge", },
  53. { Ricoh_vid, Ricoh_476_did, "Ricoh 476 PCI/Cardbus bridge", },
  54. { Ricoh_vid, Ricoh_478_did, "Ricoh 478 PCI/Cardbus bridge", },
  55. { TI_vid, TI_1131_did, "TI PCI-1131 Cardbus Controller", },
  56. { TI_vid, TI_1250_did, "TI PCI-1250 Cardbus Controller", },
  57. { TI_vid, TI_1450_did, "TI PCI-1450 Cardbus Controller", },
  58. { TI_vid, TI_1251A_did, "TI PCI-1251A Cardbus Controller", },
  59. { TI_vid, TI_1420_did, "TI PCI-1420 Cardbus Controller", },
  60. { O2_vid, O2_OZ711M3_did, "O2Micro OZ711M3 MemoryCardBus", },
  61. };
  62. /* Cardbus registers */
  63. enum {
  64. SocketEvent = 0,
  65. SE_CCD = 3 << 1,
  66. SE_POWER = 1 << 3,
  67. SocketMask = 1,
  68. SocketState = 2,
  69. SS_CCD = 3 << 1,
  70. SS_POWER = 1 << 3,
  71. SS_PC16 = 1 << 4,
  72. SS_CBC = 1 << 5,
  73. SS_NOTCARD = 1 << 7,
  74. SS_BADVCC = 1 << 9,
  75. SS_5V = 1 << 10,
  76. SS_3V = 1 << 11,
  77. SocketForce = 3,
  78. SocketControl = 4,
  79. SC_5V = 0x22,
  80. SC_3V = 0x33,
  81. };
  82. enum {
  83. PciPCR_IO = 1 << 0,
  84. PciPCR_MEM = 1 << 1,
  85. PciPCR_Master = 1 << 2,
  86. PciPMC = 0xa4,
  87. Nbars = 6,
  88. Ncmd = 10,
  89. CBIRQ = 9,
  90. PC16,
  91. PC32,
  92. };
  93. enum {
  94. Ti82365,
  95. Tpd6710,
  96. Tpd6720,
  97. Tvg46x,
  98. };
  99. /*
  100. * Intel 82365SL PCIC controller for the PCMCIA or
  101. * Cirrus Logic PD6710/PD6720 which is mostly register compatible
  102. */
  103. enum
  104. {
  105. /*
  106. * registers indices
  107. */
  108. Rid= 0x0, /* identification and revision */
  109. Ris= 0x1, /* interface status */
  110. Rpc= 0x2, /* power control */
  111. Foutena= (1<<7), /* output enable */
  112. Fautopower= (1<<5), /* automatic power switching */
  113. Fcardena= (1<<4), /* PC card enable */
  114. Rigc= 0x3, /* interrupt and general control */
  115. Fiocard= (1<<5), /* I/O card (vs memory) */
  116. Fnotreset= (1<<6), /* reset if not set */
  117. FSMIena= (1<<4), /* enable change interrupt on SMI */
  118. Rcsc= 0x4, /* card status change */
  119. Rcscic= 0x5, /* card status change interrupt config */
  120. Fchangeena= (1<<3), /* card changed */
  121. Fbwarnena= (1<<1), /* card battery warning */
  122. Fbdeadena= (1<<0), /* card battery dead */
  123. Rwe= 0x6, /* address window enable */
  124. Fmem16= (1<<5), /* use A23-A12 to decode address */
  125. Rio= 0x7, /* I/O control */
  126. Fwidth16= (1<<0), /* 16 bit data width */
  127. Fiocs16= (1<<1), /* IOCS16 determines data width */
  128. Fzerows= (1<<2), /* zero wait state */
  129. Ftiming= (1<<3), /* timing register to use */
  130. Riobtm0lo= 0x8, /* I/O address 0 start low byte */
  131. Riobtm0hi= 0x9, /* I/O address 0 start high byte */
  132. Riotop0lo= 0xa, /* I/O address 0 stop low byte */
  133. Riotop0hi= 0xb, /* I/O address 0 stop high byte */
  134. Riobtm1lo= 0xc, /* I/O address 1 start low byte */
  135. Riobtm1hi= 0xd, /* I/O address 1 start high byte */
  136. Riotop1lo= 0xe, /* I/O address 1 stop low byte */
  137. Riotop1hi= 0xf, /* I/O address 1 stop high byte */
  138. Rmap= 0x10, /* map 0 */
  139. /*
  140. * CL-PD67xx extension registers
  141. */
  142. Rmisc1= 0x16, /* misc control 1 */
  143. F5Vdetect= (1<<0),
  144. Fvcc3V= (1<<1),
  145. Fpmint= (1<<2),
  146. Fpsirq= (1<<3),
  147. Fspeaker= (1<<4),
  148. Finpack= (1<<7),
  149. Rfifo= 0x17, /* fifo control */
  150. Fflush= (1<<7), /* flush fifo */
  151. Rmisc2= 0x1E, /* misc control 2 */
  152. Flowpow= (1<<1), /* low power mode */
  153. Rchipinfo= 0x1F, /* chip information */
  154. Ratactl= 0x26, /* ATA control */
  155. /*
  156. * offsets into the system memory address maps
  157. */
  158. Mbtmlo= 0x0, /* System mem addr mapping start low byte */
  159. Mbtmhi= 0x1, /* System mem addr mapping start high byte */
  160. F16bit= (1<<7), /* 16-bit wide data path */
  161. Mtoplo= 0x2, /* System mem addr mapping stop low byte */
  162. Mtophi= 0x3, /* System mem addr mapping stop high byte */
  163. Ftimer1= (1<<6), /* timer set 1 */
  164. Mofflo= 0x4, /* Card memory offset address low byte */
  165. Moffhi= 0x5, /* Card memory offset address high byte */
  166. Fregactive= (1<<6), /* attribute memory */
  167. /*
  168. * configuration registers - they start at an offset in attribute
  169. * memory found in the CIS.
  170. */
  171. Rconfig= 0,
  172. Creset= (1<<7), /* reset device */
  173. Clevel= (1<<6), /* level sensitive interrupt line */
  174. };
  175. /*
  176. * read and crack the card information structure enough to set
  177. * important parameters like power
  178. */
  179. /* cis memory walking */
  180. typedef struct Cisdat Cisdat;
  181. struct Cisdat {
  182. uchar *cisbase;
  183. int cispos;
  184. int cisskip;
  185. int cislen;
  186. };
  187. typedef struct Pcminfo Pcminfo;
  188. struct Pcminfo {
  189. char verstr[512]; /* Version string */
  190. PCMmap mmap[4]; /* maps, last is always for the kernel */
  191. ulong conf_addr; /* Config address */
  192. uchar conf_present; /* Config register present */
  193. int nctab; /* In use configuration tables */
  194. PCMconftab ctab[8]; /* Configuration tables */
  195. PCMconftab *defctab; /* Default conftab */
  196. int port; /* Actual port usage */
  197. int irq; /* Actual IRQ usage */
  198. };
  199. typedef struct Cardbus Cardbus;
  200. struct Cardbus {
  201. Lock;
  202. Variant *variant; /* Which CardBus chipset */
  203. Pcidev *pci; /* The bridge itself */
  204. ulong *regs; /* Cardbus registers */
  205. int ltype; /* Legacy type */
  206. int lindex; /* Legacy port index address */
  207. int ldata; /* Legacy port data address */
  208. int lbase; /* Base register for this socket */
  209. int state; /* Current state of card */
  210. int type; /* Type of card */
  211. Pcminfo linfo; /* PCMCIA slot info */
  212. int special; /* card is allocated to a driver */
  213. int refs; /* Number of refs to slot */
  214. Lock refslock; /* inc/dev ref lock */
  215. };
  216. static int managerstarted;
  217. enum {
  218. Mshift= 12,
  219. Mgran= (1<<Mshift), /* granularity of maps */
  220. Mmask= ~(Mgran-1), /* mask for address bits important to the chip */
  221. };
  222. static Cardbus cbslots[Nslots];
  223. static int nslots;
  224. static ulong exponent[8] = {
  225. 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
  226. };
  227. static ulong vmant[16] = {
  228. 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90,
  229. };
  230. static ulong mantissa[16] = {
  231. 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80,
  232. };
  233. static char Enocard[] = "No card in slot";
  234. enum
  235. {
  236. CMdown,
  237. CMpower,
  238. };
  239. static Cmdtab pccardctlmsg[] =
  240. {
  241. CMdown, "down", 2,
  242. CMpower, "power", 1,
  243. };
  244. static int powerup(Cardbus *);
  245. static void configure(Cardbus *);
  246. static void powerdown(Cardbus *cb);
  247. static void unconfigure(Cardbus *cb);
  248. static void i82365probe(Cardbus *cb, int lindex, int ldata);
  249. static void i82365configure(Cardbus *cb);
  250. static PCMmap *isamap(Cardbus *cb, ulong offset, int len, int attr);
  251. static void isaunmap(PCMmap* m);
  252. static uchar rdreg(Cardbus *cb, int index);
  253. static void wrreg(Cardbus *cb, int index, uchar val);
  254. static int readc(Cisdat *cis, uchar *x);
  255. static void tvers1(Cardbus *cb, Cisdat *cis, int );
  256. static void tcfig(Cardbus *cb, Cisdat *cis, int );
  257. static void tentry(Cardbus *cb, Cisdat *cis, int );
  258. static int vcode(int volt);
  259. static int pccard_pcmspecial(char *idstr, ISAConf *isa);
  260. static void pccard_pcmspecialclose(int slotno);
  261. enum {
  262. CardDetected,
  263. CardPowered,
  264. CardEjected,
  265. CardConfigured,
  266. };
  267. static char *messages[] = {
  268. [CardDetected] "CardDetected",
  269. [CardPowered] "CardPowered",
  270. [CardEjected] "CardEjected",
  271. [CardConfigured] "CardConfigured",
  272. };
  273. enum {
  274. SlotEmpty,
  275. SlotFull,
  276. SlotPowered,
  277. SlotConfigured,
  278. };
  279. static char *states[] = {
  280. [SlotEmpty] "SlotEmpty",
  281. [SlotFull] "SlotFull",
  282. [SlotPowered] "SlotPowered",
  283. [SlotConfigured] "SlotConfigured",
  284. };
  285. static void
  286. engine(Cardbus *cb, int message)
  287. {
  288. if(DEBUG)
  289. print("engine(%ld): %s(%s)\n", cb - cbslots,
  290. states[cb->state], messages[message]);
  291. switch (cb->state) {
  292. case SlotEmpty:
  293. switch (message) {
  294. case CardDetected:
  295. cb->state = SlotFull;
  296. powerup(cb);
  297. break;
  298. case CardEjected:
  299. break;
  300. default:
  301. if(DEBUG)
  302. print("#Y%ld: Invalid message %s in SlotEmpty state\n",
  303. cb - cbslots, messages[message]);
  304. break;
  305. }
  306. break;
  307. case SlotFull:
  308. switch (message) {
  309. case CardPowered:
  310. cb->state = SlotPowered;
  311. configure(cb);
  312. break;
  313. case CardEjected:
  314. cb->state = SlotEmpty;
  315. powerdown(cb);
  316. break;
  317. default:
  318. if(DEBUG)
  319. print("#Y%ld: Invalid message %s in SlotFull state\n",
  320. cb - cbslots, messages[message]);
  321. break;
  322. }
  323. break;
  324. case SlotPowered:
  325. switch (message) {
  326. case CardConfigured:
  327. cb->state = SlotConfigured;
  328. break;
  329. case CardEjected:
  330. cb->state = SlotEmpty;
  331. unconfigure(cb);
  332. powerdown(cb);
  333. break;
  334. default:
  335. print("#Y%ld: Invalid message %s in SlotPowered state\n",
  336. cb - cbslots, messages[message]);
  337. break;
  338. }
  339. break;
  340. case SlotConfigured:
  341. switch (message) {
  342. case CardEjected:
  343. cb->state = SlotEmpty;
  344. unconfigure(cb);
  345. powerdown(cb);
  346. break;
  347. default:
  348. if(DEBUG)
  349. print("#Y%ld: Invalid message %s in SlotConfigured state\n",
  350. cb - cbslots, messages[message]);
  351. break;
  352. }
  353. break;
  354. }
  355. }
  356. static void
  357. qengine(Cardbus *cb, int message)
  358. {
  359. lock(cb);
  360. engine(cb, message);
  361. unlock(cb);
  362. }
  363. typedef struct Events Events;
  364. struct Events {
  365. Cardbus *cb;
  366. int message;
  367. };
  368. static Lock levents;
  369. static Events events[NUMEVENTS];
  370. static Rendez revents;
  371. static int nevents;
  372. static void
  373. iengine(Cardbus *cb, int message)
  374. {
  375. if (nevents >= NUMEVENTS) {
  376. print("#Y: Too many events queued, discarding request\n");
  377. return;
  378. }
  379. ilock(&levents);
  380. events[nevents].cb = cb;
  381. events[nevents].message = message;
  382. nevents++;
  383. iunlock(&levents);
  384. wakeup(&revents);
  385. }
  386. static int
  387. eventoccured(void)
  388. {
  389. return nevents > 0;
  390. }
  391. static void
  392. processevents(void *)
  393. {
  394. while (1) {
  395. int message;
  396. Cardbus *cb;
  397. sleep(&revents, (int (*)(void *))eventoccured, nil);
  398. cb = nil;
  399. message = 0;
  400. ilock(&levents);
  401. if (nevents > 0) {
  402. cb = events[0].cb;
  403. message = events[0].message;
  404. nevents--;
  405. if (nevents > 0)
  406. memmove(events, &events[1], nevents * sizeof(Events));
  407. }
  408. iunlock(&levents);
  409. if (cb)
  410. qengine(cb, message);
  411. }
  412. }
  413. static void
  414. cbinterrupt(Ureg *, void *)
  415. {
  416. int i;
  417. for (i = 0; i != nslots; i++) {
  418. Cardbus *cb = &cbslots[i];
  419. ulong event, state;
  420. event = cb->regs[SocketEvent];
  421. if(!(event & (SE_POWER|SE_CCD)))
  422. continue;
  423. state = cb->regs[SocketState];
  424. rdreg(cb, Rcsc); /* Ack the interrupt */
  425. if(DEBUG)
  426. print("#Y%ld: interrupt: event %.8lX, state %.8lX, (%s)\n",
  427. cb - cbslots, event, state, states[cb->state]);
  428. if (event & SE_CCD) {
  429. cb->regs[SocketEvent] |= SE_CCD; /* Ack interrupt */
  430. if (state & SE_CCD) {
  431. if (cb->state != SlotEmpty) {
  432. print("#Y: take cardejected interrupt\n");
  433. iengine(cb, CardEjected);
  434. }
  435. }
  436. else
  437. iengine(cb, CardDetected);
  438. }
  439. if (event & SE_POWER) {
  440. cb->regs[SocketEvent] |= SE_POWER; /* Ack interrupt */
  441. iengine(cb, CardPowered);
  442. }
  443. }
  444. }
  445. void
  446. devpccardlink(void)
  447. {
  448. static int initialized;
  449. Pcidev *pci;
  450. int i;
  451. uchar intl;
  452. char *p;
  453. void *baddrva;
  454. if (initialized)
  455. return;
  456. initialized = 1;
  457. if((p=getconf("pccard0")) && strncmp(p, "disabled", 8)==0)
  458. return;
  459. if(_pcmspecial)
  460. return;
  461. /* Allocate legacy space */
  462. if (ioalloc(LegacyAddr, 2, 0, "i82365.0") < 0)
  463. print("#Y: WARNING: Cannot allocate legacy ports\n");
  464. /* Find all CardBus controllers */
  465. pci = nil;
  466. intl = 0xff;
  467. while ((pci = pcimatch(pci, 0, 0)) != nil) {
  468. ulong baddr;
  469. Cardbus *cb;
  470. int slot;
  471. uchar pin;
  472. if(pci->ccrb != 6 || pci->ccru != 7)
  473. continue;
  474. for (i = 0; i != nelem(variant); i++)
  475. if (pci->vid == variant[i].vid && pci->did == variant[i].did)
  476. break;
  477. if (i == nelem(variant))
  478. continue;
  479. /* initialize this slot */
  480. slot = nslots++;
  481. cb = &cbslots[slot];
  482. cb->pci = pci;
  483. cb->variant = &variant[i];
  484. if (pci->vid != TI_vid) {
  485. // Gross hack, needs a fix. Inherit the mappings from 9load
  486. // for the TIs (pb)
  487. pcicfgw32(pci, PciCBMBR0, 0xffffffff);
  488. pcicfgw32(pci, PciCBMLR0, 0);
  489. pcicfgw32(pci, PciCBMBR1, 0xffffffff);
  490. pcicfgw32(pci, PciCBMLR1, 0);
  491. pcicfgw32(pci, PciCBIBR0, 0xffffffff);
  492. pcicfgw32(pci, PciCBILR0, 0);
  493. pcicfgw32(pci, PciCBIBR1, 0xffffffff);
  494. pcicfgw32(pci, PciCBILR1, 0);
  495. }
  496. // Set up PCI bus numbers if needed.
  497. if (pcicfgr8(pci, PciSBN) == 0) {
  498. static int busbase = 0x20;
  499. pcicfgw8(pci, PciSBN, busbase);
  500. pcicfgw8(pci, PciUBN, busbase + 2);
  501. busbase += 3;
  502. }
  503. // Patch up intl if needed.
  504. if ((pin = pcicfgr8(pci, PciINTP)) != 0 &&
  505. (pci->intl == 0xff || pci->intl == 0)) {
  506. pci->intl = pciipin(nil, pin);
  507. pcicfgw8(pci, PciINTL, pci->intl);
  508. if (pci->intl == 0xff || pci->intl == 0)
  509. print("#Y%ld: No interrupt?\n", cb - cbslots);
  510. }
  511. // Don't you love standards!
  512. if (pci->vid == TI_vid) {
  513. if (pci->did <= TI_1131_did) {
  514. uchar cc;
  515. cc = pcicfgr8(pci, TI1131xCC);
  516. cc &= ~(TI113X_CC_PCI_IRQ_ENA |
  517. TI113X_CC_PCI_IREQ |
  518. TI113X_CC_PCI_CSC |
  519. TI113X_CC_ZVENABLE);
  520. cc |= TI113X_CC_PCI_IRQ_ENA |
  521. TI113X_CC_PCI_IREQ |
  522. TI113X_CC_SPKROUTEN;
  523. pcicfgw8(pci, TI1131xCC, cc);
  524. // PCI interrupts only
  525. pcicfgw8(pci, TI1131xDC,
  526. pcicfgr8(pci, TI1131xDC) & ~6);
  527. // CSC ints to PCI bus.
  528. wrreg(cb, Rigc, rdreg(cb, Rigc) | 0x10);
  529. }
  530. else if (pci->did == TI_1250_did) {
  531. print("No support yet for the TI_1250_did, prod pb\n");
  532. }
  533. else if (pci->did == TI_1420_did) {
  534. // Disable Vcc protection
  535. pcicfgw32(cb->pci, 0x80,
  536. pcicfgr32(cb->pci, 0x80) | (1 << 21));
  537. }
  538. pcicfgw16(cb->pci, PciPMC, pcicfgr16(cb->pci, PciPMC) & ~3);
  539. }
  540. if (pci->vid == O2_vid) {
  541. if(DEBUG)
  542. print("writing O2 config\n");
  543. pcicfgw8(cb->pci, 0x94, 0xCA);
  544. pcicfgw8(cb->pci, 0xD4, 0xCA);
  545. }
  546. if (intl != 0xff && intl != pci->intl)
  547. intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
  548. intl = pci->intl;
  549. if ((baddr = pcicfgr32(cb->pci, PciBAR0)) == 0) {
  550. int size = (pci->did == Ricoh_478_did)? 0x10000: 0x1000;
  551. baddr = upaalloc(size, size);
  552. baddrva = vmap(baddr, size);
  553. pcicfgw32(cb->pci, PciBAR0, baddr);
  554. cb->regs = (ulong *)baddrva;
  555. }
  556. else
  557. cb->regs = (ulong *)vmap(baddr, 4096);
  558. cb->state = SlotEmpty;
  559. /* Don't really know what to do with this... */
  560. i82365probe(cb, LegacyAddr, LegacyAddr + 1);
  561. print("#Y%ld: %s, %.8ulX intl %d\n", cb - cbslots,
  562. variant[i].name, baddr, pci->intl);
  563. }
  564. if (nslots == 0){
  565. iofree(LegacyAddr);
  566. return;
  567. }
  568. _pcmspecial = pccard_pcmspecial;
  569. _pcmspecialclose = pccard_pcmspecialclose;
  570. for (i = 0; i != nslots; i++) {
  571. Cardbus *cb = &cbslots[i];
  572. if ((cb->regs[SocketState] & SE_CCD) == 0)
  573. engine(cb, CardDetected);
  574. }
  575. delay(500); /* Allow time for power up */
  576. for (i = 0; i != nslots; i++) {
  577. Cardbus *cb = &cbslots[i];
  578. if (cb->regs[SocketState] & SE_POWER)
  579. engine(cb, CardPowered);
  580. /* Ack and enable interrupts on all events */
  581. //cb->regs[SocketEvent] = cb->regs[SocketEvent];
  582. cb->regs[SocketMask] |= 0xF;
  583. wrreg(cb, Rcscic, 0xC);
  584. }
  585. }
  586. static int
  587. powerup(Cardbus *cb)
  588. {
  589. ulong state;
  590. ushort bcr;
  591. state = cb->regs[SocketState];
  592. if (state & SS_PC16) {
  593. if(DEBUG)
  594. print("#Y%ld: Probed a PC16 card, powering up card\n",
  595. cb - cbslots);
  596. cb->type = PC16;
  597. memset(&cb->linfo, 0, sizeof(Pcminfo));
  598. /* power up and unreset, wait's are empirical (???) */
  599. wrreg(cb, Rpc, Fautopower|Foutena|Fcardena);
  600. delay(300);
  601. wrreg(cb, Rigc, 0);
  602. delay(100);
  603. wrreg(cb, Rigc, Fnotreset);
  604. delay(500);
  605. // return 1;
  606. }
  607. if (state & SS_CCD)
  608. return 0;
  609. if (state & SS_NOTCARD) {
  610. print("#Y%ld: No card inserted\n", cb - cbslots);
  611. return 0;
  612. }
  613. if ((state & SS_3V) == 0 && (state & SS_5V) == 0) {
  614. print("#Y%ld: Unsupported voltage, powering down card!\n",
  615. cb - cbslots);
  616. cb->regs[SocketControl] = 0;
  617. return 0;
  618. }
  619. if(DEBUG)
  620. print("#Y%ld: card %spowered at %d volt\n", cb - cbslots,
  621. (state & SS_POWER)? "": "not ",
  622. (state & SS_3V)? 3: (state & SS_5V)? 5: -1);
  623. /* Power up the card
  624. * and make sure the secondary bus is not in reset.
  625. */
  626. cb->regs[SocketControl] = (state & SS_5V)? SC_5V: SC_3V;
  627. delay(50);
  628. bcr = pcicfgr16(cb->pci, PciBCR);
  629. bcr &= ~0x40;
  630. pcicfgw16(cb->pci, PciBCR, bcr);
  631. delay(100);
  632. if (state & SS_PC16)
  633. cb->type = PC16;
  634. else
  635. cb->type = PC32;
  636. return 1;
  637. }
  638. static void
  639. powerdown(Cardbus *cb)
  640. {
  641. ushort bcr;
  642. if (cb->type == PC16) {
  643. wrreg(cb, Rpc, 0); /* turn off card power */
  644. wrreg(cb, Rwe, 0); /* no windows */
  645. cb->type = -1;
  646. return;
  647. }
  648. bcr = pcicfgr16(cb->pci, PciBCR);
  649. bcr |= 0x40;
  650. pcicfgw16(cb->pci, PciBCR, bcr);
  651. cb->regs[SocketControl] = 0;
  652. cb->type = -1;
  653. }
  654. static void
  655. configure(Cardbus *cb)
  656. {
  657. int i, r;
  658. ulong size, bar;
  659. Pcidev *pci;
  660. ulong membase, iobase, memlen, iolen, rombase, romlen;
  661. if(DEBUG)
  662. print("configuring slot %ld (%s)\n", cb - cbslots, states[cb->state]);
  663. if (cb->state == SlotConfigured)
  664. return;
  665. engine(cb, CardConfigured);
  666. delay(50); /* Emperically established */
  667. if (cb->type == PC16) {
  668. i82365configure(cb);
  669. return;
  670. }
  671. /* Scan the CardBus for new PCI devices */
  672. pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
  673. /*
  674. * size the devices on the bus, reserve a minimum for devices arriving later,
  675. * allow for ROM space, allocate space, and set the cardbus mapping registers
  676. */
  677. pcibussize(cb->pci->bridge, &memlen, &iolen); /* TO DO: need initial alignments */
  678. romlen = 0;
  679. for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
  680. size = pcibarsize(pci, PciEBAR0);
  681. if(size > 0){
  682. pci->rom.bar = -1;
  683. pci->rom.size = size;
  684. romlen += size;
  685. }
  686. }
  687. if(iolen < 512)
  688. iolen = 512;
  689. iobase = ioreserve(~0, iolen, 0, "cardbus");
  690. pcicfgw32(cb->pci, PciCBIBR0, iobase);
  691. pcicfgw32(cb->pci, PciCBILR0, iobase + iolen-1);
  692. pcicfgw32(cb->pci, PciCBIBR1, 0);
  693. pcicfgw32(cb->pci, PciCBILR1, 0);
  694. rombase = memlen;
  695. memlen += romlen;
  696. if(memlen < 1*1024*1024)
  697. memlen = 1*1024*1024;
  698. membase = upaalloc(memlen, 4*1024*1024); /* TO DO: better alignment */
  699. pcicfgw32(cb->pci, PciCBMBR0, membase);
  700. pcicfgw32(cb->pci, PciCBMLR0, membase + memlen-1);
  701. pcicfgw32(cb->pci, PciCBMBR1, 0);
  702. pcicfgw32(cb->pci, PciCBMLR1, 0);
  703. // pcibussize(cb->pci->bridge, &membase, &iobase); /* now assign them */
  704. rombase += membase;
  705. for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
  706. r = pcicfgr16(pci, PciPCR);
  707. r &= ~(PciPCR_IO|PciPCR_MEM);
  708. pcicfgw16(pci, PciPCR, r);
  709. /*
  710. * Treat the found device as an ordinary PCI card.
  711. * It seems that the CIS is not always present in
  712. * CardBus cards.
  713. * XXX, need to support multifunction cards
  714. */
  715. for(i = 0; i < Nbars; i++) {
  716. if(pci->mem[i].size == 0)
  717. continue;
  718. bar = pci->mem[i].bar;
  719. if(bar & 1)
  720. bar += iobase;
  721. else
  722. bar += membase;
  723. pci->mem[i].bar = bar;
  724. pcicfgw32(pci, PciBAR0 + 4*i, bar);
  725. if((bar & 1) == 0){
  726. print("%T mem[%d] %8.8lux %d\n", pci->tbdf, i, bar, pci->mem[i].size);
  727. if(bar & 0x80){ /* TO DO: enable prefetch */
  728. ;
  729. }
  730. }
  731. }
  732. if((size = pcibarsize(pci, PciEBAR0)) > 0) { /* TO DO: can this be done by pci.c? */
  733. pci->rom.bar = rombase;
  734. pci->rom.size = size;
  735. rombase += size;
  736. pcicfgw32(pci, PciEBAR0, pci->rom.bar);
  737. }
  738. /* Set the basic PCI registers for the device */
  739. pci->pcr = pcicfgr16(pci, PciPCR);
  740. pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
  741. pci->cls = 8;
  742. pci->ltr = 64;
  743. pcicfgw16(pci, PciPCR, pci->pcr);
  744. pcicfgw8(pci, PciCLS, pci->cls);
  745. pcicfgw8(pci, PciLTR, pci->ltr);
  746. if (pcicfgr8(pci, PciINTP)) {
  747. pci->intl = pcicfgr8(cb->pci, PciINTL);
  748. pcicfgw8(pci, PciINTL, pci->intl);
  749. /* Route interrupts to INTA#/B# */
  750. pcicfgw16(cb->pci, PciBCR,
  751. pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
  752. }
  753. }
  754. }
  755. static void
  756. unconfigure(Cardbus *cb)
  757. {
  758. Pcidev *pci;
  759. int i, ioindex, memindex, r;
  760. if (cb->type == PC16) {
  761. print("#Y%d: Don't know how to unconfigure a PC16 card\n",
  762. (int)(cb - cbslots));
  763. memset(&cb->linfo, 0, sizeof(Pcminfo));
  764. return;
  765. }
  766. pci = cb->pci->bridge;
  767. if (pci == nil)
  768. return; /* Not configured */
  769. cb->pci->bridge = nil;
  770. memindex = ioindex = 0;
  771. while (pci) {
  772. Pcidev *_pci;
  773. for (i = 0; i != Nbars; i++) {
  774. if (pci->mem[i].size == 0)
  775. continue;
  776. if (pci->mem[i].bar & 1) {
  777. iofree(pci->mem[i].bar & ~1);
  778. pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8,
  779. (ushort)-1);
  780. pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8, 0);
  781. ioindex++;
  782. continue;
  783. }
  784. upafree(pci->mem[i].bar & ~0xF, pci->mem[i].size);
  785. pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
  786. pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
  787. r = pcicfgr16(cb->pci, PciBCR);
  788. r &= ~(1 << (8 + memindex));
  789. pcicfgw16(cb->pci, PciBCR, r);
  790. memindex++;
  791. }
  792. if (pci->rom.bar && memindex < 2) {
  793. upafree(pci->rom.bar & ~0xF, pci->rom.size);
  794. pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
  795. pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
  796. memindex++;
  797. }
  798. _pci = pci->list;
  799. free(_pci);
  800. pci = _pci;
  801. }
  802. }
  803. static void
  804. i82365configure(Cardbus *cb)
  805. {
  806. int this;
  807. Cisdat cis;
  808. PCMmap *m;
  809. uchar type, link;
  810. /*
  811. * Read all tuples in attribute space.
  812. */
  813. m = isamap(cb, 0, 0, 1);
  814. if(m == 0)
  815. return;
  816. cis.cisbase = KADDR(m->isa);
  817. cis.cispos = 0;
  818. cis.cisskip = 2;
  819. cis.cislen = m->len;
  820. /* loop through all the tuples */
  821. for(;;){
  822. this = cis.cispos;
  823. if(readc(&cis, &type) != 1)
  824. break;
  825. if(type == 0xFF)
  826. break;
  827. if(readc(&cis, &link) != 1)
  828. break;
  829. switch(type){
  830. default:
  831. break;
  832. case 0x15:
  833. tvers1(cb, &cis, type);
  834. break;
  835. case 0x1A:
  836. tcfig(cb, &cis, type);
  837. break;
  838. case 0x1B:
  839. tentry(cb, &cis, type);
  840. break;
  841. }
  842. if(link == 0xFF)
  843. break;
  844. cis.cispos = this + (2+link);
  845. }
  846. isaunmap(m);
  847. }
  848. /*
  849. * look for a card whose version contains 'idstr'
  850. */
  851. static int
  852. pccard_pcmspecial(char *idstr, ISAConf *isa)
  853. {
  854. int i, irq;
  855. PCMconftab *ct, *et;
  856. Pcminfo *pi;
  857. Cardbus *cb;
  858. uchar x, we, *p;
  859. cb = nil;
  860. for (i = 0; i != nslots; i++) {
  861. cb = &cbslots[i];
  862. lock(cb);
  863. if (cb->state == SlotConfigured &&
  864. cb->type == PC16 &&
  865. !cb->special &&
  866. strstr(cb->linfo.verstr, idstr))
  867. break;
  868. unlock(cb);
  869. }
  870. if (i == nslots) {
  871. //if(DEBUG)
  872. // print("#Y: %s not found\n", idstr);
  873. return -1;
  874. }
  875. pi = &cb->linfo;
  876. /*
  877. * configure the PCMslot for IO. We assume very heavily that we can read
  878. * configuration info from the CIS. If not, we won't set up correctly.
  879. */
  880. irq = isa->irq;
  881. if(irq == 2)
  882. irq = 9;
  883. et = &pi->ctab[pi->nctab];
  884. ct = nil;
  885. for(i = 0; i < isa->nopt; i++){
  886. int index;
  887. char *cp;
  888. if(strncmp(isa->opt[i], "index=", 6))
  889. continue;
  890. index = strtol(&isa->opt[i][6], &cp, 0);
  891. if(cp == &isa->opt[i][6] || index >= pi->nctab) {
  892. unlock(cb);
  893. print("#Y%d: Cannot find index %d in conf table\n",
  894. (int)(cb - cbslots), index);
  895. return -1;
  896. }
  897. ct = &pi->ctab[index];
  898. }
  899. if(ct == nil){
  900. PCMconftab *t;
  901. /* assume default is right */
  902. if(pi->defctab)
  903. ct = pi->defctab;
  904. else
  905. ct = pi->ctab;
  906. /* try for best match */
  907. if(ct->nio == 0
  908. || ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){
  909. for(t = pi->ctab; t < et; t++)
  910. if(t->nio
  911. && t->io[0].start == isa->port
  912. && ((1<<irq) & t->irqs)){
  913. ct = t;
  914. break;
  915. }
  916. }
  917. if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){
  918. for(t = pi->ctab; t < et; t++)
  919. if(t->nio && ((1<<irq) & t->irqs)){
  920. ct = t;
  921. break;
  922. }
  923. }
  924. if(ct->nio == 0){
  925. for(t = pi->ctab; t < et; t++)
  926. if(t->nio){
  927. ct = t;
  928. break;
  929. }
  930. }
  931. }
  932. if(ct == et || ct->nio == 0) {
  933. unlock(cb);
  934. print("#Y%d: No configuration?\n", (int)(cb - cbslots));
  935. return -1;
  936. }
  937. if(isa->port == 0 && ct->io[0].start == 0) {
  938. unlock(cb);
  939. print("#Y%d: No part or start address\n", (int)(cb - cbslots));
  940. return -1;
  941. }
  942. cb->special = 1; /* taken */
  943. /* route interrupts */
  944. isa->irq = irq;
  945. wrreg(cb, Rigc, irq | Fnotreset | Fiocard);
  946. /* set power and enable device */
  947. x = vcode(ct->vpp1);
  948. wrreg(cb, Rpc, x|Fautopower|Foutena|Fcardena);
  949. /* 16-bit data path */
  950. if(ct->bit16)
  951. x = Ftiming|Fiocs16|Fwidth16;
  952. else
  953. x = Ftiming;
  954. if(ct->nio == 2 && ct->io[1].start)
  955. x |= x<<4;
  956. wrreg(cb, Rio, x);
  957. /*
  958. * enable io port map 0
  959. * the 'top' register value includes the last valid address
  960. */
  961. if(isa->port == 0)
  962. isa->port = ct->io[0].start;
  963. we = rdreg(cb, Rwe);
  964. wrreg(cb, Riobtm0lo, isa->port);
  965. wrreg(cb, Riobtm0hi, isa->port>>8);
  966. i = isa->port+ct->io[0].len-1;
  967. wrreg(cb, Riotop0lo, i);
  968. wrreg(cb, Riotop0hi, i>>8);
  969. we |= 1<<6;
  970. if(ct->nio == 2 && ct->io[1].start){
  971. wrreg(cb, Riobtm1lo, ct->io[1].start);
  972. wrreg(cb, Riobtm1hi, ct->io[1].start>>8);
  973. i = ct->io[1].start+ct->io[1].len-1;
  974. wrreg(cb, Riotop1lo, i);
  975. wrreg(cb, Riotop1hi, i>>8);
  976. we |= 1<<7;
  977. }
  978. wrreg(cb, Rwe, we);
  979. /* only touch Rconfig if it is present */
  980. if(pi->conf_present & (1<<Rconfig)){
  981. PCMmap *m;
  982. /* Reset adapter */
  983. m = isamap(cb, pi->conf_addr + Rconfig, 1, 1);
  984. p = KADDR(m->isa + pi->conf_addr + Rconfig - m->ca);
  985. /* set configuration and interrupt type */
  986. x = ct->index;
  987. if(ct->irqtype & 0x20)
  988. x |= Clevel;
  989. *p = x;
  990. delay(5);
  991. isaunmap(m);
  992. }
  993. pi->port = isa->port;
  994. pi->irq = isa->irq;
  995. unlock(cb);
  996. print("#Y%ld: %s irq %d, port %lX\n", cb - cbslots, pi->verstr, isa->irq, isa->port);
  997. return (int)(cb - cbslots);
  998. }
  999. static void
  1000. pccard_pcmspecialclose(int slotno)
  1001. {
  1002. Cardbus *cb = &cbslots[slotno];
  1003. wrreg(cb, Rwe, 0); /* no windows */
  1004. cb->special = 0;
  1005. }
  1006. static Chan*
  1007. pccardattach(char *spec)
  1008. {
  1009. if (!managerstarted) {
  1010. managerstarted = 1;
  1011. kproc("cardbus", processevents, nil);
  1012. }
  1013. return devattach('Y', spec);
  1014. }
  1015. enum
  1016. {
  1017. Qdir,
  1018. Qctl,
  1019. Nents = 1,
  1020. };
  1021. #define SLOTNO(c) ((ulong)((c->qid.path>>8)&0xff))
  1022. #define TYPE(c) ((ulong)(c->qid.path&0xff))
  1023. #define QID(s,t) (((s)<<8)|(t))
  1024. static int
  1025. pccardgen(Chan *c, char*, Dirtab *, int , int i, Dir *dp)
  1026. {
  1027. int slotno;
  1028. Qid qid;
  1029. long len;
  1030. int entry;
  1031. if(i == DEVDOTDOT){
  1032. mkqid(&qid, Qdir, 0, QTDIR);
  1033. devdir(c, qid, "#Y", 0, eve, 0555, dp);
  1034. return 1;
  1035. }
  1036. len = 0;
  1037. if(i >= Nents * nslots) return -1;
  1038. slotno = i / Nents;
  1039. entry = i % Nents;
  1040. if (entry == 0) {
  1041. qid.path = QID(slotno, Qctl);
  1042. snprint(up->genbuf, sizeof up->genbuf, "cb%dctl", slotno);
  1043. }
  1044. else {
  1045. /* Entries for memory regions. I'll implement them when
  1046. needed. (pb) */
  1047. }
  1048. qid.vers = 0;
  1049. qid.type = QTFILE;
  1050. devdir(c, qid, up->genbuf, len, eve, 0660, dp);
  1051. return 1;
  1052. }
  1053. static Walkqid*
  1054. pccardwalk(Chan *c, Chan *nc, char **name, int nname)
  1055. {
  1056. return devwalk(c, nc, name, nname, 0, 0, pccardgen);
  1057. }
  1058. static int
  1059. pccardstat(Chan *c, uchar *db, int n)
  1060. {
  1061. return devstat(c, db, n, 0, 0, pccardgen);
  1062. }
  1063. static void
  1064. increfp(Cardbus *cb)
  1065. {
  1066. lock(&cb->refslock);
  1067. cb->refs++;
  1068. unlock(&cb->refslock);
  1069. }
  1070. static void
  1071. decrefp(Cardbus *cb)
  1072. {
  1073. lock(&cb->refslock);
  1074. cb->refs--;
  1075. unlock(&cb->refslock);
  1076. }
  1077. static Chan*
  1078. pccardopen(Chan *c, int omode)
  1079. {
  1080. if (c->qid.type & QTDIR){
  1081. if(omode != OREAD)
  1082. error(Eperm);
  1083. } else
  1084. increfp(&cbslots[SLOTNO(c)]);
  1085. c->mode = openmode(omode);
  1086. c->flag |= COPEN;
  1087. c->offset = 0;
  1088. return c;
  1089. }
  1090. static void
  1091. pccardclose(Chan *c)
  1092. {
  1093. if(c->flag & COPEN)
  1094. if((c->qid.type & QTDIR) == 0)
  1095. decrefp(&cbslots[SLOTNO(c)]);
  1096. }
  1097. static long
  1098. pccardread(Chan *c, void *a, long n, vlong offset)
  1099. {
  1100. Cardbus *cb;
  1101. char *buf, *p, *e;
  1102. int i;
  1103. switch(TYPE(c)){
  1104. case Qdir:
  1105. return devdirread(c, a, n, 0, 0, pccardgen);
  1106. case Qctl:
  1107. buf = p = malloc(READSTR);
  1108. buf[0] = 0;
  1109. e = p + READSTR;
  1110. cb = &cbslots[SLOTNO(c)];
  1111. lock(cb);
  1112. p = seprint(p, e, "slot %ld: %s; ", cb - cbslots, states[cb->state]);
  1113. switch (cb->type) {
  1114. case -1:
  1115. seprint(p, e, "\n");
  1116. break;
  1117. case PC32:
  1118. if (cb->pci->bridge) {
  1119. Pcidev *pci = cb->pci->bridge;
  1120. int i;
  1121. while (pci) {
  1122. p = seprint(p, e, "%.4uX %.4uX; irq %d\n",
  1123. pci->vid, pci->did, pci->intl);
  1124. for (i = 0; i != Nbars; i++)
  1125. if (pci->mem[i].size)
  1126. p = seprint(p, e,
  1127. "\tmem[%d] %.8ulX (%.8uX)\n",
  1128. i, pci->mem[i].bar,
  1129. pci->mem[i].size);
  1130. if (pci->rom.size)
  1131. p = seprint(p, e, "\tROM %.8ulX (%.8uX)\n",
  1132. pci->rom.bar, pci->rom.size);
  1133. pci = pci->list;
  1134. }
  1135. }
  1136. break;
  1137. case PC16:
  1138. if (cb->state == SlotConfigured) {
  1139. Pcminfo *pi = &cb->linfo;
  1140. p = seprint(p, e, "%s port %X; irq %d;\n",
  1141. pi->verstr, pi->port,
  1142. pi->irq);
  1143. for (i = 0; i != pi->nctab; i++) {
  1144. PCMconftab *ct;
  1145. int j;
  1146. ct = &pi->ctab[i];
  1147. p = seprint(p, e,
  1148. "\tconfiguration[%d] irqs %.4uX; vpp %d, %d; %s\n",
  1149. i, ct->irqs, ct->vpp1, ct->vpp2,
  1150. (ct == pi->defctab)? "(default);": "");
  1151. for (j = 0; j != ct->nio; j++)
  1152. if (ct->io[j].len > 0)
  1153. p = seprint(p, e, "\t\tio[%d] %.8ulX %uld\n",
  1154. j, ct->io[j].start, ct->io[j].len);
  1155. }
  1156. }
  1157. break;
  1158. }
  1159. unlock(cb);
  1160. n = readstr(offset, a, n, buf);
  1161. free(buf);
  1162. return n;
  1163. }
  1164. return 0;
  1165. }
  1166. static long
  1167. pccardwrite(Chan *c, void *v, long n, vlong)
  1168. {
  1169. Rune r;
  1170. ulong n0;
  1171. char *device;
  1172. Cmdbuf *cbf;
  1173. Cmdtab *ct;
  1174. Cardbus *cb;
  1175. n0 = n;
  1176. switch(TYPE(c)){
  1177. case Qctl:
  1178. cb = &cbslots[SLOTNO(c)];
  1179. cbf = parsecmd(v, n);
  1180. if(waserror()){
  1181. free(cbf);
  1182. nexterror();
  1183. }
  1184. ct = lookupcmd(cbf, pccardctlmsg, nelem(pccardctlmsg));
  1185. switch(ct->index){
  1186. case CMdown:
  1187. device = cbf->f[1];
  1188. device += chartorune(&r, device);
  1189. if ((n = devno(r, 1)) >= 0 && devtab[n]->config)
  1190. devtab[n]->config(0, device, nil);
  1191. qengine(cb, CardEjected);
  1192. break;
  1193. case CMpower:
  1194. if ((cb->regs[SocketState] & SS_CCD) == 0)
  1195. qengine(cb, CardDetected);
  1196. break;
  1197. }
  1198. poperror();
  1199. free(cbf);
  1200. break;
  1201. }
  1202. return n0 - n;
  1203. }
  1204. Dev pccarddevtab = {
  1205. 'Y',
  1206. "cardbus",
  1207. devreset,
  1208. devinit,
  1209. devshutdown,
  1210. pccardattach,
  1211. pccardwalk,
  1212. pccardstat,
  1213. pccardopen,
  1214. devcreate,
  1215. pccardclose,
  1216. pccardread,
  1217. devbread,
  1218. pccardwrite,
  1219. devbwrite,
  1220. devremove,
  1221. devwstat,
  1222. };
  1223. static PCMmap *
  1224. isamap(Cardbus *cb, ulong offset, int len, int attr)
  1225. {
  1226. uchar we, bit;
  1227. PCMmap *m, *nm;
  1228. Pcminfo *pi;
  1229. int i;
  1230. ulong e;
  1231. pi = &cb->linfo;
  1232. /* convert offset to granularity */
  1233. if(len <= 0)
  1234. len = 1;
  1235. e = ROUND(offset+len, Mgran);
  1236. offset &= Mmask;
  1237. len = e - offset;
  1238. /* look for a map that covers the right area */
  1239. we = rdreg(cb, Rwe);
  1240. bit = 1;
  1241. nm = 0;
  1242. for(m = pi->mmap; m < &pi->mmap[nelem(pi->mmap)]; m++){
  1243. if((we & bit))
  1244. if(m->attr == attr)
  1245. if(offset >= m->ca && e <= m->cea){
  1246. m->ref++;
  1247. return m;
  1248. }
  1249. bit <<= 1;
  1250. if(nm == 0 && m->ref == 0)
  1251. nm = m;
  1252. }
  1253. m = nm;
  1254. if(m == 0)
  1255. return 0;
  1256. /* if isa space isn't big enough, free it and get more */
  1257. if(m->len < len){
  1258. if(m->isa){
  1259. umbfree(m->isa, m->len);
  1260. m->len = 0;
  1261. }
  1262. m->isa = PADDR(umbmalloc(0, len, Mgran));
  1263. if(m->isa == 0){
  1264. print("isamap: out of isa space\n");
  1265. return 0;
  1266. }
  1267. m->len = len;
  1268. }
  1269. /* set up new map */
  1270. m->ca = offset;
  1271. m->cea = m->ca + m->len;
  1272. m->attr = attr;
  1273. i = m - pi->mmap;
  1274. bit = 1<<i;
  1275. wrreg(cb, Rwe, we & ~bit); /* disable map before changing it */
  1276. wrreg(cb, MAP(i, Mbtmlo), m->isa>>Mshift);
  1277. wrreg(cb, MAP(i, Mbtmhi), (m->isa>>(Mshift+8)) | F16bit);
  1278. wrreg(cb, MAP(i, Mtoplo), (m->isa+m->len-1)>>Mshift);
  1279. wrreg(cb, MAP(i, Mtophi), ((m->isa+m->len-1)>>(Mshift+8)));
  1280. offset -= m->isa;
  1281. offset &= (1<<25)-1;
  1282. offset >>= Mshift;
  1283. wrreg(cb, MAP(i, Mofflo), offset);
  1284. wrreg(cb, MAP(i, Moffhi), (offset>>8) | (attr ? Fregactive : 0));
  1285. wrreg(cb, Rwe, we | bit); /* enable map */
  1286. m->ref = 1;
  1287. return m;
  1288. }
  1289. static void
  1290. isaunmap(PCMmap* m)
  1291. {
  1292. m->ref--;
  1293. }
  1294. /*
  1295. * reading and writing card registers
  1296. */
  1297. static uchar
  1298. rdreg(Cardbus *cb, int index)
  1299. {
  1300. outb(cb->lindex, cb->lbase + index);
  1301. return inb(cb->ldata);
  1302. }
  1303. static void
  1304. wrreg(Cardbus *cb, int index, uchar val)
  1305. {
  1306. outb(cb->lindex, cb->lbase + index);
  1307. outb(cb->ldata, val);
  1308. }
  1309. static int
  1310. readc(Cisdat *cis, uchar *x)
  1311. {
  1312. if(cis->cispos >= cis->cislen)
  1313. return 0;
  1314. *x = cis->cisbase[cis->cisskip*cis->cispos];
  1315. cis->cispos++;
  1316. return 1;
  1317. }
  1318. static ulong
  1319. getlong(Cisdat *cis, int size)
  1320. {
  1321. uchar c;
  1322. int i;
  1323. ulong x;
  1324. x = 0;
  1325. for(i = 0; i < size; i++){
  1326. if(readc(cis, &c) != 1)
  1327. break;
  1328. x |= c<<(i*8);
  1329. }
  1330. return x;
  1331. }
  1332. static void
  1333. tcfig(Cardbus *cb, Cisdat *cis, int )
  1334. {
  1335. uchar size, rasize, rmsize;
  1336. uchar last;
  1337. Pcminfo *pi;
  1338. if(readc(cis, &size) != 1)
  1339. return;
  1340. rasize = (size&0x3) + 1;
  1341. rmsize = ((size>>2)&0xf) + 1;
  1342. if(readc(cis, &last) != 1)
  1343. return;
  1344. pi = &cb->linfo;
  1345. pi->conf_addr = getlong(cis, rasize);
  1346. pi->conf_present = getlong(cis, rmsize);
  1347. }
  1348. static void
  1349. tvers1(Cardbus *cb, Cisdat *cis, int )
  1350. {
  1351. uchar c, major, minor, last;
  1352. int i;
  1353. Pcminfo *pi;
  1354. pi = &cb->linfo;
  1355. if(readc(cis, &major) != 1)
  1356. return;
  1357. if(readc(cis, &minor) != 1)
  1358. return;
  1359. last = 0;
  1360. for(i = 0; i < sizeof(pi->verstr) - 1; i++){
  1361. if(readc(cis, &c) != 1)
  1362. return;
  1363. if(c == 0)
  1364. c = ';';
  1365. if(c == '\n')
  1366. c = ';';
  1367. if(c == 0xff)
  1368. break;
  1369. if(c == ';' && last == ';')
  1370. continue;
  1371. pi->verstr[i] = c;
  1372. last = c;
  1373. }
  1374. pi->verstr[i] = 0;
  1375. }
  1376. static ulong
  1377. microvolt(Cisdat *cis)
  1378. {
  1379. uchar c;
  1380. ulong microvolts;
  1381. ulong exp;
  1382. if(readc(cis, &c) != 1)
  1383. return 0;
  1384. exp = exponent[c&0x7];
  1385. microvolts = vmant[(c>>3)&0xf]*exp;
  1386. while(c & 0x80){
  1387. if(readc(cis, &c) != 1)
  1388. return 0;
  1389. switch(c){
  1390. case 0x7d:
  1391. break; /* high impedence when sleeping */
  1392. case 0x7e:
  1393. case 0x7f:
  1394. microvolts = 0; /* no connection */
  1395. break;
  1396. default:
  1397. exp /= 10;
  1398. microvolts += exp*(c&0x7f);
  1399. }
  1400. }
  1401. return microvolts;
  1402. }
  1403. static ulong
  1404. nanoamps(Cisdat *cis)
  1405. {
  1406. uchar c;
  1407. ulong nanoamps;
  1408. if(readc(cis, &c) != 1)
  1409. return 0;
  1410. nanoamps = exponent[c&0x7]*vmant[(c>>3)&0xf];
  1411. while(c & 0x80){
  1412. if(readc(cis, &c) != 1)
  1413. return 0;
  1414. if(c == 0x7d || c == 0x7e || c == 0x7f)
  1415. nanoamps = 0;
  1416. }
  1417. return nanoamps;
  1418. }
  1419. /*
  1420. * only nominal voltage (feature 1) is important for config,
  1421. * other features must read card to stay in sync.
  1422. */
  1423. static ulong
  1424. power(Cisdat *cis)
  1425. {
  1426. uchar feature;
  1427. ulong mv;
  1428. mv = 0;
  1429. if(readc(cis, &feature) != 1)
  1430. return 0;
  1431. if(feature & 1)
  1432. mv = microvolt(cis);
  1433. if(feature & 2)
  1434. microvolt(cis);
  1435. if(feature & 4)
  1436. microvolt(cis);
  1437. if(feature & 8)
  1438. nanoamps(cis);
  1439. if(feature & 0x10)
  1440. nanoamps(cis);
  1441. if(feature & 0x20)
  1442. nanoamps(cis);
  1443. if(feature & 0x40)
  1444. nanoamps(cis);
  1445. return mv/1000000;
  1446. }
  1447. static ulong
  1448. ttiming(Cisdat *cis, int scale)
  1449. {
  1450. uchar unscaled;
  1451. ulong nanosecs;
  1452. if(readc(cis, &unscaled) != 1)
  1453. return 0;
  1454. nanosecs = (mantissa[(unscaled>>3)&0xf]*exponent[unscaled&7])/10;
  1455. nanosecs = nanosecs * exponent[scale];
  1456. return nanosecs;
  1457. }
  1458. static void
  1459. timing(Cisdat *cis, PCMconftab *ct)
  1460. {
  1461. uchar c, i;
  1462. if(readc(cis, &c) != 1)
  1463. return;
  1464. i = c&0x3;
  1465. if(i != 3)
  1466. ct->maxwait = ttiming(cis, i); /* max wait */
  1467. i = (c>>2)&0x7;
  1468. if(i != 7)
  1469. ct->readywait = ttiming(cis, i); /* max ready/busy wait */
  1470. i = (c>>5)&0x7;
  1471. if(i != 7)
  1472. ct->otherwait = ttiming(cis, i); /* reserved wait */
  1473. }
  1474. static void
  1475. iospaces(Cisdat *cis, PCMconftab *ct)
  1476. {
  1477. uchar c;
  1478. int i, nio;
  1479. ct->nio = 0;
  1480. if(readc(cis, &c) != 1)
  1481. return;
  1482. ct->bit16 = ((c>>5)&3) >= 2;
  1483. if(!(c & 0x80)){
  1484. ct->io[0].start = 0;
  1485. ct->io[0].len = 1<<(c&0x1f);
  1486. ct->nio = 1;
  1487. return;
  1488. }
  1489. if(readc(cis, &c) != 1)
  1490. return;
  1491. /*
  1492. * For each of the range descriptions read the
  1493. * start address and the length (value is length-1).
  1494. */
  1495. nio = (c&0xf)+1;
  1496. for(i = 0; i < nio; i++){
  1497. ct->io[i].start = getlong(cis, (c>>4)&0x3);
  1498. ct->io[i].len = getlong(cis, (c>>6)&0x3)+1;
  1499. }
  1500. ct->nio = nio;
  1501. }
  1502. static void
  1503. irq(Cisdat *cis, PCMconftab *ct)
  1504. {
  1505. uchar c;
  1506. if(readc(cis, &c) != 1)
  1507. return;
  1508. ct->irqtype = c & 0xe0;
  1509. if(c & 0x10)
  1510. ct->irqs = getlong(cis, 2);
  1511. else
  1512. ct->irqs = 1<<(c&0xf);
  1513. ct->irqs &= 0xDEB8; /* levels available to card */
  1514. }
  1515. static void
  1516. memspace(Cisdat *cis, int asize, int lsize, int host)
  1517. {
  1518. ulong haddress, address, len;
  1519. len = getlong(cis, lsize)*256;
  1520. address = getlong(cis, asize)*256;
  1521. USED(len, address);
  1522. if(host){
  1523. haddress = getlong(cis, asize)*256;
  1524. USED(haddress);
  1525. }
  1526. }
  1527. static void
  1528. tentry(Cardbus *cb, Cisdat *cis, int )
  1529. {
  1530. uchar c, i, feature;
  1531. PCMconftab *ct;
  1532. Pcminfo *pi;
  1533. pi = &cb->linfo;
  1534. if(pi->nctab >= nelem(pi->ctab))
  1535. return;
  1536. if(readc(cis, &c) != 1)
  1537. return;
  1538. ct = &pi->ctab[pi->nctab++];
  1539. /* copy from last default config */
  1540. if(pi->defctab)
  1541. *ct = *pi->defctab;
  1542. ct->index = c & 0x3f;
  1543. /* is this the new default? */
  1544. if(c & 0x40)
  1545. pi->defctab = ct;
  1546. /* memory wait specified? */
  1547. if(c & 0x80){
  1548. if(readc(cis, &i) != 1)
  1549. return;
  1550. if(i&0x80)
  1551. ct->memwait = 1;
  1552. }
  1553. if(readc(cis, &feature) != 1)
  1554. return;
  1555. switch(feature&0x3){
  1556. case 1:
  1557. ct->vpp1 = ct->vpp2 = power(cis);
  1558. break;
  1559. case 2:
  1560. power(cis);
  1561. ct->vpp1 = ct->vpp2 = power(cis);
  1562. break;
  1563. case 3:
  1564. power(cis);
  1565. ct->vpp1 = power(cis);
  1566. ct->vpp2 = power(cis);
  1567. break;
  1568. default:
  1569. break;
  1570. }
  1571. if(feature&0x4)
  1572. timing(cis, ct);
  1573. if(feature&0x8)
  1574. iospaces(cis, ct);
  1575. if(feature&0x10)
  1576. irq(cis, ct);
  1577. switch((feature>>5)&0x3){
  1578. case 1:
  1579. memspace(cis, 0, 2, 0);
  1580. break;
  1581. case 2:
  1582. memspace(cis, 2, 2, 0);
  1583. break;
  1584. case 3:
  1585. if(readc(cis, &c) != 1)
  1586. return;
  1587. for(i = 0; i <= (c&0x7); i++)
  1588. memspace(cis, (c>>5)&0x3, (c>>3)&0x3, c&0x80);
  1589. break;
  1590. }
  1591. }
  1592. static void
  1593. i82365probe(Cardbus *cb, int lindex, int ldata)
  1594. {
  1595. uchar c, id;
  1596. int dev = 0; /* According to the Ricoh spec 00->3F _and_ 80->BF seem
  1597. to be the same socket A (ditto for B). */
  1598. outb(lindex, Rid + (dev<<7));
  1599. id = inb(ldata);
  1600. if((id & 0xf0) != 0x80)
  1601. return; /* not a memory & I/O card */
  1602. if((id & 0x0f) == 0x00)
  1603. return; /* no revision number, not possible */
  1604. cb->lindex = lindex;
  1605. cb->ldata = ldata;
  1606. cb->ltype = Ti82365;
  1607. cb->lbase = (int)(cb - cbslots) * 0x40;
  1608. switch(id){
  1609. case 0x82:
  1610. case 0x83:
  1611. case 0x84:
  1612. /* could be a cirrus */
  1613. outb(cb->lindex, Rchipinfo + (dev<<7));
  1614. outb(cb->ldata, 0);
  1615. c = inb(cb->ldata);
  1616. if((c & 0xc0) != 0xc0)
  1617. break;
  1618. c = inb(cb->ldata);
  1619. if((c & 0xc0) != 0x00)
  1620. break;
  1621. if(c & 0x20){
  1622. cb->ltype = Tpd6720;
  1623. } else {
  1624. cb->ltype = Tpd6710;
  1625. }
  1626. /* low power mode */
  1627. outb(cb->lindex, Rmisc2 + (dev<<7));
  1628. c = inb(cb->ldata);
  1629. outb(cb->ldata, c & ~Flowpow);
  1630. break;
  1631. break;
  1632. }
  1633. /* if it's not a Cirrus, it could be a Vadem... */
  1634. if(cb->ltype == Ti82365){
  1635. /* unlock the Vadem extended regs */
  1636. outb(cb->lindex, 0x0E + (dev<<7));
  1637. outb(cb->lindex, 0x37 + (dev<<7));
  1638. /* make the id register show the Vadem id */
  1639. outb(cb->lindex, 0x3A + (dev<<7));
  1640. c = inb(cb->ldata);
  1641. outb(cb->ldata, c|0xC0);
  1642. outb(cb->lindex, Rid + (dev<<7));
  1643. c = inb(cb->ldata);
  1644. if(c & 0x08)
  1645. cb->ltype = Tvg46x;
  1646. /* go back to Intel compatible id */
  1647. outb(cb->lindex, 0x3A + (dev<<7));
  1648. c = inb(cb->ldata);
  1649. outb(cb->ldata, c & ~0xC0);
  1650. }
  1651. }
  1652. static int
  1653. vcode(int volt)
  1654. {
  1655. switch(volt){
  1656. case 5:
  1657. return 1;
  1658. case 12:
  1659. return 2;
  1660. default:
  1661. return 0;
  1662. }
  1663. }