ethervgbe.c 26 KB

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  1. /*
  2. * VIA Velocity gigabit ethernet.
  3. * Register info has been stolen from FreeBSD driver.
  4. *
  5. * Has been tested on:
  6. * - VIA8237 (ABIT AV8): 100Mpbs Full duplex only.
  7. * It works enough to run replica/pull, vncv, ...
  8. *
  9. * To do:
  10. * - 64/48 bits
  11. * - autonegotiation
  12. * - thresholds
  13. * - dynamic ring sizing ??
  14. * - link status change
  15. * - shutdown
  16. * - promiscuous
  17. * - report error
  18. * - Rx/Tx Csum
  19. * - Jumbo frames
  20. *
  21. * Philippe Anel, xigh@free.fr
  22. */
  23. #include "u.h"
  24. #include "../port/lib.h"
  25. #include "mem.h"
  26. #include "dat.h"
  27. #include "fns.h"
  28. #include "io.h"
  29. #include "../port/error.h"
  30. #include "../port/netif.h"
  31. #include "etherif.h"
  32. #include "ethermii.h"
  33. #define DEBUG
  34. enum
  35. {
  36. DumpIntr = (1<<0),
  37. DumpRx = (1<<1),
  38. DumpTx = (1<<2),
  39. };
  40. #define htole16(x) (x)
  41. #define htole32(x) (x)
  42. #define le32toh(x) (x)
  43. enum
  44. {
  45. Timeout = 50000,
  46. RxCount = 256,
  47. TxCount = 256,
  48. RxSize = 2048,
  49. EthAddr = 0x00,
  50. /* Command registers. */
  51. Cr0S = 0x08, /* Global command 0 (Set) */
  52. Cr0C = 0x0c, /* Global command 0 (Clear) */
  53. Cr0_Start = 0x01, /* - start MAC */
  54. Cr0_Stop = 0x02, /* - stop MAC */
  55. Cr0_EnableRx = 0x04, /* - turn on Rx engine */
  56. Cr0_EnableTx = 0x08, /* - turn on Tx engine */
  57. Cr1S = 0x09, /* Global command 1 (Set) */
  58. Cr1C = 0x0d, /* Global command 1 (Clear) */
  59. Cr1_NoPool = 0x08, /* - disable Rx/Tx desc pool */
  60. Cr1_reset = 0x80, /* - software reset */
  61. Cr2S = 0x0a, /* Global command 2 (Set) */
  62. Cr2_XonEnable = 0x80, /* - 802.3x XON/XOFF flow control */
  63. Cr3S = 0x0b, /* Global command 3 (Set) */
  64. Cr3C = 0x0f, /* Global command 3 (Set) */
  65. Cr3_IntMask = 0x02, /* - Mask all interrupts */
  66. /* Eeprom registers. */
  67. Eecsr = 0x93, /* EEPROM control/status */
  68. Eecsr_Autold = 0x20, /* - trigger reload from EEPROM */
  69. /* Mii registers. */
  70. MiiStatus = 0x6D, /* MII port status */
  71. MiiStatus_idle = 0x80, /* - idle */
  72. MiiCmd = 0x70, /* MII command */
  73. MiiCmd_write = 0x20, /* - write */
  74. MiiCmd_read = 0x40, /* - read */
  75. MiiCmd_auto = 0x80, /* - enable autopolling */
  76. MiiAddr = 0x71, /* MII address */
  77. MiiData = 0x72, /* MII data */
  78. /* 64 bits related registers. */
  79. TxDescHi = 0x18,
  80. DataBufHi = 0x1d,
  81. /* Rx engine registers. */
  82. RxDescLo = 0x38, /* Rx descriptor base address (lo 32 bits) */
  83. RxCsrS = 0x32, /* Rx descriptor queue control/status (Set) */
  84. RxCsrC = 0x36, /* Rx descriptor queue control/status (Clear) */
  85. RxCsr_RunQueue = 0x01, /* - enable queue */
  86. RxCsr_Active = 0x02, /* - queue active indicator */
  87. RxCsr_Wakeup = 0x04, /* - wake up queue */
  88. RxCsr_Dead = 0x08, /* - queue dead indicator */
  89. RxNum = 0x50, /* Size of Rx desc ring */
  90. RxDscIdx = 0x3c, /* Current Rx descriptor index */
  91. RxResCnt = 0x5e, /* Rx descriptor residue count */
  92. RxHostErr = 0x23, /* Rx host error status */
  93. RxTimer = 0x3e, /* Rx queue timer pend */
  94. RxControl = 0x06, /* MAC Rx control */
  95. RxControl_BadFrame = 0x01, /* - accept CRC error frames */
  96. RxControl_Runt = 0x02, /* - accept runts */
  97. RxControl_MultiCast = 0x04, /* - accept multicasts */
  98. RxControl_BroadCast = 0x08, /* - accept broadcasts */
  99. RxControl_Promisc = 0x10, /* - promisc mode */
  100. RxControl_Giant = 0x20, /* - accept VLAN tagged frames */
  101. RxControl_UniCast = 0x40, /* - use perfect filtering */
  102. RxControl_SymbolErr = 0x80, /* - accept symbol err packet */
  103. RxConfig = 0x7e, /* MAC Rx config */
  104. RxConfig_VlanFilter = 0x01, /* - filter VLAN ID mismatches */
  105. RxConfig_VlanOpt0 = (0<<1), /* - TX: no tag insert, RX: all, no extr */
  106. RxConfig_VlanOpt1 = (1<<1), /* - TX: no tag insert, RX: tagged pkts, no extr */
  107. RxConfig_VlanOpt2 = (2<<1), /* - TX: tag insert, RX: all, extract tags */
  108. RxConfig_VlanOpt3 = (3<<1), /* - TX: tag insert, RX: tagged pkts, with extr */
  109. RxConfig_FifoLowWat = 0x08, /* - RX FIFO low watermark (7QW/15QW) */
  110. RxConfig_FifoTh128 = (0<<4), /* - RX FIFO threshold 128 bytes */
  111. RxConfig_FifoTh512 = (1<<4), /* - RX FIFO threshold 512 bytes */
  112. RxConfig_FifoTh1024 = (2<<4), /* - RX FIFO threshold 1024 bytes */
  113. RxConfig_FifoThFwd = (3<<4), /* - RX FIFO threshold ??? */
  114. RxConfig_ArbPrio = 0x80, /* - arbitration priority */
  115. /* Tx engine registers. */
  116. TxDescLo = 0x40, /* Tx descriptor base address (lo 32 bits) */
  117. TxCsrS = 0x30, /* Tx descriptor queue control/status (Set) */
  118. TxCsrC = 0x38, /* Tx descriptor queue control/status (Clear) */
  119. TxCsr_RunQueue = 0x01, /* - enable queue */
  120. TxCsr_Active = 0x02, /* - queue active indicator */
  121. TxCsr_Wakeup = 0x04, /* - wake up queue */
  122. TxCsr_Dead = 0x08, /* - queue dead indicator */
  123. TxNum = 0x52, /* Size of Tx desc ring */
  124. TxDscIdx = 0x54, /* Current Tx descriptor index */
  125. TxHostErr = 0x22, /* Tx host error status */
  126. TxTimer = 0x3f, /* Tx queue timer pend */
  127. TxControl = 0x07, /* MAC Rx control */
  128. TxControl_LC_Off = (0<<0), /* - loopback control off */
  129. TxControl_LC_Mac = (1<<0), /* - loopback control MAC internal */
  130. TxControl_LC_Ext = (2<<0), /* - loopback control external */
  131. TxControl_Coll16 = (0<<2), /* - one set of 16 retries */
  132. TxControl_Coll32 = (1<<2), /* - two sets of 16 retries */
  133. TxControl_Coll48 = (2<<2), /* - three sets of 16 retries */
  134. TxControl_CollInf = (3<<2), /* - retry forever */
  135. TxConfig = 0x7f, /* MAC Tx config */
  136. TxConfig_SnapOpt = 0x01, /* - 1 == insert VLAN tag at 13th byte, */
  137. /* 0 == insert VLAN tag after SNAP header (21st byte) */
  138. TxConfig_NonBlk = 0x02, /* - priority TX/non-blocking mode */
  139. TxConfig_Blk64 = (0<<3), /* - non-blocking threshold 64 packets */
  140. TxConfig_Blk32 = (1<<3), /* - non-blocking threshold 32 packets */
  141. TxConfig_Blk128 = (2<<3), /* - non-blocking threshold 128 packets */
  142. TxConfig_Blk8 = (3<<3), /* - non-blocking threshold 8 packets */
  143. TxConfig_ArbPrio = 0x80, /* - arbitration priority */
  144. /* Timer registers. */
  145. Timer0 = 0x74, /* single-shot timer */
  146. Timer1 = 0x76, /* periodic timer */
  147. /* Chip config registers. */
  148. ChipCfgA = 0x78, /* chip config A */
  149. ChipCfgB = 0x79, /* chip config B */
  150. ChipCfgC = 0x7a, /* chip config C */
  151. ChipCfgD = 0x7b, /* chip config D */
  152. /* DMA config registers. */
  153. DmaCfg0 = 0x7C, /* DMA config 0 */
  154. DmaCfg1 = 0x7D, /* DMA config 1 */
  155. /* Interrupt registers. */
  156. IntCtl = 0x20, /* Interrupt control */
  157. Imr = 0x28, /* Interrupt mask */
  158. Isr = 0x24, /* Interrupt status */
  159. Isr_RxHiPrio = (1<<0), /* - hi prio Rx int */
  160. Isr_TxHiPrio = (1<<1), /* - hi prio Tx int */
  161. Isr_RxComplete = (1<<2), /* - Rx queue completed */
  162. Isr_TxComplete = (1<<3), /* - One of Tx queues completed */
  163. Isr_TxComplete0 = (1<<4), /* - Tx queue 0 completed */
  164. Isr_TxComplete1 = (1<<5), /* - Tx queue 1 completed */
  165. Isr_TxComplete2 = (1<<6), /* - Tx queue 2 completed */
  166. Isr_TxComplete3 = (1<<7), /* - Tx queue 3 completed */
  167. Isr_Reserved8 = (1<<8), /* - reserved */
  168. Isr_Reserver9 = (1<<9), /* - reserved */
  169. Isr_RxCountOvflow = (1<<10), /* - Rx packet count overflow */
  170. Isr_RxPause = (1<<11), /* - pause frame Rx */
  171. Isr_RxFifoOvflow = (1<<12), /* - RX FIFO overflow */
  172. Isr_RxNoDesc = (1<<13), /* - ran out of Rx descriptors */
  173. Isr_RxNoDescWar = (1<<14), /* - running out of Rx descriptors */
  174. Isr_LinkStatus = (1<<15), /* - link status change */
  175. Isr_Timer0 = (1<<16), /* - one shot timer expired */
  176. Isr_Timer1 = (1<<17), /* - periodic timer expired */
  177. Isr_Power = (1<<18), /* - wake up power event */
  178. Isr_PhyIntr = (1<<19), /* - PHY interrupt */
  179. Isr_Stopped = (1<<20), /* - software shutdown complete */
  180. Isr_MibOvflow = (1<<21), /* - MIB counter overflow warning */
  181. Isr_SoftIntr = (1<<22), /* - software interrupt */
  182. Isr_HoldOffReload = (1<<23), /* - reload hold timer */
  183. Isr_RxDmaStall = (1<<24), /* - Rx DMA stall */
  184. Isr_TxDmaStall = (1<<25), /* - Tx DMA stall */
  185. Isr_Reserved26 = (1<<26), /* - reserved */
  186. Isr_Reserved27 = (1<<27), /* - reserved */
  187. Isr_Source0 = (1<<28), /* - interrupt source indication */
  188. Isr_Source1 = (1<<29), /* - interrupt source indication */
  189. Isr_Source2 = (1<<30), /* - interrupt source indication */
  190. Isr_Source3 = (1<<31), /* - interrupt source indication */
  191. Isr_Mask = Isr_TxComplete0|Isr_RxComplete|Isr_Stopped|
  192. Isr_RxFifoOvflow|Isr_PhyIntr|Isr_LinkStatus|
  193. Isr_RxNoDesc|Isr_RxDmaStall|Isr_TxDmaStall
  194. };
  195. typedef struct Frag Frag;
  196. struct Frag
  197. {
  198. ulong addr_lo;
  199. ushort addr_hi;
  200. ushort length;
  201. };
  202. typedef struct RxDesc RxDesc;
  203. struct RxDesc
  204. {
  205. ulong status;
  206. ulong control;
  207. Frag;
  208. };
  209. typedef struct TxDesc TxDesc;
  210. struct TxDesc
  211. {
  212. ulong status;
  213. ulong control;
  214. Frag frags[7];
  215. };
  216. enum
  217. {
  218. RxDesc_Status_VidMiss = (1<<0), /* VLAN tag filter miss */
  219. RxDesc_Status_CrcErr = (1<<1), /* bad CRC error */
  220. RxDesc_Status_FrAlErr = (1<<3), /* frame alignment error */
  221. RxDesc_Status_CsumErr = (1<<3), /* bad TCP/IP checksum */
  222. RxDesc_Status_RxLenErr = (1<<4), /* Rx length error */
  223. RxDesc_Status_SymErr = (1<<5), /* PCS symbol error */
  224. RxDesc_Status_SnTag = (1<<6), /* RX'ed tagged SNAP pkt */
  225. RxDesc_Status_DeTag = (1<<7), /* VLAN tag extracted */
  226. RxDesc_Status_OneFrag = (0<<8), /* only one fragment */
  227. RxDesc_Status_FirstFrag = (1<<8), /* first frag in frame */
  228. RxDesc_Status_LastFrag = (2<<8), /* last frag in frame */
  229. RxDesc_Status_MidFrag = (3<<8), /* intermediate frag */
  230. RxDesc_Status_Vtag = (1<<10), /* VLAN tag indicator */
  231. RxDesc_Status_UniCast = (1<<11), /* unicast frame */
  232. RxDesc_Status_BroadCast = (1<<12), /* broadcast frame */
  233. RxDesc_Status_MultiCast = (1<<13), /* multicast frame */
  234. RxDesc_Status_Perfect = (1<<14), /* perfect filter hit */
  235. RxDesc_Status_Goodframe = (1<<15), /* frame is good. */
  236. RxDesc_Status_SizShift = 16, /* received frame len shift */
  237. RxDesc_Status_SizMask = 0x3FFF, /* received frame len mask */
  238. RxDesc_Status_Shutdown = (1<<30), /* shutdown during RX */
  239. RxDesc_Status_Own = (1<<31), /* own bit */
  240. /* ... */
  241. TxDesc_Status_Own = (1<<31), /* own bit */
  242. /* ... */
  243. TxDesc_Control_Intr = (1<<23), /* Tx intr request */
  244. TxDesc_Control_Normal = (3<<24), /* normal frame */
  245. };
  246. typedef struct Stats Stats;
  247. struct Stats
  248. {
  249. ulong rx;
  250. ulong tx;
  251. ulong txe;
  252. ulong intr;
  253. };
  254. typedef struct Ctlr Ctlr;
  255. struct Ctlr
  256. {
  257. Ctlr* link;
  258. Pcidev* pdev;
  259. int port;
  260. int inited;
  261. Lock init_lock;
  262. ulong debugflags;
  263. ulong debugcount;
  264. Mii* mii;
  265. int active;
  266. uchar ea[6];
  267. RxDesc* rx_ring;
  268. Block* rx_blocks[RxCount];
  269. Lock tx_lock;
  270. TxDesc* tx_ring;
  271. Block* tx_blocks[TxCount];
  272. ulong tx_count;
  273. Stats stats;
  274. };
  275. static Ctlr* vgbehead;
  276. static Ctlr* vgbetail;
  277. #define riob(c, r) inb(c->port + r)
  278. #define riow(c, r) ins(c->port + r)
  279. #define riol(c, r) inl(c->port + r)
  280. #define wiob(c, r, d) outb(c->port + r, d)
  281. #define wiow(c, r, d) outs(c->port + r, d)
  282. #define wiol(c, r, d) outl(c->port + r, d)
  283. #define siob(c, r, b) wiob(c, r, riob(c, r) | b)
  284. #define siow(c, r, b) wiow(c, r, riob(c, r) | b)
  285. #define siol(c, r, b) wiol(c, r, riob(c, r) | b)
  286. #define ciob(c, r, b) wiob(c, r, riob(c, r) & ~b)
  287. #define ciow(c, r, b) wiow(c, r, riob(c, r) & ~b)
  288. #define ciol(c, r, b) wiol(c, r, riob(c, r) & ~b)
  289. static int
  290. vgbemiiw(Mii* mii, int phy, int addr, int data)
  291. {
  292. Ctlr* ctlr;
  293. int i;
  294. if(phy != 1)
  295. return -1;
  296. ctlr = mii->ctlr;
  297. wiob(ctlr, MiiAddr, addr);
  298. wiow(ctlr, MiiData, (ushort) data);
  299. wiob(ctlr, MiiCmd, MiiCmd_write);
  300. for(i = 0; i < Timeout; i++)
  301. if((riob(ctlr, MiiCmd) & MiiCmd_write) == 0)
  302. break;
  303. if(i >= Timeout){
  304. print("vgbe: miiw timeout\n");
  305. return -1;
  306. }
  307. return 0;
  308. }
  309. static int
  310. vgbemiir(Mii* mii, int phy, int addr)
  311. {
  312. Ctlr* ctlr;
  313. int i;
  314. if(phy != 1)
  315. return -1;
  316. ctlr = mii->ctlr;
  317. wiob(ctlr, MiiAddr, addr);
  318. wiob(ctlr, MiiCmd, MiiCmd_read);
  319. for(i = 0; i < Timeout; i++)
  320. if((riob(ctlr, MiiCmd) & MiiCmd_read) == 0)
  321. break;
  322. if(i >= Timeout){
  323. print("vgbe: miir timeout\n");
  324. return -1;
  325. }
  326. return riow(ctlr, MiiData);
  327. }
  328. static long
  329. vgbeifstat(Ether* edev, void* a, long n, ulong offset)
  330. {
  331. char* p;
  332. Ctlr* ctlr;
  333. int l;
  334. ctlr = edev->ctlr;
  335. p = malloc(2*READSTR);
  336. l = 0;
  337. l += snprint(p+l, 2*READSTR-l, "tx: %uld\n", ctlr->stats.tx);
  338. l += snprint(p+l, 2*READSTR-l, "tx [errs]: %uld\n", ctlr->stats.txe);
  339. l += snprint(p+l, 2*READSTR-l, "rx: %uld\n", ctlr->stats.rx);
  340. l += snprint(p+l, 2*READSTR-l, "intr: %uld\n", ctlr->stats.intr);
  341. snprint(p+l, 2*READSTR-l, "\n");
  342. n = readstr(offset, a, n, p);
  343. free(p);
  344. return n;
  345. }
  346. static char* vgbeisr_info[] = {
  347. "hi prio Rx int",
  348. "hi prio Tx int",
  349. "Rx queue completed",
  350. "One of Tx queues completed",
  351. "Tx queue 0 completed",
  352. "Tx queue 1 completed",
  353. "Tx queue 2 completed",
  354. "Tx queue 3 completed",
  355. "reserved",
  356. "reserved",
  357. "Rx packet count overflow",
  358. "pause frame Rx'ed",
  359. "RX FIFO overflow",
  360. "ran out of Rx descriptors",
  361. "running out of Rx descriptors",
  362. "link status change",
  363. "one shot timer expired",
  364. "periodic timer expired",
  365. "wake up power event",
  366. "PHY interrupt",
  367. "software shutdown complete",
  368. "MIB counter overflow warning",
  369. "software interrupt",
  370. "reload hold timer",
  371. "Rx DMA stall",
  372. "Tx DMA stall",
  373. "reserved",
  374. "reserved",
  375. "interrupt source indication 0",
  376. "interrupt source indication 1",
  377. "interrupt source indication 2",
  378. "interrupt source indication 3",
  379. };
  380. static void
  381. vgbedumpisr(ulong isr)
  382. {
  383. int i;
  384. for(i = 0; i < 32; i++){
  385. ulong mask;
  386. mask = 1<<i;
  387. if(isr & mask)
  388. print("vgbe: irq: - %02d : %c %s\n", i,
  389. Isr_Mask & mask ? '*' : '-', vgbeisr_info[i]);
  390. }
  391. }
  392. static int
  393. vgbenewrx(Ctlr* ctlr, int i)
  394. {
  395. Block* block;
  396. RxDesc* desc;
  397. /* Allocate Rx block. (TODO: Alignment ?) */
  398. block = allocb(RxSize);
  399. /* Remember that block. */
  400. ctlr->rx_blocks[i] = block;
  401. /* Initialize Rx descriptor. (TODO: 48/64 bits support ?) */
  402. desc = &ctlr->rx_ring[i];
  403. desc->status = htole32(RxDesc_Status_Own);
  404. desc->control = htole32(0);
  405. desc->addr_lo = htole32((ulong)PCIWADDR(block->rp));
  406. desc->addr_hi = htole16(0);
  407. desc->length = htole16(RxSize | 0x8000);
  408. return 0;
  409. }
  410. static void
  411. vgberxeof(Ether* edev)
  412. {
  413. Ctlr* ctlr;
  414. int i;
  415. Block* block;
  416. ulong length, status;
  417. RxDesc* desc;
  418. ctlr = edev->ctlr;
  419. if(ctlr->debugflags & DumpRx)
  420. print("vgbe: rx_eof\n");
  421. for(i = 0; i < RxCount; i++){
  422. /* Remember that block. */
  423. desc = &ctlr->rx_ring[i];
  424. status = le32toh(desc->status);
  425. if(status & RxDesc_Status_Own)
  426. continue;
  427. if(status & RxDesc_Status_Goodframe){
  428. length = status >> RxDesc_Status_SizShift;
  429. length &= RxDesc_Status_SizMask;
  430. if(ctlr->debugflags & DumpRx)
  431. print("vgbe: Rx-desc[%03d] status=%#08ulx ctl=%#08ulx len=%uld bytes\n",
  432. i, status, desc->control, length);
  433. block = ctlr->rx_blocks[i];
  434. block->wp = block->rp + length;
  435. ctlr->stats.rx++;
  436. etheriq(edev, block, 0);
  437. }
  438. else
  439. print("vgbe: Rx-desc[%#02x] *BAD FRAME* status=%#08ulx ctl=%#08ulx\n",
  440. i, status, desc->control);
  441. /* reset packet ... */
  442. desc->status = htole32(RxDesc_Status_Own);
  443. desc->control = htole32(0);
  444. }
  445. if(ctlr->debugflags & DumpRx)
  446. print("vgbe: rx_eof: done\n");
  447. wiow(ctlr, RxResCnt, RxCount);
  448. wiob(ctlr, RxCsrS, RxCsr_Wakeup);
  449. }
  450. static void
  451. vgbetxeof(Ether* edev)
  452. {
  453. Ctlr* ctlr;
  454. int i, count;
  455. Block* block;
  456. ulong status;
  457. ctlr = edev->ctlr;
  458. ilock(&ctlr->tx_lock);
  459. if(ctlr->debugflags & DumpTx)
  460. print("vgbe: tx_eof\n");
  461. for(count = 0, i = 0; i < TxCount; i++){
  462. block = ctlr->tx_blocks[i];
  463. if(block == nil)
  464. continue;
  465. status = le32toh(ctlr->tx_ring[i].status);
  466. if(status & TxDesc_Status_Own)
  467. continue;
  468. /* Todo add info if it failed */
  469. ctlr->stats.tx++;
  470. if(ctlr->debugflags & DumpTx)
  471. print("vgbe: Block[%03d]:%#p has been sent\n", i, block);
  472. count++;
  473. ctlr->tx_blocks[i] = nil;
  474. freeb(block);
  475. if(ctlr->debugflags & DumpTx)
  476. print("vgbe: Block[%03d]:%#p has been freed\n", i, block);
  477. }
  478. ctlr->tx_count -= count;
  479. if(ctlr->debugflags & DumpTx)
  480. print("vgbe: tx_eof: done [count=%d]\n", count);
  481. iunlock(&ctlr->tx_lock);
  482. if(ctlr->tx_count)
  483. wiob(ctlr, TxCsrS, TxCsr_Wakeup);
  484. }
  485. static void
  486. vgbeinterrupt(Ureg *, void* arg)
  487. {
  488. Ether* edev;
  489. Ctlr* ctlr;
  490. ulong status;
  491. edev = (Ether *) arg;
  492. if(edev == nil)
  493. return;
  494. ctlr = edev->ctlr;
  495. if(ctlr == nil)
  496. return;
  497. /* Mask interrupts. */
  498. wiol(ctlr, Imr, 0);
  499. status = riol(ctlr, Isr);
  500. if(status == 0xffff)
  501. goto end;
  502. /* acknowledge */
  503. if(status)
  504. wiol(ctlr, Isr, status);
  505. if((status & Isr_Mask) == 0)
  506. goto end;
  507. ctlr->stats.intr++;
  508. if(ctlr->debugflags & DumpIntr)
  509. if(ctlr->debugcount){
  510. print("vgbe: irq: status = %#08ulx\n", status);
  511. vgbedumpisr(status);
  512. ctlr->debugcount--;
  513. }
  514. if(status & Isr_RxComplete)
  515. vgberxeof(edev);
  516. if(status & Isr_TxComplete0)
  517. vgbetxeof(edev);
  518. if(status & Isr_Stopped)
  519. print("vgbe: irq: software shutdown complete\n");
  520. if(status & Isr_RxFifoOvflow)
  521. print("vgbe: irq: RX FIFO overflow\n");
  522. if(status & Isr_PhyIntr)
  523. print("vgbe: irq: PHY interrupt\n");
  524. if(status & Isr_LinkStatus)
  525. print("vgbe: irq: link status change\n");
  526. if(status & Isr_RxNoDesc)
  527. print("vgbe: irq: ran out of Rx descriptors\n");
  528. if(status & Isr_RxDmaStall){
  529. print("vgbe: irq: Rx DMA stall\n");
  530. wiol(ctlr, Cr3C, Cr3_IntMask);
  531. return;
  532. }
  533. if(status & Isr_TxDmaStall){
  534. print("vgbe: irq: Tx DMA stall\n");
  535. wiol(ctlr, Cr3C, Cr3_IntMask);
  536. return;
  537. }
  538. end:
  539. /* Unmask interrupts. */
  540. wiol(ctlr, Imr, ~0);
  541. }
  542. static void
  543. vgbetransmit(Ether* edev)
  544. {
  545. Block* block;
  546. Ctlr* ctlr;
  547. int i, index, start, count;
  548. TxDesc* desc;
  549. ulong status, length;
  550. ctlr = edev->ctlr;
  551. ilock(&ctlr->tx_lock);
  552. start = riow(ctlr, TxDscIdx);
  553. if(ctlr->debugflags & DumpTx)
  554. print("vgbe: transmit (start=%d)\n", start);
  555. /* find empty slot */
  556. for(count = 0, i = 0; i < TxCount; i++){
  557. index = (i + start) % TxCount;
  558. if(ctlr->tx_blocks[index])
  559. continue;
  560. desc = &ctlr->tx_ring[index];
  561. status = le32toh(desc->status);
  562. if(status & TxDesc_Status_Own)
  563. continue;
  564. block = qget(edev->oq);
  565. if(block == nil)
  566. break;
  567. count++;
  568. length = BLEN(block);
  569. if(ctlr->debugflags & DumpTx)
  570. print("vgbe: Tx-Desc[%03d] Block:%#p, addr=%#08ulx, len:%ld\n", index, block,
  571. PCIWADDR(block->rp), length);
  572. ctlr->tx_blocks[index] = block;
  573. /* Initialize Tx descriptor. */
  574. desc->status = htole32((length<<16)|TxDesc_Status_Own);
  575. desc->control = htole32(TxDesc_Control_Intr|TxDesc_Control_Normal|((1+1)<<28));
  576. desc->frags[0].addr_lo = htole32((ulong) PCIWADDR(block->rp));
  577. desc->frags[0].addr_hi = htole16(0);
  578. desc->frags[0].length = htole16(length);
  579. }
  580. ctlr->tx_count += count;
  581. if(ctlr->debugflags & DumpTx)
  582. print("vgbe: transmit: done [count=%d]\n", count);
  583. iunlock(&ctlr->tx_lock);
  584. if(ctlr->tx_count)
  585. wiob(ctlr, TxCsrS, TxCsr_Wakeup);
  586. if(count == 0)
  587. print("vgbe: transmit: no Tx entry available\n");
  588. }
  589. static void
  590. vgbeattach(Ether* edev)
  591. {
  592. Ctlr* ctlr;
  593. RxDesc* rxdesc;
  594. TxDesc* txdesc;
  595. int i;
  596. ctlr = edev->ctlr;
  597. lock(&ctlr->init_lock);
  598. if(ctlr->inited){
  599. unlock(&ctlr->init_lock);
  600. return;
  601. }
  602. // print("vgbe: attach\n");
  603. /* Allocate Rx ring. (TODO: Alignment ?) */
  604. rxdesc = mallocalign(RxCount* sizeof(RxDesc), 256, 0, 0);
  605. if(rxdesc == nil){
  606. print("vgbe: unable to alloc Rx ring\n");
  607. unlock(&ctlr->init_lock);
  608. return;
  609. }
  610. ctlr->rx_ring = rxdesc;
  611. /* Allocate Rx blocks, initialize Rx ring. */
  612. for(i = 0; i < RxCount; i++)
  613. vgbenewrx(ctlr, i);
  614. /* Init Rx MAC. */
  615. wiob(ctlr, RxControl,
  616. RxControl_MultiCast|RxControl_BroadCast|RxControl_UniCast);
  617. wiob(ctlr, RxConfig, RxConfig_VlanOpt0);
  618. /* Load Rx ring. */
  619. wiol(ctlr, RxDescLo, (ulong) PCIWADDR(rxdesc));
  620. wiow(ctlr, RxNum, RxCount - 1);
  621. wiow(ctlr, RxDscIdx, 0);
  622. wiow(ctlr, RxResCnt, RxCount);
  623. /* Allocate Tx ring. */
  624. txdesc = mallocalign(TxCount* sizeof(TxDesc), 256, 0, 0);
  625. if(txdesc == nil){
  626. print("vgbe: unable to alloc Tx ring\n");
  627. unlock(&ctlr->init_lock);
  628. return;
  629. }
  630. ctlr->tx_ring = txdesc;
  631. /* Init DMAs */
  632. wiob(ctlr, DmaCfg0, 4);
  633. /* Init Tx MAC. */
  634. wiob(ctlr, TxControl, 0);
  635. wiob(ctlr, TxConfig, TxConfig_NonBlk|TxConfig_ArbPrio);
  636. /* Load Tx ring. */
  637. wiol(ctlr, TxDescLo, (ulong) PCIWADDR(txdesc));
  638. wiow(ctlr, TxNum, TxCount - 1);
  639. wiow(ctlr, TxDscIdx, 0);
  640. /* Enable Xon/Xoff */
  641. wiob(ctlr, Cr2S, 0xb|Cr2_XonEnable);
  642. /* Enable Rx queue */
  643. wiob(ctlr, RxCsrS, RxCsr_RunQueue);
  644. /* Enable Tx queue */
  645. wiob(ctlr, TxCsrS, TxCsr_RunQueue);
  646. /* Done */
  647. ctlr->inited = 1;
  648. unlock(&ctlr->init_lock);
  649. /* Enable interrupts */
  650. wiol(ctlr, Isr, 0xffffffff);
  651. wiob(ctlr, Cr3S, Cr3_IntMask);
  652. /* Wake up Rx queue */
  653. wiob(ctlr, RxCsrS, RxCsr_Wakeup);
  654. }
  655. static void
  656. vgbereset(Ctlr* ctlr)
  657. {
  658. // MiiPhy* phy;
  659. int timeo, i;
  660. // print("vgbe: reset\n");
  661. /* Soft reset the controller. */
  662. wiob(ctlr, Cr1S, Cr1_reset);
  663. for(timeo = 0; timeo < Timeout; timeo++)
  664. if((riob(ctlr, Cr1S) & Cr1_reset) == 0)
  665. break;
  666. if(timeo >= Timeout){
  667. print("vgbe: softreset timeout\n");
  668. return;
  669. }
  670. /* Reload eeprom. */
  671. siob(ctlr, Eecsr, Eecsr_Autold);
  672. for(timeo = 0; timeo < Timeout; timeo++)
  673. if((riob(ctlr, Eecsr) & Eecsr_Autold) == 0)
  674. break;
  675. if(timeo >= Timeout){
  676. print("vgbe: eeprom reload timeout\n");
  677. return;
  678. }
  679. /* Load the MAC address. */
  680. for(i = 0; i < Eaddrlen; i++)
  681. ctlr->ea[i] = riob(ctlr, EthAddr+i);
  682. /* Initialize interrupts. */
  683. wiol(ctlr, Isr, 0xffffffff);
  684. wiol(ctlr, Imr, 0xffffffff);
  685. /* Disable interrupts. */
  686. wiol(ctlr, Cr3C, Cr3_IntMask);
  687. /* 32 bits addresses only. (TODO: 64 bits ?) */
  688. wiol(ctlr, TxDescHi, 0);
  689. wiow(ctlr, DataBufHi, 0);
  690. /* Enable MAC (turning off Rx/Tx engines for the moment). */
  691. wiob(ctlr, Cr0C, Cr0_Stop|Cr0_EnableRx|Cr0_EnableTx);
  692. wiob(ctlr, Cr0S, Cr0_Start);
  693. /* Initialize Rx engine. */
  694. wiow(ctlr, RxCsrC, RxCsr_RunQueue);
  695. /* Initialize Tx engine. */
  696. wiow(ctlr, TxCsrC, TxCsr_RunQueue);
  697. /* Enable Rx/Tx engines. */
  698. wiob(ctlr, Cr0S, Cr0_EnableRx|Cr0_EnableTx);
  699. /* Initialize link management. */
  700. ctlr->mii = malloc(sizeof(Mii));
  701. if(ctlr->mii == nil){
  702. print("vgbe: unable to alloc Mii\n");
  703. return;
  704. }
  705. ctlr->mii->mir = vgbemiir;
  706. ctlr->mii->miw = vgbemiiw;
  707. ctlr->mii->ctlr = ctlr;
  708. if(mii(ctlr->mii, 1<<1) == 0){
  709. print("vgbe: no phy found\n");
  710. return;
  711. }
  712. // phy = ctlr->mii->curphy;
  713. // print("vgbe: phy:oui %#x\n", phy->oui);
  714. }
  715. static void
  716. vgbepci(void)
  717. {
  718. Pcidev* pdev;
  719. // print("vgbe: pci\n");
  720. pdev = nil;
  721. while(pdev = pcimatch(pdev, 0, 0)){
  722. Ctlr* ctlr;
  723. int port, size;
  724. if(pdev->ccrb != 0x02 || pdev->ccru != 0)
  725. continue;
  726. switch((pdev->did<<16) | pdev->vid){
  727. default:
  728. continue;
  729. case (0x3119<<16)|0x1106: /* VIA Velocity (VT6122) */
  730. break;
  731. }
  732. if((pdev->pcr & 1) == 0){
  733. print("vgbe: io not enabled [pcr=%#lux]\n", (ulong)pdev->pcr);
  734. continue;
  735. }
  736. pcisetbme(pdev);
  737. pcisetpms(pdev, 0);
  738. port = pdev->mem[0].bar;
  739. size = pdev->mem[0].size;
  740. if((port & 1) == 0){
  741. print("vgbe: bar[0]=%#x is not io\n", port);
  742. continue;
  743. }
  744. if(port > 0xff00){
  745. print("vgbe: invalid port %#ux\n", port);
  746. continue;
  747. }
  748. port &= 0xfffe;
  749. if(size != 256){
  750. print("vgbe: invalid io size: %d\n", size);
  751. continue;
  752. }
  753. if(ioalloc(port, size, 0, "vge") < 0){
  754. print("vgbe: port %#ux already in use\n", port);
  755. continue;
  756. }
  757. ctlr = malloc(sizeof(Ctlr));
  758. if(ctlr == nil){
  759. print("vgbe: unable to alloc Ctlr\n");
  760. iofree(port);
  761. continue;
  762. }
  763. ctlr->pdev = pdev;
  764. ctlr->port = port;
  765. ctlr->inited = 0;
  766. if(vgbehead != nil)
  767. vgbetail->link = ctlr;
  768. else
  769. vgbehead = ctlr;
  770. vgbetail = ctlr;
  771. }
  772. }
  773. static long
  774. vgbectl(Ether* edev, void* buf, long n)
  775. {
  776. Cmdbuf* cb;
  777. Ctlr* ctlr;
  778. ulong index;
  779. char* rptr;
  780. RxDesc* rd;
  781. TxDesc* td;
  782. uchar* p;
  783. ctlr = edev->ctlr;
  784. cb = parsecmd(buf, n);
  785. if(waserror()){
  786. free(cb);
  787. nexterror();
  788. }
  789. if(cistrcmp(cb->f[0], "reset") == 0){
  790. vgbereset(ctlr);
  791. wiob(ctlr, Cr3S, Cr3_IntMask);
  792. wiob(ctlr, RxCsrS, RxCsr_RunQueue);
  793. wiob(ctlr, RxCsrS, RxCsr_Wakeup);
  794. }
  795. else if(cistrcmp(cb->f[0], "dumpintr") == 0){
  796. if(cb->nf < 2)
  797. error(Ecmdargs);
  798. if(cistrcmp(cb->f[1], "on") == 0){
  799. ctlr->debugflags |= DumpIntr;
  800. ctlr->debugcount = ~0;
  801. }
  802. else if(cistrcmp(cb->f[1], "off") == 0)
  803. ctlr->debugflags &= ~DumpIntr;
  804. else{
  805. ulong count;
  806. char* rptr;
  807. count = strtoul(cb->f[1], &rptr, 0);
  808. if(rptr == cb->f[1])
  809. error("invalid control request");
  810. ctlr->debugflags |= DumpIntr;
  811. ctlr->debugcount = count;
  812. print("vgbe: debugcount set to %uld\n", count);
  813. }
  814. }
  815. else if(cistrcmp(cb->f[0], "dumprx") == 0){
  816. if(cb->nf < 2)
  817. error(Ecmdargs);
  818. if(cistrcmp(cb->f[1], "on") == 0)
  819. ctlr->debugflags |= DumpRx;
  820. else if(cistrcmp(cb->f[1], "off") == 0)
  821. ctlr->debugflags &= ~DumpRx;
  822. else{
  823. index = strtoul(cb->f[1], &rptr, 0);
  824. if((rptr == cb->f[1]) || (index >= RxCount))
  825. error("invalid control request");
  826. rd = &ctlr->rx_ring[index];
  827. print("vgbe: DumpRx[%03uld] status=%#08ulx ctl=%#08ulx len=%#04ux bytes\n",
  828. index, rd->status, rd->control, rd->length);
  829. }
  830. }
  831. else if(cistrcmp(cb->f[0], "dumptx") == 0){
  832. if(cb->nf < 2)
  833. error(Ecmdargs);
  834. if(cistrcmp(cb->f[1], "on") == 0)
  835. ctlr->debugflags |= DumpTx;
  836. else if(cistrcmp(cb->f[1], "off") == 0)
  837. ctlr->debugflags &= ~DumpTx;
  838. else{
  839. index = strtoul(cb->f[1], &rptr, 0);
  840. if((rptr == cb->f[1]) || (index >= TxCount))
  841. error("invalid control request");
  842. td = &ctlr->tx_ring[index];
  843. print("vgbe: DumpTx[%03uld] status=%#08ulx ctl=%#08ulx len=%#04ux bytes",
  844. index, td->status, td->control, td->frags[0].length);
  845. p = (uchar*)td;
  846. for(index = 0; index < sizeof(TxDesc); index++){
  847. if((index % 16) == 0)
  848. print("\nvgbe: ");
  849. else
  850. print(" ");
  851. print("%#02x", p[index]);
  852. }
  853. }
  854. }
  855. else if(cistrcmp(cb->f[0], "dumpall") == 0){
  856. if(cb->nf < 2)
  857. error(Ecmdargs);
  858. if(cistrcmp(cb->f[1], "on") == 0){
  859. ctlr->debugflags = ~0;
  860. ctlr->debugcount = ~0;
  861. }
  862. else if(cistrcmp(cb->f[1], "off") == 0)
  863. ctlr->debugflags = 0;
  864. else error("invalid control request");
  865. }
  866. else
  867. error(Ebadctl);
  868. free(cb);
  869. poperror();
  870. return n;
  871. }
  872. static void
  873. vgbepromiscuous(void* arg, int on)
  874. {
  875. USED(arg, on);
  876. }
  877. /* multicast already on, don't need to do anything */
  878. static void
  879. vgbemulticast(void*, uchar*, int)
  880. {
  881. }
  882. static int
  883. vgbepnp(Ether* edev)
  884. {
  885. Ctlr* ctlr;
  886. // print("vgbe: pnp\n");
  887. if(vgbehead == nil)
  888. vgbepci();
  889. for(ctlr = vgbehead; ctlr != nil; ctlr = ctlr->link){
  890. if(ctlr->active)
  891. continue;
  892. if(edev->port == 0 || edev->port == ctlr->port){
  893. ctlr->active = 1;
  894. break;
  895. }
  896. }
  897. if(ctlr == nil)
  898. return -1;
  899. vgbereset(ctlr);
  900. edev->ctlr = ctlr;
  901. edev->port = ctlr->port;
  902. edev->irq = ctlr->pdev->intl;
  903. edev->tbdf = ctlr->pdev->tbdf;
  904. edev->mbps = 1000;
  905. memmove(edev->ea, ctlr->ea, Eaddrlen);
  906. edev->attach = vgbeattach;
  907. edev->transmit = vgbetransmit;
  908. edev->interrupt = vgbeinterrupt;
  909. edev->ifstat = vgbeifstat;
  910. // edev->promiscuous = vgbepromiscuous;
  911. edev->multicast = vgbemulticast;
  912. // edev->shutdown = vgbeshutdown;
  913. edev->ctl = vgbectl;
  914. edev->arg = edev;
  915. return 0;
  916. }
  917. void
  918. ethervgbelink(void)
  919. {
  920. addethercard("vgbe", vgbepnp);
  921. }