piix4smbus.c 5.1 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. //
  8. // SMBus support for the PIIX4
  9. //
  10. enum
  11. {
  12. IntelVendID= 0x8086,
  13. Piix4PMID= 0x7113, /* PIIX4 power management function */
  14. // SMBus configuration registers (function 3)
  15. SMBbase= 0x90, // 4 byte base address (bit 0 == 1, bit 3:1 == 0)
  16. SMBconfig= 0xd2,
  17. SMBintrselect= (7<<1),
  18. SMIenable= (0<<1), // interrupts sent to SMI#
  19. IRQ9enable= (4<<1), // intettupts sent to IRQ9
  20. SMBenable= (1<<0), // 1 enables
  21. // SMBus IO space registers
  22. Hoststatus= 0x0, // (writing 1 bits reset the interrupt bits)
  23. Failed= (1<<4), // transaction terminated by KILL
  24. Bus_error= (1<<3), // transactio collision
  25. Dev_error= (1<<2), // device error interrupt
  26. Host_complete= (1<<1), // host command completion interrupt
  27. Host_busy= (1<<0), //
  28. Slavestatus= 0x1, // (writing 1 bits reset)
  29. Alert_sts= (1<<5), // someone asserted SMBALERT#
  30. Shdw2_sts= (1<<4), // slave accessed shadow 2 port
  31. Shdw1_sts= (1<<3), // slave accessed shadow 1 port
  32. Slv_sts= (1<<2), // slave accessed shadow 1 port
  33. Slv_bsy= (1<<0),
  34. Hostcontrol= 0x2,
  35. Start= (1<<6), // start execution
  36. Cmd_prot= (7<<2), // command protocol mask
  37. Quick= (0<<2), // address only
  38. Byte= (1<<2), // address + cmd
  39. ByteData= (2<<2), // address + cmd + data
  40. WordData= (3<<2), // address + cmd + data + data
  41. Kill= (1<<1), // abort in progress command
  42. Ienable= (1<<0), // enable completion interrupts
  43. Hostcommand= 0x3,
  44. Hostaddress= 0x4,
  45. AddressMask= (0x7f<<1), // target address
  46. Read= (1<<0), // 1 == read, 0 == write
  47. Hostdata0= 0x5,
  48. Hostdata1= 0x6,
  49. Blockdata= 0x7,
  50. Slavecontrol= 0x8,
  51. Alert_en= (1<<3), // enable inter on SMBALERT#
  52. Shdw2_en= (1<<2), // enable inter on external shadow 2 access
  53. Shdw1_en= (1<<1), // enable inter on external shadow 1 access
  54. Slv_en= (1<<0), // enable inter on access of host ctlr slave port
  55. Shadowcommand= 0x9,
  56. Slaveevent= 0xa,
  57. Slavedata= 0xc,
  58. };
  59. static struct
  60. {
  61. int rw;
  62. int cmd;
  63. int len;
  64. int proto;
  65. } proto[] =
  66. {
  67. [SMBquick] { 0, 0, 0, Quick },
  68. [SMBsend] { 0, 1, 0, Byte },
  69. [SMBbytewrite] { 0, 1, 1, ByteData },
  70. [SMBwordwrite] { 0, 1, 2, WordData },
  71. [SMBrecv] { Read, 0, 1, Byte },
  72. [SMBbyteread] { Read, 1, 1, ByteData },
  73. [SMBwordread] { Read, 1, 2, WordData },
  74. };
  75. static void
  76. transact(SMBus *s, int type, int addr, int cmd, uchar *data)
  77. {
  78. int tries, status;
  79. char err[256];
  80. if(type < 0 || type > nelem(proto))
  81. panic("piix4smbus: illegal transaction type %d", type);
  82. if(waserror()){
  83. qunlock(s);
  84. nexterror();
  85. }
  86. qlock(s);
  87. // wait a while for the host interface to be available
  88. for(tries = 0; tries < 1000000; tries++){
  89. if((inb(s->base+Hoststatus) & Host_busy) == 0)
  90. break;
  91. sched();
  92. }
  93. if(tries >= 1000000){
  94. // try aborting current transaction
  95. outb(s->base+Hostcontrol, Kill);
  96. for(tries = 0; tries < 1000000; tries++){
  97. if((inb(s->base+Hoststatus) & Host_busy) == 0)
  98. break;
  99. sched();
  100. }
  101. if(tries >= 1000000){
  102. snprint(err, sizeof(err), "SMBus jammed: %2.2ux", inb(s->base+Hoststatus));
  103. error(err);
  104. }
  105. }
  106. // set up for transaction
  107. outb(s->base+Hostaddress, (addr<<1)|proto[type].rw);
  108. if(proto[type].cmd)
  109. outb(s->base+Hostcommand, cmd);
  110. if(proto[type].rw != Read){
  111. switch(proto[type].len){
  112. case 2:
  113. outb(s->base+Hostdata1, data[1]);
  114. // fall through
  115. case 1:
  116. outb(s->base+Hostdata0, data[0]);
  117. break;
  118. }
  119. }
  120. // reset the completion/error bits and start transaction
  121. outb(s->base+Hoststatus, Failed|Bus_error|Dev_error|Host_complete);
  122. outb(s->base+Hostcontrol, Start|proto[type].proto);
  123. // wait for completion
  124. status = 0;
  125. for(tries = 0; tries < 1000000; tries++){
  126. status = inb(s->base+Hoststatus);
  127. if(status & (Failed|Bus_error|Dev_error|Host_complete))
  128. break;
  129. sched();
  130. }
  131. if((status & Host_complete) == 0){
  132. snprint(err, sizeof(err), "SMBus request failed: %2.2ux", status);
  133. error(err);
  134. }
  135. // get results
  136. if(proto[type].rw == Read){
  137. switch(proto[type].len){
  138. case 2:
  139. data[1] = inb(s->base+Hostdata1);
  140. // fall through
  141. case 1:
  142. data[0] = inb(s->base+Hostdata0);
  143. break;
  144. }
  145. }
  146. qunlock(s);
  147. poperror();
  148. }
  149. static SMBus smbusproto =
  150. {
  151. .transact = transact,
  152. };
  153. //
  154. // return 0 if this is a piix4 with an smbus interface
  155. //
  156. SMBus*
  157. piix4smbus(void)
  158. {
  159. Pcidev *p;
  160. static SMBus *s;
  161. if(s != nil)
  162. return s;
  163. p = pcimatch(nil, IntelVendID, Piix4PMID);
  164. if(p == nil)
  165. return nil;
  166. s = smalloc(sizeof(*s));
  167. memmove(s, &smbusproto, sizeof(*s));
  168. s->arg = p;
  169. // disable the smbus
  170. pcicfgw8(p, SMBconfig, IRQ9enable|0);
  171. // see if bios gave us a viable port space
  172. s->base = pcicfgr32(p, SMBbase) & ~1;
  173. print("SMB base from bios is 0x%lux\n", s->base);
  174. if(ioalloc(s->base, 0xd, 0, "piix4smbus") < 0){
  175. s->base = ioalloc(-1, 0xd, 2, "piix4smbus");
  176. if(s->base < 0){
  177. free(s);
  178. print("piix4smbus: can't allocate io port\n");
  179. return nil;
  180. }
  181. print("SMB base ialloc is 0x%lux\n", s->base);
  182. pcicfgw32(p, SMBbase, s->base|1);
  183. }
  184. // disable SMBus interrupts, abort any transaction in progress
  185. outb(s->base+Hostcontrol, Kill);
  186. outb(s->base+Slavecontrol, 0);
  187. // enable the smbus
  188. pcicfgw8(p, SMBconfig, IRQ9enable|SMBenable);
  189. return s;
  190. }