pci.c 26 KB

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  1. /*
  2. * PCI support code.
  3. * Needs a massive rewrite.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #define DBG if(0) pcilog
  13. struct
  14. {
  15. char output[16384];
  16. int ptr;
  17. }PCICONS;
  18. int
  19. pcilog(char *fmt, ...)
  20. {
  21. int n;
  22. va_list arg;
  23. char buf[PRINTSIZE];
  24. va_start(arg, fmt);
  25. n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
  26. va_end(arg);
  27. memmove(PCICONS.output+PCICONS.ptr, buf, n);
  28. PCICONS.ptr += n;
  29. return n;
  30. }
  31. enum
  32. { /* configuration mechanism #1 */
  33. PciADDR = 0xCF8, /* CONFIG_ADDRESS */
  34. PciDATA = 0xCFC, /* CONFIG_DATA */
  35. /* configuration mechanism #2 */
  36. PciCSE = 0xCF8, /* configuration space enable */
  37. PciFORWARD = 0xCFA, /* which bus */
  38. MaxFNO = 7,
  39. MaxUBN = 255,
  40. };
  41. enum
  42. { /* command register */
  43. IOen = (1<<0),
  44. MEMen = (1<<1),
  45. MASen = (1<<2),
  46. MemWrInv = (1<<4),
  47. PErrEn = (1<<6),
  48. SErrEn = (1<<8),
  49. };
  50. static Lock pcicfglock;
  51. static Lock pcicfginitlock;
  52. static int pcicfgmode = -1;
  53. static int pcimaxbno = 7;
  54. static int pcimaxdno;
  55. static Pcidev* pciroot;
  56. static Pcidev* pcilist;
  57. static Pcidev* pcitail;
  58. static int nobios, nopcirouting;
  59. static int pcicfgrw32(int, int, int, int);
  60. static int pcicfgrw16(int, int, int, int);
  61. static int pcicfgrw8(int, int, int, int);
  62. static char* bustypes[] = {
  63. "CBUSI",
  64. "CBUSII",
  65. "EISA",
  66. "FUTURE",
  67. "INTERN",
  68. "ISA",
  69. "MBI",
  70. "MBII",
  71. "MCA",
  72. "MPI",
  73. "MPSA",
  74. "NUBUS",
  75. "PCI",
  76. "PCMCIA",
  77. "TC",
  78. "VL",
  79. "VME",
  80. "XPRESS",
  81. };
  82. #pragma varargck type "T" int
  83. static int
  84. tbdffmt(Fmt* fmt)
  85. {
  86. char *p;
  87. int l, r, type, tbdf;
  88. if((p = malloc(READSTR)) == nil)
  89. return fmtstrcpy(fmt, "(tbdfconv)");
  90. switch(fmt->r){
  91. case 'T':
  92. tbdf = va_arg(fmt->args, int);
  93. type = BUSTYPE(tbdf);
  94. if(type < nelem(bustypes))
  95. l = snprint(p, READSTR, bustypes[type]);
  96. else
  97. l = snprint(p, READSTR, "%d", type);
  98. snprint(p+l, READSTR-l, ".%d.%d.%d",
  99. BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
  100. break;
  101. default:
  102. snprint(p, READSTR, "(tbdfconv)");
  103. break;
  104. }
  105. r = fmtstrcpy(fmt, p);
  106. free(p);
  107. return r;
  108. }
  109. ulong
  110. pcibarsize(Pcidev *p, int rno)
  111. {
  112. ulong v, size;
  113. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  114. pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
  115. size = pcicfgrw32(p->tbdf, rno, 0, 1);
  116. if(v & 1)
  117. size |= 0xFFFF0000;
  118. pcicfgrw32(p->tbdf, rno, v, 0);
  119. return -(size & ~0x0F);
  120. }
  121. static int
  122. pcisizcmp(void *a, void *b)
  123. {
  124. Pcisiz *aa, *bb;
  125. aa = a;
  126. bb = b;
  127. return aa->siz - bb->siz;
  128. }
  129. static ulong
  130. pcimask(ulong v)
  131. {
  132. ulong m;
  133. m = BI2BY*sizeof(v);
  134. for(m = 1<<(m-1); m != 0; m >>= 1) {
  135. if(m & v)
  136. break;
  137. }
  138. m--;
  139. if((v & m) == 0)
  140. return v;
  141. v |= m;
  142. return v+1;
  143. }
  144. static void
  145. pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
  146. {
  147. Pcidev *p;
  148. int ntb, i, size, rno, hole;
  149. ulong v, mema, ioa, sioa, smema, base, limit;
  150. Pcisiz *table, *tptr, *mtb, *itb;
  151. extern void qsort(void*, long, long, int (*)(void*, void*));
  152. if(!nobios)
  153. return;
  154. ioa = *pioa;
  155. mema = *pmema;
  156. DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
  157. wrreg, root->tbdf, mema, ioa);
  158. ntb = 0;
  159. for(p = root; p != nil; p = p->link)
  160. ntb++;
  161. ntb *= (PciCIS-PciBAR0)/4;
  162. table = malloc(2*ntb*sizeof(Pcisiz));
  163. itb = table;
  164. mtb = table+ntb;
  165. /*
  166. * Build a table of sizes
  167. */
  168. for(p = root; p != nil; p = p->link) {
  169. if(p->ccrb == 0x06) {
  170. if(p->ccru != 0x04 || p->bridge == nil) {
  171. // DBG("pci: ignored bridge %T\n", p->tbdf);
  172. continue;
  173. }
  174. sioa = ioa;
  175. smema = mema;
  176. pcibusmap(p->bridge, &smema, &sioa, 0);
  177. hole = pcimask(smema-mema);
  178. if(hole < (1<<20))
  179. hole = 1<<20;
  180. p->mema.size = hole;
  181. hole = pcimask(sioa-ioa);
  182. if(hole < (1<<12))
  183. hole = 1<<12;
  184. p->ioa.size = hole;
  185. itb->dev = p;
  186. itb->bar = -1;
  187. itb->siz = p->ioa.size;
  188. itb++;
  189. mtb->dev = p;
  190. mtb->bar = -1;
  191. mtb->siz = p->mema.size;
  192. mtb++;
  193. continue;
  194. }
  195. for(i = 0; i <= 5; i++) {
  196. rno = PciBAR0 + i*4;
  197. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  198. size = pcibarsize(p, rno);
  199. if(size == 0)
  200. continue;
  201. if(v & 1) {
  202. itb->dev = p;
  203. itb->bar = i;
  204. itb->siz = size;
  205. itb++;
  206. }
  207. else {
  208. mtb->dev = p;
  209. mtb->bar = i;
  210. mtb->siz = size;
  211. mtb++;
  212. }
  213. p->mem[i].size = size;
  214. }
  215. }
  216. /*
  217. * Sort both tables IO smallest first, Memory largest
  218. */
  219. qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
  220. tptr = table+ntb;
  221. qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
  222. /*
  223. * Allocate IO address space on this bus
  224. */
  225. for(tptr = table; tptr < itb; tptr++) {
  226. hole = tptr->siz;
  227. if(tptr->bar == -1)
  228. hole = 1<<12;
  229. ioa = (ioa+hole-1) & ~(hole-1);
  230. p = tptr->dev;
  231. if(tptr->bar == -1)
  232. p->ioa.bar = ioa;
  233. else {
  234. p->pcr |= IOen;
  235. p->mem[tptr->bar].bar = ioa|1;
  236. if(wrreg)
  237. pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
  238. }
  239. ioa += tptr->siz;
  240. }
  241. /*
  242. * Allocate Memory address space on this bus
  243. */
  244. for(tptr = table+ntb; tptr < mtb; tptr++) {
  245. hole = tptr->siz;
  246. if(tptr->bar == -1)
  247. hole = 1<<20;
  248. mema = (mema+hole-1) & ~(hole-1);
  249. p = tptr->dev;
  250. if(tptr->bar == -1)
  251. p->mema.bar = mema;
  252. else {
  253. p->pcr |= MEMen;
  254. p->mem[tptr->bar].bar = mema;
  255. if(wrreg)
  256. pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
  257. }
  258. mema += tptr->siz;
  259. }
  260. *pmema = mema;
  261. *pioa = ioa;
  262. free(table);
  263. if(wrreg == 0)
  264. return;
  265. /*
  266. * Finally set all the bridge addresses & registers
  267. */
  268. for(p = root; p != nil; p = p->link) {
  269. if(p->bridge == nil) {
  270. pcicfgrw8(p->tbdf, PciLTR, 64, 0);
  271. p->pcr |= MASen;
  272. pcicfgrw16(p->tbdf, PciPCR, p->pcr, 0);
  273. continue;
  274. }
  275. base = p->ioa.bar;
  276. limit = base+p->ioa.size-1;
  277. v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
  278. v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
  279. pcicfgrw32(p->tbdf, PciIBR, v, 0);
  280. v = (limit & 0xFFFF0000)|(base>>16);
  281. pcicfgrw32(p->tbdf, PciIUBR, v, 0);
  282. base = p->mema.bar;
  283. limit = base+p->mema.size-1;
  284. v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
  285. pcicfgrw32(p->tbdf, PciMBR, v, 0);
  286. /*
  287. * Disable memory prefetch
  288. */
  289. pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
  290. pcicfgrw8(p->tbdf, PciLTR, 64, 0);
  291. /*
  292. * Enable the bridge
  293. */
  294. p->pcr |= IOen|MEMen|MASen;
  295. pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr , 0);
  296. sioa = p->ioa.bar;
  297. smema = p->mema.bar;
  298. pcibusmap(p->bridge, &smema, &sioa, 1);
  299. }
  300. }
  301. static int
  302. pcilscan(int bno, Pcidev** list)
  303. {
  304. Pcidev *p, *head, *tail;
  305. int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
  306. maxubn = bno;
  307. head = nil;
  308. tail = nil;
  309. for(dno = 0; dno <= pcimaxdno; dno++){
  310. maxfno = 0;
  311. for(fno = 0; fno <= maxfno; fno++){
  312. /*
  313. * For this possible device, form the
  314. * bus+device+function triplet needed to address it
  315. * and try to read the vendor and device ID.
  316. * If successful, allocate a device struct and
  317. * start to fill it in with some useful information
  318. * from the device's configuration space.
  319. */
  320. tbdf = MKBUS(BusPCI, bno, dno, fno);
  321. l = pcicfgrw32(tbdf, PciVID, 0, 1);
  322. if(l == 0xFFFFFFFF || l == 0)
  323. continue;
  324. p = malloc(sizeof(*p));
  325. p->tbdf = tbdf;
  326. p->vid = l;
  327. p->did = l>>16;
  328. if(pcilist != nil)
  329. pcitail->list = p;
  330. else
  331. pcilist = p;
  332. pcitail = p;
  333. p->pcr = pcicfgr16(p, PciPCR);
  334. p->rid = pcicfgr8(p, PciRID);
  335. p->ccrp = pcicfgr8(p, PciCCRp);
  336. p->ccru = pcicfgr8(p, PciCCRu);
  337. p->ccrb = pcicfgr8(p, PciCCRb);
  338. p->cls = pcicfgr8(p, PciCLS);
  339. p->ltr = pcicfgr8(p, PciLTR);
  340. p->intl = pcicfgr8(p, PciINTL);
  341. /*
  342. * If the device is a multi-function device adjust the
  343. * loop count so all possible functions are checked.
  344. */
  345. hdt = pcicfgr8(p, PciHDT);
  346. if(hdt & 0x80)
  347. maxfno = MaxFNO;
  348. /*
  349. * If appropriate, read the base address registers
  350. * and work out the sizes.
  351. */
  352. switch(p->ccrb) {
  353. case 0x01: /* mass storage controller */
  354. case 0x02: /* network controller */
  355. case 0x03: /* display controller */
  356. case 0x04: /* multimedia device */
  357. case 0x07: /* simple comm. controllers */
  358. case 0x08: /* base system peripherals */
  359. case 0x09: /* input devices */
  360. case 0x0A: /* docking stations */
  361. case 0x0B: /* processors */
  362. case 0x0C: /* serial bus controllers */
  363. if((hdt & 0x7F) != 0)
  364. break;
  365. rno = PciBAR0 - 4;
  366. for(i = 0; i < nelem(p->mem); i++) {
  367. rno += 4;
  368. p->mem[i].bar = pcicfgr32(p, rno);
  369. p->mem[i].size = pcibarsize(p, rno);
  370. }
  371. break;
  372. case 0x00:
  373. case 0x05: /* memory controller */
  374. case 0x06: /* bridge device */
  375. default:
  376. break;
  377. }
  378. if(head != nil)
  379. tail->link = p;
  380. else
  381. head = p;
  382. tail = p;
  383. }
  384. }
  385. *list = head;
  386. for(p = head; p != nil; p = p->link){
  387. /*
  388. * Find PCI-PCI bridges and recursively descend the tree.
  389. */
  390. if(p->ccrb != 0x06 || p->ccru != 0x04)
  391. continue;
  392. /*
  393. * If the secondary or subordinate bus number is not
  394. * initialised try to do what the PCI BIOS should have
  395. * done and fill in the numbers as the tree is descended.
  396. * On the way down the subordinate bus number is set to
  397. * the maximum as it's not known how many buses are behind
  398. * this one; the final value is set on the way back up.
  399. */
  400. sbn = pcicfgr8(p, PciSBN);
  401. ubn = pcicfgr8(p, PciUBN);
  402. if(sbn == 0 || ubn == 0 || nobios) {
  403. sbn = maxubn+1;
  404. /*
  405. * Make sure memory, I/O and master enables are
  406. * off, set the primary, secondary and subordinate
  407. * bus numbers and clear the secondary status before
  408. * attempting to scan the secondary bus.
  409. *
  410. * Initialisation of the bridge should be done here.
  411. */
  412. pcicfgw32(p, PciPCR, 0xFFFF0000);
  413. l = (MaxUBN<<16)|(sbn<<8)|bno;
  414. pcicfgw32(p, PciPBN, l);
  415. pcicfgw16(p, PciSPSR, 0xFFFF);
  416. maxubn = pcilscan(sbn, &p->bridge);
  417. l = (maxubn<<16)|(sbn<<8)|bno;
  418. pcicfgw32(p, PciPBN, l);
  419. }
  420. else {
  421. if(ubn > maxubn)
  422. maxubn = ubn;
  423. pcilscan(sbn, &p->bridge);
  424. }
  425. }
  426. return maxubn;
  427. }
  428. int
  429. pciscan(int bno, Pcidev **list)
  430. {
  431. int ubn;
  432. lock(&pcicfginitlock);
  433. ubn = pcilscan(bno, list);
  434. unlock(&pcicfginitlock);
  435. return ubn;
  436. }
  437. static uchar
  438. pIIxget(Pcidev *router, uchar link)
  439. {
  440. uchar pirq;
  441. /* link should be 0x60, 0x61, 0x62, 0x63 */
  442. pirq = pcicfgr8(router, link);
  443. return (pirq < 16)? pirq: 0;
  444. }
  445. static void
  446. pIIxset(Pcidev *router, uchar link, uchar irq)
  447. {
  448. pcicfgw8(router, link, irq);
  449. }
  450. static uchar
  451. viaget(Pcidev *router, uchar link)
  452. {
  453. uchar pirq;
  454. /* link should be 1, 2, 3, 5 */
  455. pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
  456. return (link & 1)? (pirq >> 4): (pirq & 15);
  457. }
  458. static void
  459. viaset(Pcidev *router, uchar link, uchar irq)
  460. {
  461. uchar pirq;
  462. pirq = pcicfgr8(router, 0x55 + (link >> 1));
  463. pirq &= (link & 1)? 0x0f: 0xf0;
  464. pirq |= (link & 1)? (irq << 4): (irq & 15);
  465. pcicfgw8(router, 0x55 + (link>>1), pirq);
  466. }
  467. static uchar
  468. optiget(Pcidev *router, uchar link)
  469. {
  470. uchar pirq = 0;
  471. /* link should be 0x02, 0x12, 0x22, 0x32 */
  472. if ((link & 0xcf) == 0x02)
  473. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  474. return (link & 0x10)? (pirq >> 4): (pirq & 15);
  475. }
  476. static void
  477. optiset(Pcidev *router, uchar link, uchar irq)
  478. {
  479. uchar pirq;
  480. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  481. pirq &= (link & 0x10)? 0x0f : 0xf0;
  482. pirq |= (link & 0x10)? (irq << 4): (irq & 15);
  483. pcicfgw8(router, 0xb8 + (link >> 5), pirq);
  484. }
  485. static uchar
  486. aliget(Pcidev *router, uchar link)
  487. {
  488. /* No, you're not dreaming */
  489. static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
  490. uchar pirq;
  491. /* link should be 0x01..0x08 */
  492. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  493. return (link & 1)? map[pirq&15]: map[pirq>>4];
  494. }
  495. static void
  496. aliset(Pcidev *router, uchar link, uchar irq)
  497. {
  498. /* Inverse of map in aliget */
  499. static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
  500. uchar pirq;
  501. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  502. pirq &= (link & 1)? 0x0f: 0xf0;
  503. pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
  504. pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
  505. }
  506. static uchar
  507. cyrixget(Pcidev *router, uchar link)
  508. {
  509. uchar pirq;
  510. /* link should be 1, 2, 3, 4 */
  511. pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
  512. return ((link & 1)? pirq >> 4: pirq & 15);
  513. }
  514. static void
  515. cyrixset(Pcidev *router, uchar link, uchar irq)
  516. {
  517. uchar pirq;
  518. pirq = pcicfgr8(router, 0x5c + (link>>1));
  519. pirq &= (link & 1)? 0x0f: 0xf0;
  520. pirq |= (link & 1)? (irq << 4): (irq & 15);
  521. pcicfgw8(router, 0x5c + (link>>1), pirq);
  522. }
  523. typedef struct Bridge Bridge;
  524. struct Bridge
  525. {
  526. ushort vid;
  527. ushort did;
  528. uchar (*get)(Pcidev *, uchar);
  529. void (*set)(Pcidev *, uchar, uchar);
  530. };
  531. static Bridge southbridges[] = {
  532. { 0x8086, 0x122e, pIIxget, pIIxset }, // Intel 82371FB
  533. { 0x8086, 0x1234, pIIxget, pIIxset }, // Intel 82371MX
  534. { 0x8086, 0x7000, pIIxget, pIIxset }, // Intel 82371SB
  535. { 0x8086, 0x7110, pIIxget, pIIxset }, // Intel 82371AB
  536. { 0x8086, 0x7198, pIIxget, pIIxset }, // Intel 82443MX (fn 1)
  537. { 0x8086, 0x2410, pIIxget, pIIxset }, // Intel 82801AA
  538. { 0x8086, 0x2420, pIIxget, pIIxset }, // Intel 82801AB
  539. { 0x8086, 0x2440, pIIxget, pIIxset }, // Intel 82801BA
  540. { 0x8086, 0x244c, pIIxget, pIIxset }, // Intel 82801BAM
  541. { 0x8086, 0x248c, pIIxget, pIIxset }, // Intel 82801CAM
  542. { 0x8086, 0x24cc, pIIxget, pIIxset }, // Intel 82801DBM
  543. { 0x8086, 0x24d0, pIIxget, pIIxset }, // Intel 82801EB
  544. { 0x8086, 0x2640, pIIxget, pIIxset }, // Intel 82801FB
  545. { 0x1106, 0x0586, viaget, viaset }, // Viatech 82C586
  546. { 0x1106, 0x0596, viaget, viaset }, // Viatech 82C596
  547. { 0x1106, 0x0686, viaget, viaset }, // Viatech 82C686
  548. { 0x1106, 0x3227, viaget, viaset }, // Viatech VT8237
  549. { 0x1045, 0xc700, optiget, optiset }, // Opti 82C700
  550. { 0x10b9, 0x1533, aliget, aliset }, // Al M1533
  551. { 0x1039, 0x0008, pIIxget, pIIxset }, // SI 503
  552. { 0x1039, 0x0496, pIIxget, pIIxset }, // SI 496
  553. { 0x1078, 0x0100, cyrixget, cyrixset }, // Cyrix 5530 Legacy
  554. { 0x1022, 0x746B, nil, nil }, // AMD 8111
  555. { 0x10DE, 0x00D1, nil, nil }, // NVIDIA nForce 3
  556. { 0x1166, 0x0200, nil, nil }, // ServerWorks ServerSet III LE
  557. };
  558. typedef struct Slot Slot;
  559. struct Slot {
  560. uchar bus; // Pci bus number
  561. uchar dev; // Pci device number
  562. uchar maps[12]; // Avoid structs! Link and mask.
  563. uchar slot; // Add-in/built-in slot
  564. uchar reserved;
  565. };
  566. typedef struct Router Router;
  567. struct Router {
  568. uchar signature[4]; // Routing table signature
  569. uchar version[2]; // Version number
  570. uchar size[2]; // Total table size
  571. uchar bus; // Interrupt router bus number
  572. uchar devfn; // Router's devfunc
  573. uchar pciirqs[2]; // Exclusive PCI irqs
  574. uchar compat[4]; // Compatible PCI interrupt router
  575. uchar miniport[4]; // Miniport data
  576. uchar reserved[11];
  577. uchar checksum;
  578. };
  579. static ushort pciirqs; // Exclusive PCI irqs
  580. static Bridge *southbridge; // Which southbridge to use.
  581. static void
  582. pcirouting(void)
  583. {
  584. Slot *e;
  585. Router *r;
  586. int size, i, fn, tbdf;
  587. Pcidev *sbpci, *pci;
  588. uchar *p, pin, irq, link, *map;
  589. // Search for PCI interrupt routing table in BIOS
  590. for(p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
  591. if(p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
  592. break;
  593. if(p >= (uchar *)KADDR(0xfffff))
  594. return;
  595. r = (Router *)p;
  596. // print("PCI interrupt routing table version %d.%d at %.6uX\n",
  597. // r->version[0], r->version[1], (ulong)r & 0xfffff);
  598. tbdf = (BusPCI << 24)|(r->bus << 16)|(r->devfn << 8);
  599. sbpci = pcimatchtbdf(tbdf);
  600. if(sbpci == nil) {
  601. print("pcirouting: Cannot find south bridge %T\n", tbdf);
  602. return;
  603. }
  604. for(i = 0; i != nelem(southbridges); i++)
  605. if(sbpci->vid == southbridges[i].vid && sbpci->did == southbridges[i].did)
  606. break;
  607. if(i == nelem(southbridges)) {
  608. print("pcirouting: ignoring south bridge %T %.4uX/%.4uX\n", tbdf, sbpci->vid, sbpci->did);
  609. return;
  610. }
  611. southbridge = &southbridges[i];
  612. if(southbridge->get == nil || southbridge->set == nil)
  613. return;
  614. pciirqs = (r->pciirqs[1] << 8)|r->pciirqs[0];
  615. size = (r->size[1] << 8)|r->size[0];
  616. for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
  617. // print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
  618. // for (i = 0; i != 4; i++) {
  619. // uchar *m = &e->maps[i * 3];
  620. // print("[%d] %.2uX %.4uX ",
  621. // i, m[0], (m[2] << 8)|m[1]);
  622. // }
  623. // print("\n");
  624. for(fn = 0; fn != 8; fn++) {
  625. tbdf = (BusPCI << 24)|(e->bus << 16)|((e->dev | fn) << 8);
  626. pci = pcimatchtbdf(tbdf);
  627. if(pci == nil)
  628. continue;
  629. pin = pcicfgr8(pci, PciINTP);
  630. if(pin == 0 || pin == 0xff)
  631. continue;
  632. map = &e->maps[(pin - 1) * 3];
  633. link = map[0];
  634. irq = southbridge->get(sbpci, link);
  635. if(irq == 0 || irq == pci->intl)
  636. continue;
  637. if(pci->intl != 0 && pci->intl != 0xFF) {
  638. print("pcirouting: BIOS workaround: %T at pin %d link %d irq %d -> %d\n",
  639. tbdf, pin, link, irq, pci->intl);
  640. southbridge->set(sbpci, link, pci->intl);
  641. continue;
  642. }
  643. print("pcirouting: %T at pin %d link %d irq %d\n", tbdf, pin, link, irq);
  644. pcicfgw8(pci, PciINTL, irq);
  645. pci->intl = irq;
  646. }
  647. }
  648. }
  649. static void
  650. pcicfginit(void)
  651. {
  652. char *p;
  653. Pcidev **list;
  654. ulong mema, ioa;
  655. int bno, n, pcibios;
  656. lock(&pcicfginitlock);
  657. if(pcicfgmode != -1)
  658. goto out;
  659. pcibios = 0;
  660. if(getconf("*nobios"))
  661. nobios = 1;
  662. else if(getconf("*pcibios"))
  663. pcibios = 1;
  664. if(getconf("*nopcirouting"))
  665. nopcirouting = 1;
  666. /*
  667. * Try to determine which PCI configuration mode is implemented.
  668. * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
  669. * a DWORD at 0xCF8 and another at 0xCFC and will pass through
  670. * any non-DWORD accesses as normal I/O cycles. There shouldn't be
  671. * a device behind these addresses so if Mode1 accesses fail try
  672. * for Mode2 (Mode2 is deprecated).
  673. */
  674. if(!pcibios){
  675. /*
  676. * Bits [30:24] of PciADDR must be 0,
  677. * according to the spec.
  678. */
  679. n = inl(PciADDR);
  680. if(!(n & 0x7FF00000)){
  681. outl(PciADDR, 0x80000000);
  682. outb(PciADDR+3, 0);
  683. if(inl(PciADDR) & 0x80000000){
  684. pcicfgmode = 1;
  685. pcimaxdno = 31;
  686. }
  687. }
  688. outl(PciADDR, n);
  689. if(pcicfgmode < 0){
  690. /*
  691. * The 'key' part of PciCSE should be 0.
  692. */
  693. n = inb(PciCSE);
  694. if(!(n & 0xF0)){
  695. outb(PciCSE, 0x0E);
  696. if(inb(PciCSE) == 0x0E){
  697. pcicfgmode = 2;
  698. pcimaxdno = 15;
  699. }
  700. }
  701. outb(PciCSE, n);
  702. }
  703. }
  704. if(pcicfgmode < 0)
  705. goto out;
  706. fmtinstall('T', tbdffmt);
  707. if(p = getconf("*pcimaxbno")){
  708. n = strtoul(p, 0, 0);
  709. if(n < pcimaxbno)
  710. pcimaxbno = n;
  711. }
  712. if(p = getconf("*pcimaxdno")){
  713. n = strtoul(p, 0, 0);
  714. if(n < pcimaxdno)
  715. pcimaxdno = n;
  716. }
  717. list = &pciroot;
  718. for(bno = 0; bno <= pcimaxbno; bno++) {
  719. int sbno = bno;
  720. bno = pcilscan(bno, list);
  721. while(*list)
  722. list = &(*list)->link;
  723. if (sbno == 0) {
  724. Pcidev *pci;
  725. /*
  726. * If we have found a PCI-to-Cardbus bridge, make sure
  727. * it has no valid mappings anymore.
  728. */
  729. pci = pciroot;
  730. while (pci) {
  731. if (pci->ccrb == 6 && pci->ccru == 7) {
  732. ushort bcr;
  733. /* reset the cardbus */
  734. bcr = pcicfgr16(pci, PciBCR);
  735. pcicfgw16(pci, PciBCR, 0x40 | bcr);
  736. delay(50);
  737. }
  738. pci = pci->link;
  739. }
  740. }
  741. }
  742. if(pciroot == nil)
  743. goto out;
  744. if(nobios) {
  745. /*
  746. * Work out how big the top bus is
  747. */
  748. mema = 0;
  749. ioa = 0;
  750. pcibusmap(pciroot, &mema, &ioa, 0);
  751. DBG("Sizes: mem=%8.8lux size=%8.8lux io=%8.8lux\n",
  752. mema, pcimask(mema), ioa);
  753. /*
  754. * Align the windows and map it
  755. */
  756. ioa = 0x1000;
  757. mema = 0x90000000;
  758. pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
  759. pcibusmap(pciroot, &mema, &ioa, 1);
  760. DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
  761. unlock(&pcicfginitlock);
  762. return;
  763. }
  764. if (!nopcirouting)
  765. pcirouting();
  766. out:
  767. unlock(&pcicfginitlock);
  768. if(getconf("*pcihinv"))
  769. pcihinv(nil);
  770. }
  771. static int
  772. pcicfgrw8(int tbdf, int rno, int data, int read)
  773. {
  774. int o, type, x;
  775. if(pcicfgmode == -1)
  776. pcicfginit();
  777. if(BUSBNO(tbdf))
  778. type = 0x01;
  779. else
  780. type = 0x00;
  781. x = -1;
  782. if(BUSDNO(tbdf) > pcimaxdno)
  783. return x;
  784. lock(&pcicfglock);
  785. switch(pcicfgmode){
  786. case 1:
  787. o = rno & 0x03;
  788. rno &= ~0x03;
  789. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  790. if(read)
  791. x = inb(PciDATA+o);
  792. else
  793. outb(PciDATA+o, data);
  794. outl(PciADDR, 0);
  795. break;
  796. case 2:
  797. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  798. outb(PciFORWARD, BUSBNO(tbdf));
  799. if(read)
  800. x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  801. else
  802. outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  803. outb(PciCSE, 0);
  804. break;
  805. }
  806. unlock(&pcicfglock);
  807. return x;
  808. }
  809. int
  810. pcicfgr8(Pcidev* pcidev, int rno)
  811. {
  812. return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
  813. }
  814. void
  815. pcicfgw8(Pcidev* pcidev, int rno, int data)
  816. {
  817. pcicfgrw8(pcidev->tbdf, rno, data, 0);
  818. }
  819. static int
  820. pcicfgrw16(int tbdf, int rno, int data, int read)
  821. {
  822. int o, type, x;
  823. if(pcicfgmode == -1)
  824. pcicfginit();
  825. if(BUSBNO(tbdf))
  826. type = 0x01;
  827. else
  828. type = 0x00;
  829. x = -1;
  830. if(BUSDNO(tbdf) > pcimaxdno)
  831. return x;
  832. lock(&pcicfglock);
  833. switch(pcicfgmode){
  834. case 1:
  835. o = rno & 0x02;
  836. rno &= ~0x03;
  837. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  838. if(read)
  839. x = ins(PciDATA+o);
  840. else
  841. outs(PciDATA+o, data);
  842. outl(PciADDR, 0);
  843. break;
  844. case 2:
  845. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  846. outb(PciFORWARD, BUSBNO(tbdf));
  847. if(read)
  848. x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  849. else
  850. outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  851. outb(PciCSE, 0);
  852. break;
  853. }
  854. unlock(&pcicfglock);
  855. return x;
  856. }
  857. int
  858. pcicfgr16(Pcidev* pcidev, int rno)
  859. {
  860. return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
  861. }
  862. void
  863. pcicfgw16(Pcidev* pcidev, int rno, int data)
  864. {
  865. pcicfgrw16(pcidev->tbdf, rno, data, 0);
  866. }
  867. static int
  868. pcicfgrw32(int tbdf, int rno, int data, int read)
  869. {
  870. int type, x;
  871. if(pcicfgmode == -1)
  872. pcicfginit();
  873. if(BUSBNO(tbdf))
  874. type = 0x01;
  875. else
  876. type = 0x00;
  877. x = -1;
  878. if(BUSDNO(tbdf) > pcimaxdno)
  879. return x;
  880. lock(&pcicfglock);
  881. switch(pcicfgmode){
  882. case 1:
  883. rno &= ~0x03;
  884. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  885. if(read)
  886. x = inl(PciDATA);
  887. else
  888. outl(PciDATA, data);
  889. outl(PciADDR, 0);
  890. break;
  891. case 2:
  892. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  893. outb(PciFORWARD, BUSBNO(tbdf));
  894. if(read)
  895. x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  896. else
  897. outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  898. outb(PciCSE, 0);
  899. break;
  900. }
  901. unlock(&pcicfglock);
  902. return x;
  903. }
  904. int
  905. pcicfgr32(Pcidev* pcidev, int rno)
  906. {
  907. return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
  908. }
  909. void
  910. pcicfgw32(Pcidev* pcidev, int rno, int data)
  911. {
  912. pcicfgrw32(pcidev->tbdf, rno, data, 0);
  913. }
  914. Pcidev*
  915. pcimatch(Pcidev* prev, int vid, int did)
  916. {
  917. if(pcicfgmode == -1)
  918. pcicfginit();
  919. if(prev == nil)
  920. prev = pcilist;
  921. else
  922. prev = prev->list;
  923. while(prev != nil){
  924. if((vid == 0 || prev->vid == vid)
  925. && (did == 0 || prev->did == did))
  926. break;
  927. prev = prev->list;
  928. }
  929. return prev;
  930. }
  931. Pcidev*
  932. pcimatchtbdf(int tbdf)
  933. {
  934. Pcidev *pcidev;
  935. if(pcicfgmode == -1)
  936. pcicfginit();
  937. for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
  938. if(pcidev->tbdf == tbdf)
  939. break;
  940. }
  941. return pcidev;
  942. }
  943. uchar
  944. pciipin(Pcidev *pci, uchar pin)
  945. {
  946. if (pci == nil)
  947. pci = pcilist;
  948. while (pci) {
  949. uchar intl;
  950. if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
  951. return pci->intl;
  952. if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
  953. return intl;
  954. pci = pci->list;
  955. }
  956. return 0;
  957. }
  958. static void
  959. pcilhinv(Pcidev* p)
  960. {
  961. int i;
  962. Pcidev *t;
  963. if(p == nil) {
  964. putstrn(PCICONS.output, PCICONS.ptr);
  965. p = pciroot;
  966. print("bus dev type vid did intl memory\n");
  967. }
  968. for(t = p; t != nil; t = t->link) {
  969. print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
  970. BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
  971. t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
  972. for(i = 0; i < nelem(p->mem); i++) {
  973. if(t->mem[i].size == 0)
  974. continue;
  975. print("%d:%.8lux %d ", i,
  976. t->mem[i].bar, t->mem[i].size);
  977. }
  978. if(t->ioa.bar || t->ioa.size)
  979. print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
  980. if(t->mema.bar || t->mema.size)
  981. print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
  982. if(t->bridge)
  983. print("->%d", BUSBNO(t->bridge->tbdf));
  984. print("\n");
  985. }
  986. while(p != nil) {
  987. if(p->bridge != nil)
  988. pcilhinv(p->bridge);
  989. p = p->link;
  990. }
  991. }
  992. void
  993. pcihinv(Pcidev* p)
  994. {
  995. if(pcicfgmode == -1)
  996. pcicfginit();
  997. lock(&pcicfginitlock);
  998. pcilhinv(p);
  999. unlock(&pcicfginitlock);
  1000. }
  1001. void
  1002. pcireset(void)
  1003. {
  1004. Pcidev *p;
  1005. if(pcicfgmode == -1)
  1006. pcicfginit();
  1007. for(p = pcilist; p != nil; p = p->list) {
  1008. /* don't mess with the bridges */
  1009. if(p->ccrb == 0x06)
  1010. continue;
  1011. pciclrbme(p);
  1012. }
  1013. }
  1014. void
  1015. pcisetioe(Pcidev* p)
  1016. {
  1017. p->pcr |= IOen;
  1018. pcicfgw16(p, PciPCR, p->pcr);
  1019. }
  1020. void
  1021. pciclrioe(Pcidev* p)
  1022. {
  1023. p->pcr &= ~IOen;
  1024. pcicfgw16(p, PciPCR, p->pcr);
  1025. }
  1026. void
  1027. pcisetbme(Pcidev* p)
  1028. {
  1029. p->pcr |= MASen;
  1030. pcicfgw16(p, PciPCR, p->pcr);
  1031. }
  1032. void
  1033. pciclrbme(Pcidev* p)
  1034. {
  1035. p->pcr &= ~MASen;
  1036. pcicfgw16(p, PciPCR, p->pcr);
  1037. }
  1038. void
  1039. pcisetmwi(Pcidev* p)
  1040. {
  1041. p->pcr |= MemWrInv;
  1042. pcicfgw16(p, PciPCR, p->pcr);
  1043. }
  1044. void
  1045. pciclrmwi(Pcidev* p)
  1046. {
  1047. p->pcr &= ~MemWrInv;
  1048. pcicfgw16(p, PciPCR, p->pcr);
  1049. }
  1050. static int
  1051. pcigetpmrb(Pcidev* p)
  1052. {
  1053. int ptr;
  1054. if(p->pmrb != 0)
  1055. return p->pmrb;
  1056. p->pmrb = -1;
  1057. /*
  1058. * If there are no extended capabilities implemented,
  1059. * (bit 4 in the status register) assume there's no standard
  1060. * power management method.
  1061. * Find the capabilities pointer based on PCI header type.
  1062. */
  1063. if(!(p->pcr & 0x0010))
  1064. return -1;
  1065. switch(pcicfgr8(p, PciHDT)){
  1066. default:
  1067. return -1;
  1068. case 0: /* all other */
  1069. case 1: /* PCI to PCI bridge */
  1070. ptr = 0x34;
  1071. break;
  1072. case 2: /* CardBus bridge */
  1073. ptr = 0x14;
  1074. break;
  1075. }
  1076. ptr = pcicfgr32(p, ptr);
  1077. while(ptr != 0){
  1078. /*
  1079. * Check for validity.
  1080. * Can't be in standard header and must be double
  1081. * word aligned.
  1082. */
  1083. if(ptr < 0x40 || (ptr & ~0xFC))
  1084. return -1;
  1085. if(pcicfgr8(p, ptr) == 0x01){
  1086. p->pmrb = ptr;
  1087. return ptr;
  1088. }
  1089. ptr = pcicfgr8(p, ptr+1);
  1090. }
  1091. return -1;
  1092. }
  1093. int
  1094. pcigetpms(Pcidev* p)
  1095. {
  1096. int pmcsr, ptr;
  1097. if((ptr = pcigetpmrb(p)) == -1)
  1098. return -1;
  1099. /*
  1100. * Power Management Register Block:
  1101. * offset 0: Capability ID
  1102. * 1: next item pointer
  1103. * 2: capabilities
  1104. * 4: control/status
  1105. * 6: bridge support extensions
  1106. * 7: data
  1107. */
  1108. pmcsr = pcicfgr16(p, ptr+4);
  1109. return pmcsr & 0x0003;
  1110. }
  1111. int
  1112. pcisetpms(Pcidev* p, int state)
  1113. {
  1114. int ostate, pmc, pmcsr, ptr;
  1115. if((ptr = pcigetpmrb(p)) == -1)
  1116. return -1;
  1117. pmc = pcicfgr16(p, ptr+2);
  1118. pmcsr = pcicfgr16(p, ptr+4);
  1119. ostate = pmcsr & 0x0003;
  1120. pmcsr &= ~0x0003;
  1121. switch(state){
  1122. default:
  1123. return -1;
  1124. case 0:
  1125. break;
  1126. case 1:
  1127. if(!(pmc & 0x0200))
  1128. return -1;
  1129. break;
  1130. case 2:
  1131. if(!(pmc & 0x0400))
  1132. return -1;
  1133. break;
  1134. case 3:
  1135. break;
  1136. }
  1137. pmcsr |= state;
  1138. pcicfgw16(p, ptr+4, pmcsr);
  1139. return ostate;
  1140. }