l.s 28 KB

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  1. #include "mem.h"
  2. #include "/sys/src/boot/pc/x16.h"
  3. #undef DELAY
  4. #define PADDR(a) ((a) & ~KZERO)
  5. #define KADDR(a) (KZERO|(a))
  6. /*
  7. * Some machine instructions not handled by 8[al].
  8. */
  9. #define OP16 BYTE $0x66
  10. #define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
  11. #define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
  12. #define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
  13. #define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
  14. #define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) */
  15. #define HLT BYTE $0xF4
  16. #define INVLPG BYTE $0x0F; BYTE $0x01; BYTE $0x39 /* INVLPG (%ecx) */
  17. /*
  18. * Macros for calculating offsets within the page directory base
  19. * and page tables. Note that these are assembler-specific hence
  20. * the '<<2'.
  21. */
  22. #define PDO(a) (((((a))>>22) & 0x03FF)<<2)
  23. #define PTO(a) (((((a))>>12) & 0x03FF)<<2)
  24. /*
  25. * For backwards compatiblity with 9load - should go away when 9load is changed
  26. * 9load currently sets up the mmu, however the first 16MB of memory is identity
  27. * mapped, so behave as if the mmu was not setup
  28. */
  29. TEXT _startKADDR(SB), $0
  30. MOVL $_startPADDR(SB), AX
  31. ANDL $~KZERO, AX
  32. JMP* AX
  33. /*
  34. * Must be 4-byte aligned.
  35. */
  36. TEXT _multibootheader(SB), $0
  37. LONG $0x1BADB002 /* magic */
  38. LONG $0x00010003 /* flags */
  39. LONG $-(0x1BADB002 + 0x00010003) /* checksum */
  40. LONG $_multibootheader-KZERO(SB) /* header_addr */
  41. LONG $_startKADDR-KZERO(SB) /* load_addr */
  42. LONG $edata-KZERO(SB) /* load_end_addr */
  43. LONG $end-KZERO(SB) /* bss_end_addr */
  44. LONG $_startKADDR-KZERO(SB) /* entry_addr */
  45. LONG $0 /* mode_type */
  46. LONG $0 /* width */
  47. LONG $0 /* height */
  48. LONG $0 /* depth */
  49. /*
  50. * In protected mode with paging turned off and segment registers setup to linear map all memory.
  51. * Entered via a jump to PADDR(entry), the physical address of the virtual kernel entry point of KADDR(entry)
  52. * Make the basic page tables for processor 0. Four pages are needed for the basic set:
  53. * a page directory, a page table for mapping the first 4MB of physical memory to KZERO,
  54. * and virtual and physical pages for mapping the Mach structure.
  55. * The remaining PTEs will be allocated later when memory is sized.
  56. * An identity mmu map is also needed for the switch to virtual mode. This
  57. * identity mapping is removed once the MMU is going and the JMP has been made
  58. * to virtual memory.
  59. */
  60. TEXT _startPADDR(SB), $0
  61. CLI /* make sure interrupts are off */
  62. /* set up the gdt so we have sane plan 9 style gdts. */
  63. MOVL $tgdtptr(SB), AX
  64. ANDL $~KZERO, AX
  65. MOVL (AX), GDTR
  66. MOVW $1, AX
  67. MOVW AX, MSW
  68. /* clear prefetch queue (weird code to avoid optimizations) */
  69. DELAY
  70. /* set segs to something sane (avoid traps later) */
  71. MOVW $(1<<3), AX
  72. MOVW AX, DS
  73. MOVW AX, SS
  74. MOVW AX, ES
  75. MOVW AX, FS
  76. MOVW AX, GS
  77. /* JMP $(2<<3):$mode32bit(SB) /**/
  78. BYTE $0xEA
  79. LONG $mode32bit-KZERO(SB)
  80. WORD $(2<<3)
  81. /*
  82. * gdt to get us to 32-bit/segmented/unpaged mode
  83. */
  84. TEXT tgdt(SB), $0
  85. /* null descriptor */
  86. LONG $0
  87. LONG $0
  88. /* data segment descriptor for 4 gigabytes (PL 0) */
  89. LONG $(0xFFFF)
  90. LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
  91. /* exec segment descriptor for 4 gigabytes (PL 0) */
  92. LONG $(0xFFFF)
  93. LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
  94. /*
  95. * pointer to initial gdt
  96. * Note the -KZERO which puts the physical address in the gdtptr.
  97. * that's needed as we start executing in physical addresses.
  98. */
  99. TEXT tgdtptr(SB), $0
  100. WORD $(3*8)
  101. LONG $tgdt-KZERO(SB)
  102. TEXT m0rgdtptr(SB), $0
  103. WORD $(NGDT*8-1)
  104. LONG $(CPU0GDT-KZERO)
  105. TEXT m0gdtptr(SB), $0
  106. WORD $(NGDT*8-1)
  107. LONG $CPU0GDT
  108. TEXT m0idtptr(SB), $0
  109. WORD $(256*8-1)
  110. LONG $IDTADDR
  111. TEXT mode32bit(SB), $0
  112. /* At this point, the GDT setup is done. */
  113. MOVL $PADDR(CPU0PDB), DI /* clear 4 pages for the tables etc. */
  114. XORL AX, AX
  115. MOVL $(4*BY2PG), CX
  116. SHRL $2, CX
  117. CLD
  118. REP; STOSL
  119. MOVL $PADDR(CPU0PDB), AX
  120. ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
  121. MOVL $PADDR(CPU0PTE), (AX) /* PTE's for KZERO */
  122. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  123. ORL BX, (AX)
  124. MOVL $PADDR(CPU0PTE), AX /* first page of page table */
  125. MOVL $1024, CX /* 1024 pages in 4MB */
  126. _setpte:
  127. MOVL BX, (AX)
  128. ADDL $(1<<PGSHIFT), BX
  129. ADDL $4, AX
  130. LOOP _setpte
  131. MOVL $PADDR(CPU0PTE), AX
  132. ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
  133. MOVL $PADDR(CPU0MACH), (AX) /* PTE for Mach */
  134. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  135. ORL BX, (AX)
  136. /*
  137. * Now ready to use the new map. Make sure the processor options are what is wanted.
  138. * It is necessary on some processors to immediately follow mode switching with a JMP instruction
  139. * to clear the prefetch queues.
  140. */
  141. MOVL $PADDR(CPU0PDB), CX /* load address of page directory */
  142. MOVL (PDO(KZERO))(CX), DX /* double-map KZERO at 0 */
  143. MOVL DX, (PDO(0))(CX)
  144. MOVL CX, CR3
  145. DELAY /* JMP .+2 */
  146. MOVL CR0, DX
  147. ORL $0x80010000, DX /* PG|WP */
  148. ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
  149. MOVL $_startpg(SB), AX /* this is a virtual address */
  150. MOVL DX, CR0 /* turn on paging */
  151. JMP* AX /* jump to the virtual nirvana */
  152. /*
  153. * Basic machine environment set, can clear BSS and create a stack.
  154. * The stack starts at the top of the page containing the Mach structure.
  155. * The x86 architecture forces the use of the same virtual address for
  156. * each processor's Mach structure, so the global Mach pointer 'm' can
  157. * be initialised here.
  158. */
  159. TEXT _startpg(SB), $0
  160. MOVL $0, (PDO(0))(CX) /* undo double-map of KZERO at 0 */
  161. MOVL CX, CR3 /* load and flush the mmu */
  162. _clearbss:
  163. MOVL $edata(SB), DI
  164. XORL AX, AX
  165. MOVL $end(SB), CX
  166. SUBL DI, CX /* end-edata bytes */
  167. SHRL $2, CX /* end-edata doublewords */
  168. CLD
  169. REP; STOSL /* clear BSS */
  170. MOVL $MACHADDR, SP
  171. MOVL SP, m(SB) /* initialise global Mach pointer */
  172. MOVL $0, 0(SP) /* initialise m->machno */
  173. ADDL $(MACHSIZE-4), SP /* initialise stack */
  174. /*
  175. * Need to do one final thing to ensure a clean machine environment,
  176. * clear the EFLAGS register, which can only be done once there is a stack.
  177. */
  178. MOVL $0, AX
  179. PUSHL AX
  180. POPFL
  181. CALL main(SB)
  182. /*
  183. * Park a processor. Should never fall through a return from main to here,
  184. * should only be called by application processors when shutting down.
  185. */
  186. TEXT idle(SB), $0
  187. _idle:
  188. STI
  189. HLT
  190. JMP _idle
  191. /*
  192. * Save registers.
  193. */
  194. TEXT saveregs(SB), $0
  195. /* appease 8l */
  196. SUBL $32, SP
  197. POPL AX
  198. POPL AX
  199. POPL AX
  200. POPL AX
  201. POPL AX
  202. POPL AX
  203. POPL AX
  204. POPL AX
  205. PUSHL AX
  206. PUSHL BX
  207. PUSHL CX
  208. PUSHL DX
  209. PUSHL BP
  210. PUSHL DI
  211. PUSHL SI
  212. PUSHFL
  213. XCHGL 32(SP), AX /* swap return PC and saved flags */
  214. XCHGL 0(SP), AX
  215. XCHGL 32(SP), AX
  216. RET
  217. TEXT restoreregs(SB), $0
  218. /* appease 8l */
  219. PUSHL AX
  220. PUSHL AX
  221. PUSHL AX
  222. PUSHL AX
  223. PUSHL AX
  224. PUSHL AX
  225. PUSHL AX
  226. PUSHL AX
  227. ADDL $32, SP
  228. XCHGL 32(SP), AX /* swap return PC and saved flags */
  229. XCHGL 0(SP), AX
  230. XCHGL 32(SP), AX
  231. POPFL
  232. POPL SI
  233. POPL DI
  234. POPL BP
  235. POPL DX
  236. POPL CX
  237. POPL BX
  238. POPL AX
  239. RET
  240. /*
  241. * Assumed to be in protected mode at time of call.
  242. * Switch to real mode, execute an interrupt, and
  243. * then switch back to protected mode.
  244. *
  245. * Assumes:
  246. *
  247. * - no device interrupts are going to come in
  248. * - 0-16MB is identity mapped in page tables
  249. * - realmode() has copied us down from 0x100000 to 0x8000
  250. * - can use code segment 0x0800 in real mode
  251. * to get at l.s code
  252. * - l.s code is less than 1 page
  253. */
  254. #define RELOC (RMCODE-KTZERO)
  255. TEXT realmodeidtptr(SB), $0
  256. WORD $(4*256-1)
  257. LONG $0
  258. TEXT realmode0(SB), $0
  259. CALL saveregs(SB)
  260. /* switch to low code address */
  261. LEAL physcode-KZERO(SB), AX
  262. JMP *AX
  263. TEXT physcode(SB), $0
  264. /* switch to low stack */
  265. MOVL SP, AX
  266. MOVL $0x7C00, SP
  267. PUSHL AX
  268. /* change gdt to physical pointer */
  269. MOVL m0rgdtptr-KZERO(SB), GDTR
  270. /* load IDT with real-mode version*/
  271. MOVL realmodeidtptr-KZERO(SB), IDTR
  272. /* edit INT $0x00 instruction below */
  273. MOVL $(RMUADDR-KZERO+48), AX /* &rmu.trap */
  274. MOVL (AX), AX
  275. MOVB AX, realmodeintrinst+(-KZERO+1+RELOC)(SB)
  276. /* disable paging */
  277. MOVL CR0, AX
  278. ANDL $0x7FFFFFFF, AX
  279. MOVL AX, CR0
  280. /* JMP .+2 to clear prefetch queue*/
  281. BYTE $0xEB; BYTE $0x00
  282. /* jump to 16-bit code segment */
  283. /* JMPFAR SELECTOR(KESEG16, SELGDT, 0):$again16bit(SB) /**/
  284. BYTE $0xEA
  285. LONG $again16bit-KZERO(SB)
  286. WORD $SELECTOR(KESEG16, SELGDT, 0)
  287. TEXT again16bit(SB), $0
  288. /*
  289. * Now in 16-bit compatibility mode.
  290. * These are 32-bit instructions being interpreted
  291. * as 16-bit instructions. I'm being lazy and
  292. * not using the macros because I know when
  293. * the 16- and 32-bit instructions look the same
  294. * or close enough.
  295. */
  296. /* disable protected mode and jump to real mode cs */
  297. OPSIZE; MOVL CR0, AX
  298. OPSIZE; XORL BX, BX
  299. OPSIZE; INCL BX
  300. OPSIZE; XORL BX, AX
  301. OPSIZE; MOVL AX, CR0
  302. /* JMPFAR 0x0800:now16real */
  303. BYTE $0xEA
  304. WORD $now16real-KZERO(SB)
  305. WORD $0x0800
  306. TEXT now16real(SB), $0
  307. /* copy the registers for the bios call */
  308. LWI(0x0000, rAX)
  309. MOVW AX,SS
  310. LWI(RMUADDR, rBP)
  311. /* offsets are in Ureg */
  312. LXW(44, xBP, rAX)
  313. MOVW AX, DS
  314. LXW(40, xBP, rAX)
  315. MOVW AX, ES
  316. OPSIZE; LXW(0, xBP, rDI)
  317. OPSIZE; LXW(4, xBP, rSI)
  318. OPSIZE; LXW(16, xBP, rBX)
  319. OPSIZE; LXW(20, xBP, rDX)
  320. OPSIZE; LXW(24, xBP, rCX)
  321. OPSIZE; LXW(28, xBP, rAX)
  322. CLC
  323. TEXT realmodeintrinst(SB), $0
  324. INT $0x00
  325. /* save the registers after the call */
  326. LWI(0x7bfc, rSP)
  327. OPSIZE; PUSHFL
  328. OPSIZE; PUSHL AX
  329. LWI(0, rAX)
  330. MOVW AX,SS
  331. LWI(RMUADDR, rBP)
  332. OPSIZE; SXW(rDI, 0, xBP)
  333. OPSIZE; SXW(rSI, 4, xBP)
  334. OPSIZE; SXW(rBX, 16, xBP)
  335. OPSIZE; SXW(rDX, 20, xBP)
  336. OPSIZE; SXW(rCX, 24, xBP)
  337. OPSIZE; POPL AX
  338. OPSIZE; SXW(rAX, 28, xBP)
  339. MOVW DS, AX
  340. OPSIZE; SXW(rAX, 44, xBP)
  341. MOVW ES, AX
  342. OPSIZE; SXW(rAX, 40, xBP)
  343. OPSIZE; POPL AX
  344. OPSIZE; SXW(rAX, 64, xBP) /* flags */
  345. /* re-enter protected mode and jump to 32-bit code */
  346. OPSIZE; MOVL $1, AX
  347. OPSIZE; MOVL AX, CR0
  348. /* JMPFAR SELECTOR(KESEG, SELGDT, 0):$again32bit(SB) /**/
  349. OPSIZE
  350. BYTE $0xEA
  351. LONG $again32bit-KZERO(SB)
  352. WORD $SELECTOR(KESEG, SELGDT, 0)
  353. TEXT again32bit(SB), $0
  354. MOVW $SELECTOR(KDSEG, SELGDT, 0),AX
  355. MOVW AX,DS
  356. MOVW AX,SS
  357. MOVW AX,ES
  358. MOVW AX,FS
  359. MOVW AX,GS
  360. /* enable paging and jump to kzero-address code */
  361. MOVL CR0, AX
  362. ORL $0x80000000, AX
  363. MOVL AX, CR0
  364. LEAL again32kzero(SB), AX
  365. JMP* AX
  366. TEXT again32kzero(SB), $0
  367. /* breathe a sigh of relief - back in 32-bit protected mode */
  368. /* switch to old stack */
  369. PUSHL AX /* match popl below for 8l */
  370. MOVL $0x7BFC, SP
  371. POPL SP
  372. /* restore idt */
  373. MOVL m0idtptr(SB),IDTR
  374. /* restore gdt */
  375. MOVL m0gdtptr(SB), GDTR
  376. CALL restoreregs(SB)
  377. RET
  378. /*
  379. /*
  380. * Port I/O.
  381. * in[bsl] input a byte|short|long
  382. * ins[bsl] input a string of bytes|shorts|longs
  383. * out[bsl] output a byte|short|long
  384. * outs[bsl] output a string of bytes|shorts|longs
  385. */
  386. TEXT inb(SB), $0
  387. MOVL port+0(FP), DX
  388. XORL AX, AX
  389. INB
  390. RET
  391. TEXT insb(SB), $0
  392. MOVL port+0(FP), DX
  393. MOVL address+4(FP), DI
  394. MOVL count+8(FP), CX
  395. CLD
  396. REP; INSB
  397. RET
  398. TEXT ins(SB), $0
  399. MOVL port+0(FP), DX
  400. XORL AX, AX
  401. OP16; INL
  402. RET
  403. TEXT inss(SB), $0
  404. MOVL port+0(FP), DX
  405. MOVL address+4(FP), DI
  406. MOVL count+8(FP), CX
  407. CLD
  408. REP; OP16; INSL
  409. RET
  410. TEXT inl(SB), $0
  411. MOVL port+0(FP), DX
  412. INL
  413. RET
  414. TEXT insl(SB), $0
  415. MOVL port+0(FP), DX
  416. MOVL address+4(FP), DI
  417. MOVL count+8(FP), CX
  418. CLD
  419. REP; INSL
  420. RET
  421. TEXT outb(SB), $0
  422. MOVL port+0(FP), DX
  423. MOVL byte+4(FP), AX
  424. OUTB
  425. RET
  426. TEXT outsb(SB), $0
  427. MOVL port+0(FP), DX
  428. MOVL address+4(FP), SI
  429. MOVL count+8(FP), CX
  430. CLD
  431. REP; OUTSB
  432. RET
  433. TEXT outs(SB), $0
  434. MOVL port+0(FP), DX
  435. MOVL short+4(FP), AX
  436. OP16; OUTL
  437. RET
  438. TEXT outss(SB), $0
  439. MOVL port+0(FP), DX
  440. MOVL address+4(FP), SI
  441. MOVL count+8(FP), CX
  442. CLD
  443. REP; OP16; OUTSL
  444. RET
  445. TEXT outl(SB), $0
  446. MOVL port+0(FP), DX
  447. MOVL long+4(FP), AX
  448. OUTL
  449. RET
  450. TEXT outsl(SB), $0
  451. MOVL port+0(FP), DX
  452. MOVL address+4(FP), SI
  453. MOVL count+8(FP), CX
  454. CLD
  455. REP; OUTSL
  456. RET
  457. /*
  458. * Read/write various system registers.
  459. * CR4 and the 'model specific registers' should only be read/written
  460. * after it has been determined the processor supports them
  461. */
  462. TEXT lgdt(SB), $0 /* GDTR - global descriptor table */
  463. MOVL gdtptr+0(FP), AX
  464. MOVL (AX), GDTR
  465. RET
  466. TEXT lidt(SB), $0 /* IDTR - interrupt descriptor table */
  467. MOVL idtptr+0(FP), AX
  468. MOVL (AX), IDTR
  469. RET
  470. TEXT ltr(SB), $0 /* TR - task register */
  471. MOVL tptr+0(FP), AX
  472. MOVW AX, TASK
  473. RET
  474. TEXT getcr0(SB), $0 /* CR0 - processor control */
  475. MOVL CR0, AX
  476. RET
  477. TEXT getcr2(SB), $0 /* CR2 - page fault linear address */
  478. MOVL CR2, AX
  479. RET
  480. TEXT getcr3(SB), $0 /* CR3 - page directory base */
  481. MOVL CR3, AX
  482. RET
  483. TEXT putcr3(SB), $0
  484. MOVL cr3+0(FP), AX
  485. MOVL AX, CR3
  486. RET
  487. TEXT getcr4(SB), $0 /* CR4 - extensions */
  488. MOVL CR4, AX
  489. RET
  490. TEXT putcr4(SB), $0
  491. MOVL cr4+0(FP), AX
  492. MOVL AX, CR4
  493. RET
  494. TEXT invlpg(SB), $0
  495. /* 486+ only */
  496. MOVL va+0(FP), CX
  497. INVLPG
  498. RET
  499. TEXT _cycles(SB), $0 /* time stamp counter */
  500. RDTSC
  501. MOVL vlong+0(FP), CX /* &vlong */
  502. MOVL AX, 0(CX) /* lo */
  503. MOVL DX, 4(CX) /* hi */
  504. RET
  505. TEXT rdmsr(SB), $0 /* model-specific register */
  506. MOVL index+0(FP), CX
  507. RDMSR
  508. MOVL vlong+4(FP), CX /* &vlong */
  509. MOVL AX, 0(CX) /* lo */
  510. MOVL DX, 4(CX) /* hi */
  511. RET
  512. TEXT wrmsr(SB), $0
  513. MOVL index+0(FP), CX
  514. MOVL lo+4(FP), AX
  515. MOVL hi+8(FP), DX
  516. WRMSR
  517. RET
  518. /*
  519. * Try to determine the CPU type which requires fiddling with EFLAGS.
  520. * If the Id bit can be toggled then the CPUID instruction can be used
  521. * to determine CPU identity and features. First have to check if it's
  522. * a 386 (Ac bit can't be set). If it's not a 386 and the Id bit can't be
  523. * toggled then it's an older 486 of some kind.
  524. *
  525. * cpuid(id[], &ax, &dx);
  526. */
  527. TEXT cpuid(SB), $0
  528. MOVL $0x240000, AX
  529. PUSHL AX
  530. POPFL /* set Id|Ac */
  531. PUSHFL
  532. POPL BX /* retrieve value */
  533. MOVL $0, AX
  534. PUSHL AX
  535. POPFL /* clear Id|Ac, EFLAGS initialised */
  536. PUSHFL
  537. POPL AX /* retrieve value */
  538. XORL BX, AX
  539. TESTL $0x040000, AX /* Ac */
  540. JZ _cpu386 /* can't set this bit on 386 */
  541. TESTL $0x200000, AX /* Id */
  542. JZ _cpu486 /* can't toggle this bit on some 486 */
  543. MOVL $0, AX
  544. CPUID
  545. MOVL id+0(FP), BP
  546. MOVL BX, 0(BP) /* "Genu" "Auth" "Cyri" */
  547. MOVL DX, 4(BP) /* "ineI" "enti" "xIns" */
  548. MOVL CX, 8(BP) /* "ntel" "cAMD" "tead" */
  549. MOVL $1, AX
  550. CPUID
  551. JMP _cpuid
  552. _cpu486:
  553. MOVL $0x400, AX
  554. MOVL $0, DX
  555. JMP _cpuid
  556. _cpu386:
  557. MOVL $0x300, AX
  558. MOVL $0, DX
  559. _cpuid:
  560. MOVL ax+4(FP), BP
  561. MOVL AX, 0(BP)
  562. MOVL dx+8(FP), BP
  563. MOVL DX, 0(BP)
  564. RET
  565. /*
  566. * Basic timing loop to determine CPU frequency.
  567. */
  568. TEXT aamloop(SB), $0
  569. MOVL count+0(FP), CX
  570. _aamloop:
  571. AAM
  572. LOOP _aamloop
  573. RET
  574. /*
  575. * Floating point.
  576. * Note: the encodings for the FCLEX, FINIT, FSAVE, FSTCW, FSENV and FSTSW
  577. * instructions do NOT have the WAIT prefix byte (i.e. they act like their
  578. * FNxxx variations) so WAIT instructions must be explicitly placed in the
  579. * code as necessary.
  580. */
  581. #define FPOFF(l) ;\
  582. MOVL CR0, AX ;\
  583. ANDL $0xC, AX /* EM, TS */ ;\
  584. CMPL AX, $0x8 ;\
  585. JEQ l ;\
  586. WAIT ;\
  587. l: ;\
  588. MOVL CR0, AX ;\
  589. ANDL $~0x4, AX /* EM=0 */ ;\
  590. ORL $0x28, AX /* NE=1, TS=1 */ ;\
  591. MOVL AX, CR0
  592. #define FPON ;\
  593. MOVL CR0, AX ;\
  594. ANDL $~0xC, AX /* EM=0, TS=0 */ ;\
  595. MOVL AX, CR0
  596. TEXT fpoff(SB), $0 /* disable */
  597. FPOFF(l1)
  598. RET
  599. TEXT fpinit(SB), $0 /* enable and init */
  600. FPON
  601. FINIT
  602. WAIT
  603. /* setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL) */
  604. /* note that low 6 bits are masks, not enables, on this chip */
  605. PUSHW $0x0232
  606. FLDCW 0(SP)
  607. POPW AX
  608. WAIT
  609. RET
  610. TEXT fpsave(SB), $0 /* save state and disable */
  611. MOVL p+0(FP), AX
  612. FSAVE 0(AX) /* no WAIT */
  613. FPOFF(l2)
  614. RET
  615. TEXT fprestore(SB), $0 /* enable and restore state */
  616. FPON
  617. MOVL p+0(FP), AX
  618. FRSTOR 0(AX)
  619. WAIT
  620. RET
  621. TEXT fpstatus(SB), $0 /* get floating point status */
  622. FSTSW AX
  623. RET
  624. TEXT fpenv(SB), $0 /* save state without waiting */
  625. MOVL p+0(FP), AX
  626. FSTENV 0(AX)
  627. RET
  628. TEXT fpclear(SB), $0 /* clear pending exceptions */
  629. FPON
  630. FCLEX /* no WAIT */
  631. FPOFF(l3)
  632. RET
  633. /*
  634. */
  635. TEXT splhi(SB), $0
  636. shi:
  637. PUSHFL
  638. POPL AX
  639. TESTL $0x200, AX
  640. JZ alreadyhi
  641. MOVL $(MACHADDR+0x04), CX /* save PC in m->splpc */
  642. MOVL (SP), BX
  643. MOVL BX, (CX)
  644. alreadyhi:
  645. CLI
  646. RET
  647. TEXT spllo(SB), $0
  648. slo:
  649. PUSHFL
  650. POPL AX
  651. TESTL $0x200, AX
  652. JNZ alreadylo
  653. MOVL $(MACHADDR+0x04), CX /* clear m->splpc */
  654. MOVL $0, (CX)
  655. alreadylo:
  656. STI
  657. RET
  658. TEXT splx(SB), $0
  659. MOVL s+0(FP), AX
  660. TESTL $0x200, AX
  661. JNZ slo
  662. JMP shi
  663. TEXT spldone(SB), $0
  664. RET
  665. TEXT islo(SB), $0
  666. PUSHFL
  667. POPL AX
  668. ANDL $0x200, AX /* interrupt enable flag */
  669. RET
  670. /*
  671. * Test-And-Set
  672. */
  673. TEXT tas(SB), $0
  674. MOVL $0xDEADDEAD, AX
  675. MOVL lock+0(FP), BX
  676. XCHGL AX, (BX) /* lock->key */
  677. RET
  678. TEXT _xinc(SB), $0 /* void _xinc(long*); */
  679. MOVL l+0(FP), AX
  680. LOCK; INCL 0(AX)
  681. RET
  682. TEXT _xdec(SB), $0 /* long _xdec(long*); */
  683. MOVL l+0(FP), BX
  684. XORL AX, AX
  685. LOCK; DECL 0(BX)
  686. JLT _xdeclt
  687. JGT _xdecgt
  688. RET
  689. _xdecgt:
  690. INCL AX
  691. RET
  692. _xdeclt:
  693. DECL AX
  694. RET
  695. TEXT mb386(SB), $0
  696. POPL AX /* return PC */
  697. PUSHFL
  698. PUSHL CS
  699. PUSHL AX
  700. IRETL
  701. TEXT mb586(SB), $0
  702. XORL AX, AX
  703. CPUID
  704. RET
  705. TEXT xchgw(SB), $0
  706. MOVL v+4(FP), AX
  707. MOVL p+0(FP), BX
  708. XCHGW AX, (BX)
  709. RET
  710. TEXT cmpswap486(SB), $0
  711. MOVL addr+0(FP), BX
  712. MOVL old+4(FP), AX
  713. MOVL new+8(FP), CX
  714. LOCK
  715. BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
  716. JNZ didnt
  717. MOVL $1, AX
  718. RET
  719. didnt:
  720. XORL AX,AX
  721. RET
  722. TEXT mul64fract(SB), $0
  723. /*
  724. * Multiply two 64-bit number s and keep the middle 64 bits from the 128-bit result
  725. * See ../port/tod.c for motivation.
  726. */
  727. MOVL r+0(FP), CX
  728. XORL BX, BX /* BX = 0 */
  729. MOVL a+8(FP), AX
  730. MULL b+16(FP) /* a1*b1 */
  731. MOVL AX, 4(CX) /* r2 = lo(a1*b1) */
  732. MOVL a+8(FP), AX
  733. MULL b+12(FP) /* a1*b0 */
  734. MOVL AX, 0(CX) /* r1 = lo(a1*b0) */
  735. ADDL DX, 4(CX) /* r2 += hi(a1*b0) */
  736. MOVL a+4(FP), AX
  737. MULL b+16(FP) /* a0*b1 */
  738. ADDL AX, 0(CX) /* r1 += lo(a0*b1) */
  739. ADCL DX, 4(CX) /* r2 += hi(a0*b1) + carry */
  740. MOVL a+4(FP), AX
  741. MULL b+12(FP) /* a0*b0 */
  742. ADDL DX, 0(CX) /* r1 += hi(a0*b0) */
  743. ADCL BX, 4(CX) /* r2 += carry */
  744. RET
  745. /*
  746. * label consists of a stack pointer and a PC
  747. */
  748. TEXT gotolabel(SB), $0
  749. MOVL label+0(FP), AX
  750. MOVL 0(AX), SP /* restore sp */
  751. MOVL 4(AX), AX /* put return pc on the stack */
  752. MOVL AX, 0(SP)
  753. MOVL $1, AX /* return 1 */
  754. RET
  755. TEXT setlabel(SB), $0
  756. MOVL label+0(FP), AX
  757. MOVL SP, 0(AX) /* store sp */
  758. MOVL 0(SP), BX /* store return pc */
  759. MOVL BX, 4(AX)
  760. MOVL $0, AX /* return 0 */
  761. RET
  762. /*
  763. * Attempt at power saving. -rsc
  764. */
  765. TEXT halt(SB), $0
  766. CLI
  767. CMPL nrdy(SB), $0
  768. JEQ _nothingready
  769. STI
  770. RET
  771. _nothingready:
  772. STI
  773. HLT
  774. RET
  775. /*
  776. * Interrupt/exception handling.
  777. * Each entry in the vector table calls either _strayintr or _strayintrx depending
  778. * on whether an error code has been automatically pushed onto the stack
  779. * (_strayintrx) or not, in which case a dummy entry must be pushed before retrieving
  780. * the trap type from the vector table entry and placing it on the stack as part
  781. * of the Ureg structure.
  782. * The size of each entry in the vector table (6 bytes) is known in trapinit().
  783. */
  784. TEXT _strayintr(SB), $0
  785. PUSHL AX /* save AX */
  786. MOVL 4(SP), AX /* return PC from vectortable(SB) */
  787. JMP intrcommon
  788. TEXT _strayintrx(SB), $0
  789. XCHGL AX, (SP) /* swap AX with vectortable CALL PC */
  790. intrcommon:
  791. PUSHL DS /* save DS */
  792. PUSHL $(KDSEL)
  793. POPL DS /* fix up DS */
  794. MOVBLZX (AX), AX /* trap type -> AX */
  795. XCHGL AX, 4(SP) /* exchange trap type with saved AX */
  796. PUSHL ES /* save ES */
  797. PUSHL $(KDSEL)
  798. POPL ES /* fix up ES */
  799. PUSHL FS /* save the rest of the Ureg struct */
  800. PUSHL GS
  801. PUSHAL
  802. PUSHL SP /* Ureg* argument to trap */
  803. CALL trap(SB)
  804. TEXT forkret(SB), $0
  805. POPL AX
  806. POPAL
  807. POPL GS
  808. POPL FS
  809. POPL ES
  810. POPL DS
  811. ADDL $8, SP /* pop error code and trap type */
  812. IRETL
  813. TEXT vectortable(SB), $0
  814. CALL _strayintr(SB); BYTE $0x00 /* divide error */
  815. CALL _strayintr(SB); BYTE $0x01 /* debug exception */
  816. CALL _strayintr(SB); BYTE $0x02 /* NMI interrupt */
  817. CALL _strayintr(SB); BYTE $0x03 /* breakpoint */
  818. CALL _strayintr(SB); BYTE $0x04 /* overflow */
  819. CALL _strayintr(SB); BYTE $0x05 /* bound */
  820. CALL _strayintr(SB); BYTE $0x06 /* invalid opcode */
  821. CALL _strayintr(SB); BYTE $0x07 /* no coprocessor available */
  822. CALL _strayintrx(SB); BYTE $0x08 /* double fault */
  823. CALL _strayintr(SB); BYTE $0x09 /* coprocessor segment overflow */
  824. CALL _strayintrx(SB); BYTE $0x0A /* invalid TSS */
  825. CALL _strayintrx(SB); BYTE $0x0B /* segment not available */
  826. CALL _strayintrx(SB); BYTE $0x0C /* stack exception */
  827. CALL _strayintrx(SB); BYTE $0x0D /* general protection error */
  828. CALL _strayintrx(SB); BYTE $0x0E /* page fault */
  829. CALL _strayintr(SB); BYTE $0x0F /* */
  830. CALL _strayintr(SB); BYTE $0x10 /* coprocessor error */
  831. CALL _strayintrx(SB); BYTE $0x11 /* alignment check */
  832. CALL _strayintr(SB); BYTE $0x12 /* machine check */
  833. CALL _strayintr(SB); BYTE $0x13
  834. CALL _strayintr(SB); BYTE $0x14
  835. CALL _strayintr(SB); BYTE $0x15
  836. CALL _strayintr(SB); BYTE $0x16
  837. CALL _strayintr(SB); BYTE $0x17
  838. CALL _strayintr(SB); BYTE $0x18
  839. CALL _strayintr(SB); BYTE $0x19
  840. CALL _strayintr(SB); BYTE $0x1A
  841. CALL _strayintr(SB); BYTE $0x1B
  842. CALL _strayintr(SB); BYTE $0x1C
  843. CALL _strayintr(SB); BYTE $0x1D
  844. CALL _strayintr(SB); BYTE $0x1E
  845. CALL _strayintr(SB); BYTE $0x1F
  846. CALL _strayintr(SB); BYTE $0x20 /* VectorLAPIC */
  847. CALL _strayintr(SB); BYTE $0x21
  848. CALL _strayintr(SB); BYTE $0x22
  849. CALL _strayintr(SB); BYTE $0x23
  850. CALL _strayintr(SB); BYTE $0x24
  851. CALL _strayintr(SB); BYTE $0x25
  852. CALL _strayintr(SB); BYTE $0x26
  853. CALL _strayintr(SB); BYTE $0x27
  854. CALL _strayintr(SB); BYTE $0x28
  855. CALL _strayintr(SB); BYTE $0x29
  856. CALL _strayintr(SB); BYTE $0x2A
  857. CALL _strayintr(SB); BYTE $0x2B
  858. CALL _strayintr(SB); BYTE $0x2C
  859. CALL _strayintr(SB); BYTE $0x2D
  860. CALL _strayintr(SB); BYTE $0x2E
  861. CALL _strayintr(SB); BYTE $0x2F
  862. CALL _strayintr(SB); BYTE $0x30
  863. CALL _strayintr(SB); BYTE $0x31
  864. CALL _strayintr(SB); BYTE $0x32
  865. CALL _strayintr(SB); BYTE $0x33
  866. CALL _strayintr(SB); BYTE $0x34
  867. CALL _strayintr(SB); BYTE $0x35
  868. CALL _strayintr(SB); BYTE $0x36
  869. CALL _strayintr(SB); BYTE $0x37
  870. CALL _strayintr(SB); BYTE $0x38
  871. CALL _strayintr(SB); BYTE $0x39
  872. CALL _strayintr(SB); BYTE $0x3A
  873. CALL _strayintr(SB); BYTE $0x3B
  874. CALL _strayintr(SB); BYTE $0x3C
  875. CALL _strayintr(SB); BYTE $0x3D
  876. CALL _strayintr(SB); BYTE $0x3E
  877. CALL _strayintr(SB); BYTE $0x3F
  878. CALL _syscallintr(SB); BYTE $0x40 /* VectorSYSCALL */
  879. CALL _strayintr(SB); BYTE $0x41
  880. CALL _strayintr(SB); BYTE $0x42
  881. CALL _strayintr(SB); BYTE $0x43
  882. CALL _strayintr(SB); BYTE $0x44
  883. CALL _strayintr(SB); BYTE $0x45
  884. CALL _strayintr(SB); BYTE $0x46
  885. CALL _strayintr(SB); BYTE $0x47
  886. CALL _strayintr(SB); BYTE $0x48
  887. CALL _strayintr(SB); BYTE $0x49
  888. CALL _strayintr(SB); BYTE $0x4A
  889. CALL _strayintr(SB); BYTE $0x4B
  890. CALL _strayintr(SB); BYTE $0x4C
  891. CALL _strayintr(SB); BYTE $0x4D
  892. CALL _strayintr(SB); BYTE $0x4E
  893. CALL _strayintr(SB); BYTE $0x4F
  894. CALL _strayintr(SB); BYTE $0x50
  895. CALL _strayintr(SB); BYTE $0x51
  896. CALL _strayintr(SB); BYTE $0x52
  897. CALL _strayintr(SB); BYTE $0x53
  898. CALL _strayintr(SB); BYTE $0x54
  899. CALL _strayintr(SB); BYTE $0x55
  900. CALL _strayintr(SB); BYTE $0x56
  901. CALL _strayintr(SB); BYTE $0x57
  902. CALL _strayintr(SB); BYTE $0x58
  903. CALL _strayintr(SB); BYTE $0x59
  904. CALL _strayintr(SB); BYTE $0x5A
  905. CALL _strayintr(SB); BYTE $0x5B
  906. CALL _strayintr(SB); BYTE $0x5C
  907. CALL _strayintr(SB); BYTE $0x5D
  908. CALL _strayintr(SB); BYTE $0x5E
  909. CALL _strayintr(SB); BYTE $0x5F
  910. CALL _strayintr(SB); BYTE $0x60
  911. CALL _strayintr(SB); BYTE $0x61
  912. CALL _strayintr(SB); BYTE $0x62
  913. CALL _strayintr(SB); BYTE $0x63
  914. CALL _strayintr(SB); BYTE $0x64
  915. CALL _strayintr(SB); BYTE $0x65
  916. CALL _strayintr(SB); BYTE $0x66
  917. CALL _strayintr(SB); BYTE $0x67
  918. CALL _strayintr(SB); BYTE $0x68
  919. CALL _strayintr(SB); BYTE $0x69
  920. CALL _strayintr(SB); BYTE $0x6A
  921. CALL _strayintr(SB); BYTE $0x6B
  922. CALL _strayintr(SB); BYTE $0x6C
  923. CALL _strayintr(SB); BYTE $0x6D
  924. CALL _strayintr(SB); BYTE $0x6E
  925. CALL _strayintr(SB); BYTE $0x6F
  926. CALL _strayintr(SB); BYTE $0x70
  927. CALL _strayintr(SB); BYTE $0x71
  928. CALL _strayintr(SB); BYTE $0x72
  929. CALL _strayintr(SB); BYTE $0x73
  930. CALL _strayintr(SB); BYTE $0x74
  931. CALL _strayintr(SB); BYTE $0x75
  932. CALL _strayintr(SB); BYTE $0x76
  933. CALL _strayintr(SB); BYTE $0x77
  934. CALL _strayintr(SB); BYTE $0x78
  935. CALL _strayintr(SB); BYTE $0x79
  936. CALL _strayintr(SB); BYTE $0x7A
  937. CALL _strayintr(SB); BYTE $0x7B
  938. CALL _strayintr(SB); BYTE $0x7C
  939. CALL _strayintr(SB); BYTE $0x7D
  940. CALL _strayintr(SB); BYTE $0x7E
  941. CALL _strayintr(SB); BYTE $0x7F
  942. CALL _strayintr(SB); BYTE $0x80 /* Vector[A]PIC */
  943. CALL _strayintr(SB); BYTE $0x81
  944. CALL _strayintr(SB); BYTE $0x82
  945. CALL _strayintr(SB); BYTE $0x83
  946. CALL _strayintr(SB); BYTE $0x84
  947. CALL _strayintr(SB); BYTE $0x85
  948. CALL _strayintr(SB); BYTE $0x86
  949. CALL _strayintr(SB); BYTE $0x87
  950. CALL _strayintr(SB); BYTE $0x88
  951. CALL _strayintr(SB); BYTE $0x89
  952. CALL _strayintr(SB); BYTE $0x8A
  953. CALL _strayintr(SB); BYTE $0x8B
  954. CALL _strayintr(SB); BYTE $0x8C
  955. CALL _strayintr(SB); BYTE $0x8D
  956. CALL _strayintr(SB); BYTE $0x8E
  957. CALL _strayintr(SB); BYTE $0x8F
  958. CALL _strayintr(SB); BYTE $0x90
  959. CALL _strayintr(SB); BYTE $0x91
  960. CALL _strayintr(SB); BYTE $0x92
  961. CALL _strayintr(SB); BYTE $0x93
  962. CALL _strayintr(SB); BYTE $0x94
  963. CALL _strayintr(SB); BYTE $0x95
  964. CALL _strayintr(SB); BYTE $0x96
  965. CALL _strayintr(SB); BYTE $0x97
  966. CALL _strayintr(SB); BYTE $0x98
  967. CALL _strayintr(SB); BYTE $0x99
  968. CALL _strayintr(SB); BYTE $0x9A
  969. CALL _strayintr(SB); BYTE $0x9B
  970. CALL _strayintr(SB); BYTE $0x9C
  971. CALL _strayintr(SB); BYTE $0x9D
  972. CALL _strayintr(SB); BYTE $0x9E
  973. CALL _strayintr(SB); BYTE $0x9F
  974. CALL _strayintr(SB); BYTE $0xA0
  975. CALL _strayintr(SB); BYTE $0xA1
  976. CALL _strayintr(SB); BYTE $0xA2
  977. CALL _strayintr(SB); BYTE $0xA3
  978. CALL _strayintr(SB); BYTE $0xA4
  979. CALL _strayintr(SB); BYTE $0xA5
  980. CALL _strayintr(SB); BYTE $0xA6
  981. CALL _strayintr(SB); BYTE $0xA7
  982. CALL _strayintr(SB); BYTE $0xA8
  983. CALL _strayintr(SB); BYTE $0xA9
  984. CALL _strayintr(SB); BYTE $0xAA
  985. CALL _strayintr(SB); BYTE $0xAB
  986. CALL _strayintr(SB); BYTE $0xAC
  987. CALL _strayintr(SB); BYTE $0xAD
  988. CALL _strayintr(SB); BYTE $0xAE
  989. CALL _strayintr(SB); BYTE $0xAF
  990. CALL _strayintr(SB); BYTE $0xB0
  991. CALL _strayintr(SB); BYTE $0xB1
  992. CALL _strayintr(SB); BYTE $0xB2
  993. CALL _strayintr(SB); BYTE $0xB3
  994. CALL _strayintr(SB); BYTE $0xB4
  995. CALL _strayintr(SB); BYTE $0xB5
  996. CALL _strayintr(SB); BYTE $0xB6
  997. CALL _strayintr(SB); BYTE $0xB7
  998. CALL _strayintr(SB); BYTE $0xB8
  999. CALL _strayintr(SB); BYTE $0xB9
  1000. CALL _strayintr(SB); BYTE $0xBA
  1001. CALL _strayintr(SB); BYTE $0xBB
  1002. CALL _strayintr(SB); BYTE $0xBC
  1003. CALL _strayintr(SB); BYTE $0xBD
  1004. CALL _strayintr(SB); BYTE $0xBE
  1005. CALL _strayintr(SB); BYTE $0xBF
  1006. CALL _strayintr(SB); BYTE $0xC0
  1007. CALL _strayintr(SB); BYTE $0xC1
  1008. CALL _strayintr(SB); BYTE $0xC2
  1009. CALL _strayintr(SB); BYTE $0xC3
  1010. CALL _strayintr(SB); BYTE $0xC4
  1011. CALL _strayintr(SB); BYTE $0xC5
  1012. CALL _strayintr(SB); BYTE $0xC6
  1013. CALL _strayintr(SB); BYTE $0xC7
  1014. CALL _strayintr(SB); BYTE $0xC8
  1015. CALL _strayintr(SB); BYTE $0xC9
  1016. CALL _strayintr(SB); BYTE $0xCA
  1017. CALL _strayintr(SB); BYTE $0xCB
  1018. CALL _strayintr(SB); BYTE $0xCC
  1019. CALL _strayintr(SB); BYTE $0xCD
  1020. CALL _strayintr(SB); BYTE $0xCE
  1021. CALL _strayintr(SB); BYTE $0xCF
  1022. CALL _strayintr(SB); BYTE $0xD0
  1023. CALL _strayintr(SB); BYTE $0xD1
  1024. CALL _strayintr(SB); BYTE $0xD2
  1025. CALL _strayintr(SB); BYTE $0xD3
  1026. CALL _strayintr(SB); BYTE $0xD4
  1027. CALL _strayintr(SB); BYTE $0xD5
  1028. CALL _strayintr(SB); BYTE $0xD6
  1029. CALL _strayintr(SB); BYTE $0xD7
  1030. CALL _strayintr(SB); BYTE $0xD8
  1031. CALL _strayintr(SB); BYTE $0xD9
  1032. CALL _strayintr(SB); BYTE $0xDA
  1033. CALL _strayintr(SB); BYTE $0xDB
  1034. CALL _strayintr(SB); BYTE $0xDC
  1035. CALL _strayintr(SB); BYTE $0xDD
  1036. CALL _strayintr(SB); BYTE $0xDE
  1037. CALL _strayintr(SB); BYTE $0xDF
  1038. CALL _strayintr(SB); BYTE $0xE0
  1039. CALL _strayintr(SB); BYTE $0xE1
  1040. CALL _strayintr(SB); BYTE $0xE2
  1041. CALL _strayintr(SB); BYTE $0xE3
  1042. CALL _strayintr(SB); BYTE $0xE4
  1043. CALL _strayintr(SB); BYTE $0xE5
  1044. CALL _strayintr(SB); BYTE $0xE6
  1045. CALL _strayintr(SB); BYTE $0xE7
  1046. CALL _strayintr(SB); BYTE $0xE8
  1047. CALL _strayintr(SB); BYTE $0xE9
  1048. CALL _strayintr(SB); BYTE $0xEA
  1049. CALL _strayintr(SB); BYTE $0xEB
  1050. CALL _strayintr(SB); BYTE $0xEC
  1051. CALL _strayintr(SB); BYTE $0xED
  1052. CALL _strayintr(SB); BYTE $0xEE
  1053. CALL _strayintr(SB); BYTE $0xEF
  1054. CALL _strayintr(SB); BYTE $0xF0
  1055. CALL _strayintr(SB); BYTE $0xF1
  1056. CALL _strayintr(SB); BYTE $0xF2
  1057. CALL _strayintr(SB); BYTE $0xF3
  1058. CALL _strayintr(SB); BYTE $0xF4
  1059. CALL _strayintr(SB); BYTE $0xF5
  1060. CALL _strayintr(SB); BYTE $0xF6
  1061. CALL _strayintr(SB); BYTE $0xF7
  1062. CALL _strayintr(SB); BYTE $0xF8
  1063. CALL _strayintr(SB); BYTE $0xF9
  1064. CALL _strayintr(SB); BYTE $0xFA
  1065. CALL _strayintr(SB); BYTE $0xFB
  1066. CALL _strayintr(SB); BYTE $0xFC
  1067. CALL _strayintr(SB); BYTE $0xFD
  1068. CALL _strayintr(SB); BYTE $0xFE
  1069. CALL _strayintr(SB); BYTE $0xFF