io.h 8.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333
  1. enum {
  2. Mhz = 1000*1000,
  3. };
  4. /*
  5. * duarts, frequency and registers
  6. */
  7. #define DUARTFREQ 3672000
  8. /*
  9. * interrupt levels on CPU boards.
  10. */
  11. enum
  12. {
  13. ILmin = 2,
  14. ILpci = 2,
  15. ILehci = 3,
  16. ILenet1 = 4, /* arge1 @ 0x19:: w switch */
  17. ILenet0 = 5, /* arge0 @ 0x1a:: */
  18. ILduart0 = 6, /* actually APB, uart is subintr 3 */
  19. ILclock = 7,
  20. ILmax = 7,
  21. ILshift = 8,
  22. };
  23. #define Rstblockbase (ulong *)KSEG1ADDR(0x18060000)
  24. #define Rstwdogctl (ulong *)KSEG1ADDR(0x18060008)
  25. #define Wdoglast (1 << 31)
  26. #define Wdogmask 3
  27. #define Wdognoaction 0
  28. #define Wdoggpintr 1
  29. #define Wdognmi 2
  30. #define Wdogreset 3
  31. #define Rstwdogtimer (ulong *)KSEG1ADDR(0x1806000c)
  32. /*
  33. * APB interrupt status and mask register and interrupt bits
  34. */
  35. #define Apbintrsts (ulong *)KSEG1ADDR(0x18060010)
  36. #define Apbintrmask (ulong *)KSEG1ADDR(0x18060014)
  37. #define Apbintrtimer 0
  38. #define Apbintrerror 1
  39. #define Apbintrgpio 2
  40. #define Apbintruart 3
  41. #define Apbintrwatchdog 4
  42. #define Apbintrperf 5
  43. #define Apbintrohci 6
  44. #define Apbintrdma 7
  45. #define Pciintrsts (ulong *)KSEG1ADDR(0x18060018)
  46. #define Pciintrmask (ulong *)KSEG1ADDR(0x1806001C)
  47. #define PCI_INTR_CORE (1 << 4)
  48. #define Reset (ulong *)KSEG1ADDR(0x18060024)
  49. #define Rstfullchip (1 << 24) /* same as pulling the reset pin */
  50. #define Rstcpucold (1 << 20) /* cold reset */
  51. #define Rstge1mac (1 << 13)
  52. #define Rstge1phy (1 << 12)
  53. #define Rstge0mac (1 << 9)
  54. #define Rstge0phy (1 << 8)
  55. #define Rstusbohcidll (1 << 6)
  56. #define Rstusbhost (1 << 5)
  57. #define Rstusbphy (1 << 4)
  58. #define Rstpcibus (1 << 1)
  59. #define Rstpcicore (1 << 0)
  60. /*
  61. * mostly PCI from here on
  62. */
  63. typedef struct Pcisiz Pcisiz;
  64. typedef struct Pcidev Pcidev;
  65. typedef struct Vctl Vctl;
  66. struct Vctl {
  67. Vctl* next; /* handlers on this vector */
  68. char name[KNAMELEN]; /* of driver */
  69. int isintr; /* interrupt or fault/trap */
  70. int irq;
  71. int tbdf;
  72. int (*isr)(int); /* get isr bit for this irq */
  73. int (*eoi)(int); /* eoi */
  74. void (*f)(Ureg*, void*); /* handler to call */
  75. void* a; /* argument to call it with */
  76. };
  77. enum {
  78. BusCBUS = 0, /* Corollary CBUS */
  79. BusCBUSII, /* Corollary CBUS II */
  80. BusEISA, /* Extended ISA */
  81. BusFUTURE, /* IEEE Futurebus */
  82. BusINTERN, /* Internal bus */
  83. BusISA, /* Industry Standard Architecture */
  84. BusMBI, /* Multibus I */
  85. BusMBII, /* Multibus II */
  86. BusMCA, /* Micro Channel Architecture */
  87. BusMPI, /* MPI */
  88. BusMPSA, /* MPSA */
  89. BusNUBUS, /* Apple Macintosh NuBus */
  90. BusPCI, /* Peripheral Component Interconnect */
  91. BusPCMCIA, /* PC Memory Card International Association */
  92. BusTC, /* DEC TurboChannel */
  93. BusVL, /* VESA Local bus */
  94. BusVME, /* VMEbus */
  95. BusXPRESS, /* Express System Bus */
  96. };
  97. #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  98. #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
  99. #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
  100. #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
  101. #define BUSTYPE(tbdf) ((tbdf)>>24)
  102. #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
  103. #define BUSUNKNOWN (-1)
  104. enum {
  105. MaxEISA = 16,
  106. CfgEISA = 0xC80,
  107. };
  108. /*
  109. * PCI support code.
  110. */
  111. enum { /* type 0 & type 1 pre-defined header */
  112. PciVID = 0x00, /* vendor ID */
  113. PciDID = 0x02, /* device ID */
  114. PciPCR = 0x04, /* command */
  115. PciPSR = 0x06, /* status */
  116. PciRID = 0x08, /* revision ID */
  117. PciCCRp = 0x09, /* programming interface class code */
  118. PciCCRu = 0x0A, /* sub-class code */
  119. PciCCRb = 0x0B, /* base class code */
  120. PciCLS = 0x0C, /* cache line size */
  121. PciLTR = 0x0D, /* latency timer */
  122. PciHDT = 0x0E, /* header type */
  123. PciBST = 0x0F, /* BIST */
  124. PciBAR0 = 0x10, /* base address */
  125. PciBAR1 = 0x14,
  126. PciINTL = 0x3C, /* interrupt line */
  127. PciINTP = 0x3D, /* interrupt pin */
  128. };
  129. /* ccrb (base class code) values; controller types */
  130. enum {
  131. Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
  132. Pcibcstore = 1, /* mass storage */
  133. Pcibcnet = 2, /* network */
  134. Pcibcdisp = 3, /* display */
  135. Pcibcmmedia = 4, /* multimedia */
  136. Pcibcmem = 5, /* memory */
  137. Pcibcbridge = 6, /* bridge */
  138. Pcibccomm = 7, /* simple comms (e.g., serial) */
  139. Pcibcbasesys = 8, /* base system */
  140. Pcibcinput = 9, /* input */
  141. Pcibcdock = 0xa, /* docking stations */
  142. Pcibcproc = 0xb, /* processors */
  143. Pcibcserial = 0xc, /* serial bus (e.g., USB) */
  144. Pcibcwireless = 0xd, /* wireless */
  145. Pcibcintell = 0xe, /* intelligent i/o */
  146. Pcibcsatcom = 0xf, /* satellite comms */
  147. Pcibccrypto = 0x10, /* encryption/decryption */
  148. Pcibcdacq = 0x11, /* data acquisition & signal proc. */
  149. };
  150. /* ccru (sub-class code) values; common cases only */
  151. enum {
  152. /* mass storage */
  153. Pciscscsi = 0, /* SCSI */
  154. Pciscide = 1, /* IDE (ATA) */
  155. Pciscsata = 6, /* SATA */
  156. /* network */
  157. Pciscether = 0, /* Ethernet */
  158. /* display */
  159. Pciscvga = 0, /* VGA */
  160. Pciscxga = 1, /* XGA */
  161. Pcisc3d = 2, /* 3D */
  162. /* bridges */
  163. Pcischostpci = 0, /* host/pci */
  164. Pciscpcicpci = 1, /* pci/pci */
  165. /* simple comms */
  166. Pciscserial = 0, /* 16450, etc. */
  167. Pciscmultiser = 1, /* multiport serial */
  168. /* serial bus */
  169. Pciscusb = 3, /* USB */
  170. };
  171. enum { /* type 0 pre-defined header */
  172. PciCIS = 0x28, /* cardbus CIS pointer */
  173. PciSVID = 0x2C, /* subsystem vendor ID */
  174. PciSID = 0x2E, /* cardbus CIS pointer */
  175. PciEBAR0 = 0x30, /* expansion ROM base address */
  176. PciMGNT = 0x3E, /* burst period length */
  177. PciMLT = 0x3F, /* maximum latency between bursts */
  178. };
  179. enum { /* type 1 pre-defined header */
  180. PciPBN = 0x18, /* primary bus number */
  181. PciSBN = 0x19, /* secondary bus number */
  182. PciUBN = 0x1A, /* subordinate bus number */
  183. PciSLTR = 0x1B, /* secondary latency timer */
  184. PciIBR = 0x1C, /* I/O base */
  185. PciILR = 0x1D, /* I/O limit */
  186. PciSPSR = 0x1E, /* secondary status */
  187. PciMBR = 0x20, /* memory base */
  188. PciMLR = 0x22, /* memory limit */
  189. PciPMBR = 0x24, /* prefetchable memory base */
  190. PciPMLR = 0x26, /* prefetchable memory limit */
  191. PciPUBR = 0x28, /* prefetchable base upper 32 bits */
  192. PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
  193. PciIUBR = 0x30, /* I/O base upper 16 bits */
  194. PciIULR = 0x32, /* I/O limit upper 16 bits */
  195. PciEBAR1 = 0x28, /* expansion ROM base address */
  196. PciBCR = 0x3E, /* bridge control register */
  197. };
  198. enum { /* type 2 pre-defined header */
  199. PciCBExCA = 0x10,
  200. PciCBSPSR = 0x16,
  201. PciCBPBN = 0x18, /* primary bus number */
  202. PciCBSBN = 0x19, /* secondary bus number */
  203. PciCBUBN = 0x1A, /* subordinate bus number */
  204. PciCBSLTR = 0x1B, /* secondary latency timer */
  205. PciCBMBR0 = 0x1C,
  206. PciCBMLR0 = 0x20,
  207. PciCBMBR1 = 0x24,
  208. PciCBMLR1 = 0x28,
  209. PciCBIBR0 = 0x2C, /* I/O base */
  210. PciCBILR0 = 0x30, /* I/O limit */
  211. PciCBIBR1 = 0x34, /* I/O base */
  212. PciCBILR1 = 0x38, /* I/O limit */
  213. PciCBSVID = 0x40, /* subsystem vendor ID */
  214. PciCBSID = 0x42, /* subsystem ID */
  215. PciCBLMBAR = 0x44, /* legacy mode base address */
  216. };
  217. struct Pcisiz
  218. {
  219. Pcidev* dev;
  220. int siz;
  221. int bar;
  222. };
  223. struct Pcidev
  224. {
  225. int tbdf; /* type+bus+device+function */
  226. ushort vid; /* vendor ID */
  227. ushort did; /* device ID */
  228. ushort pcr;
  229. uchar rid;
  230. uchar ccrp;
  231. uchar ccru;
  232. uchar ccrb;
  233. uchar cls;
  234. uchar ltr;
  235. struct {
  236. ulong bar; /* base address */
  237. int size;
  238. } mem[6];
  239. struct {
  240. ulong bar;
  241. int size;
  242. } rom;
  243. uchar intl; /* interrupt line */
  244. Pcidev* list;
  245. Pcidev* link; /* next device on this bno */
  246. Pcidev* bridge; /* down a bus */
  247. struct {
  248. ulong bar;
  249. int size;
  250. } ioa, mema;
  251. int pmrb; /* power management register block */
  252. };
  253. enum {
  254. /* vendor ids */
  255. Vatiamd = 0x1002,
  256. Vintel = 0x8086,
  257. Vjmicron= 0x197b,
  258. Vmarvell= 0x1b4b,
  259. Vmyricom= 0x14c1,
  260. };
  261. #define PCIWINDOW 0
  262. #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
  263. #define ISAWINDOW 0
  264. #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
  265. /* SMBus transactions */
  266. enum
  267. {
  268. SMBquick, /* sends address only */
  269. /* write */
  270. SMBsend, /* sends address and cmd */
  271. SMBbytewrite, /* sends address and cmd and 1 byte */
  272. SMBwordwrite, /* sends address and cmd and 2 bytes */
  273. /* read */
  274. SMBrecv, /* sends address, recvs 1 byte */
  275. SMBbyteread, /* sends address and cmd, recv's byte */
  276. SMBwordread, /* sends address and cmd, recv's 2 bytes */
  277. };
  278. typedef struct SMBus SMBus;
  279. struct SMBus {
  280. QLock; /* mutex */
  281. Rendez r; /* rendezvous point for completion interrupts */
  282. void *arg; /* implementation dependent */
  283. ulong base; /* port or memory base of smbus */
  284. int busy;
  285. void (*transact)(SMBus*, int, int, int, uchar*);
  286. };
  287. #pragma varargck type "T" int
  288. #pragma varargck type "T" uint