mips.s 2.5 KB

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  1. /*
  2. * mips 24k machine assist
  3. */
  4. #undef MASK
  5. #define MASK(w) ((1<<(w))-1)
  6. #define SP R29
  7. #define NOP NOR R0, R0, R0
  8. #define CONST(x,r) MOVW $((x)&0xffff0000), r; OR $((x)&0xffff), r
  9. /* a mips 24k erratum requires a NOP after; experience dictates EHB before */
  10. #define ERET EHB; WORD $0x42000018; NOP
  11. #define RETURN RET; NOP
  12. /*
  13. * R4000 instructions
  14. */
  15. #define LL(base, rt) WORD $((060<<26)|((base)<<21)|((rt)<<16))
  16. #define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
  17. /* new instructions in mips 24k (mips32r2) */
  18. #define DI(rt) WORD $(0x41606000|((rt)<<16)) /* interrupts off */
  19. #define EI(rt) WORD $(0x41606020|((rt)<<16)) /* interrupts on */
  20. #define EHB WORD $0xc0
  21. /* jalr with hazard barrier, link in R22 */
  22. #define JALRHB(r) WORD $(((r)<<21)|(22<<11)|(1<<10)|9); NOP
  23. /* jump register with hazard barrier */
  24. #define JRHB(r) WORD $(((r)<<21)|(1<<10)|8); NOP
  25. #define MFC0(src,sel,dst) WORD $(0x40000000|((src)<<11)|((dst)<<16)|(sel))
  26. #define MTC0(src,dst,sel) WORD $(0x40800000|((dst)<<11)|((src)<<16)|(sel))
  27. #define MIPS24KNOP NOP /* for erratum #48 */
  28. #define RDHWR(hwr, r) WORD $(0x7c00003b|((hwr)<<11)|((r)<<16))
  29. #define SYNC WORD $0xf /* all sync barriers */
  30. #define WAIT WORD $0x42000020 /* wait for interrupt */
  31. /* all barriers, clears all hazards; clobbers r/Reg and R22 */
  32. #define BARRIERS(r, Reg, label) \
  33. SYNC; EHB; MOVW $ret(SB), Reg; JALRHB(r)
  34. /* same but return to KSEG1 */
  35. #define UBARRIERS(r, Reg, label) \
  36. SYNC; EHB; MOVW $ret(SB), Reg; OR $KSEG1, Reg; JALRHB(r)
  37. /* alternative definitions using labels */
  38. #ifdef notdef
  39. /* all barriers, clears all hazards; clobbers r/Reg */
  40. #define BARRIERS(r, Reg, label) \
  41. SYNC; EHB; \
  42. MOVW $label(SB), Reg; \
  43. JRHB(r); \
  44. TEXT label(SB), $-4; \
  45. NOP
  46. #define UBARRIERS(r, Reg, label) \
  47. SYNC; EHB; \
  48. MOVW $label(SB), Reg; \
  49. OR $KSEG1, Reg; \
  50. JRHB(r); \
  51. TEXT label(SB), $-4; \
  52. NOP
  53. #endif
  54. #define PUTC(c, r1, r2) CONST(PHYSCONS, r1); MOVW $(c), r2; MOVW r2, (r1); NOP
  55. /*
  56. * cache manipulation
  57. */
  58. #define CACHE BREAK /* overloaded op-code */
  59. #define PI R((0 /* primary I cache */
  60. #define PD R((1 /* primary D cache */
  61. #define TD R((2 /* tertiary I/D cache */
  62. #define SD R((3 /* secondary combined I/D cache */
  63. #define IWBI (0<<2))) /* index write-back invalidate */
  64. #define ILT (1<<2))) /* index load tag */
  65. #define IST (2<<2))) /* index store tag */
  66. /* #define CDE (3<<2))) /* create dirty exclusive */
  67. #define HINV (4<<2))) /* hit invalidate */
  68. #define HWBI (5<<2))) /* hit write back invalidate */
  69. #define HWB (6<<2))) /* hit write back */
  70. /* #define HSV (7<<2))) /* hit set virtual */