ether82563.c 36 KB

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  1. /*
  2. * Intel 8256[36], 8257[12], 82573[ev] Gigabit Ethernet PCI-Express Controllers
  3. */
  4. #include "u.h"
  5. #include "../port/lib.h"
  6. #include "mem.h"
  7. #include "dat.h"
  8. #include "fns.h"
  9. #include "io.h"
  10. #include "../port/error.h"
  11. #include "../port/netif.h"
  12. #include "etherif.h"
  13. /*
  14. * these are in the order they appear in the manual, not numeric order.
  15. * It was too hard to find them in the book. Ref 21489, rev 2.6
  16. */
  17. enum {
  18. /* General */
  19. Ctrl = 0x0000, /* Device Control */
  20. Status = 0x0008, /* Device Status */
  21. Eec = 0x0010, /* EEPROM/Flash Control/Data */
  22. Eerd = 0x0014, /* EEPROM Read */
  23. Ctrlext = 0x0018, /* Extended Device Control */
  24. Fla = 0x001c, /* Flash Access */
  25. Mdic = 0x0020, /* MDI Control */
  26. Seresctl = 0x0024, /* Serdes ana */
  27. Fcal = 0x0028, /* Flow Control Address Low */
  28. Fcah = 0x002C, /* Flow Control Address High */
  29. Fct = 0x0030, /* Flow Control Type */
  30. Kumctrlsta = 0x0034, /* Kumeran Controll and Status Register */
  31. Vet = 0x0038, /* VLAN EtherType */
  32. Fcttv = 0x0170, /* Flow Control Transmit Timer Value */
  33. Txcw = 0x0178, /* Transmit Configuration Word */
  34. Rxcw = 0x0180, /* Receive Configuration Word */
  35. Ledctl = 0x0E00, /* LED control */
  36. Pba = 0x1000, /* Packet Buffer Allocation */
  37. Pbs = 0x1008, /* Packet Buffer Size */
  38. /* Interrupt */
  39. Icr = 0x00C0, /* Interrupt Cause Read */
  40. Itr = 0x00c4, /* Interrupt Throttling Rate */
  41. Ics = 0x00C8, /* Interrupt Cause Set */
  42. Ims = 0x00D0, /* Interrupt Mask Set/Read */
  43. Imc = 0x00D8, /* Interrupt mask Clear */
  44. Iam = 0x00E0, /* Interrupt acknowledge Auto Mask */
  45. /* Receive */
  46. Rctl = 0x0100, /* Control */
  47. Ert = 0x2008, /* Early Receive Threshold (573[EVL] only) */
  48. Fcrtl = 0x2160, /* Flow Control RX Threshold Low */
  49. Fcrth = 0x2168, /* Flow Control Rx Threshold High */
  50. Psrctl = 0x2170, /* Packet Split Receive Control */
  51. Rdbal = 0x2800, /* Rdesc Base Address Low Queue 0 */
  52. Rdbah = 0x2804, /* Rdesc Base Address High Queue 0 */
  53. Rdlen = 0x2808, /* Descriptor Length Queue 0 */
  54. Rdh = 0x2810, /* Descriptor Head Queue 0 */
  55. Rdt = 0x2818, /* Descriptor Tail Queue 0 */
  56. Rdtr = 0x2820, /* Descriptor Timer Ring */
  57. Rxdctl = 0x2828, /* Descriptor Control */
  58. Radv = 0x282C, /* Interrupt Absolute Delay Timer */
  59. Rdbal1 = 0x2900, /* Rdesc Base Address Low Queue 1 */
  60. Rdbah1 = 0x2804, /* Rdesc Base Address High Queue 1 */
  61. Rdlen1 = 0x2908, /* Descriptor Length Queue 1 */
  62. Rdh1 = 0x2910, /* Descriptor Head Queue 1 */
  63. Rdt1 = 0x2918, /* Descriptor Tail Queue 1 */
  64. Rxdctl1 = 0x2928, /* Descriptor Control Queue 1 */
  65. Rsrpd = 0x2c00, /* Small Packet Detect */
  66. Raid = 0x2c08, /* ACK interrupt delay */
  67. Cpuvec = 0x2c10, /* CPU Vector */
  68. Rxcsum = 0x5000, /* Checksum Control */
  69. Rfctl = 0x5008, /* Filter Control */
  70. Mta = 0x5200, /* Multicast Table Array */
  71. Ral = 0x5400, /* Receive Address Low */
  72. Rah = 0x5404, /* Receive Address High */
  73. Vfta = 0x5600, /* VLAN Filter Table Array */
  74. Mrqc = 0x5818, /* Multiple Receive Queues Command */
  75. Rssim = 0x5864, /* RSS Interrupt Mask */
  76. Rssir = 0x5868, /* RSS Interrupt Request */
  77. Reta = 0x5c00, /* Redirection Table */
  78. Rssrk = 0x5c80, /* RSS Random Key */
  79. /* Transmit */
  80. Tctl = 0x0400, /* Transmit Control */
  81. Tipg = 0x0410, /* Transmit IPG */
  82. Tkabgtxd = 0x3004, /* glci afe band gap transmit ref data, or something */
  83. Tdbal = 0x3800, /* Tdesc Base Address Low */
  84. Tdbah = 0x3804, /* Tdesc Base Address High */
  85. Tdlen = 0x3808, /* Descriptor Length */
  86. Tdh = 0x3810, /* Descriptor Head */
  87. Tdt = 0x3818, /* Descriptor Tail */
  88. Tidv = 0x3820, /* Interrupt Delay Value */
  89. Txdctl = 0x3828, /* Descriptor Control */
  90. Tadv = 0x382C, /* Interrupt Absolute Delay Timer */
  91. Tarc0 = 0x3840, /* Arbitration Counter Queue 0 */
  92. Tdbal1 = 0x3900, /* Descriptor Base Low Queue 1 */
  93. Tdbah1 = 0x3904, /* Descriptor Base High Queue 1 */
  94. Tdlen1 = 0x3908, /* Descriptor Length Queue 1 */
  95. Tdh1 = 0x3910, /* Descriptor Head Queue 1 */
  96. Tdt1 = 0x3918, /* Descriptor Tail Queue 1 */
  97. Txdctl1 = 0x3928, /* Descriptor Control 1 */
  98. Tarc1 = 0x3940, /* Arbitration Counter Queue 1 */
  99. /* Statistics */
  100. Statistics = 0x4000, /* Start of Statistics Area */
  101. Gorcl = 0x88/4, /* Good Octets Received Count */
  102. Gotcl = 0x90/4, /* Good Octets Transmitted Count */
  103. Torl = 0xC0/4, /* Total Octets Received */
  104. Totl = 0xC8/4, /* Total Octets Transmitted */
  105. Nstatistics = 0x124/4,
  106. };
  107. enum { /* Ctrl */
  108. GIOmd = 1<<2, /* BIO master disable */
  109. Lrst = 1<<3, /* link reset */
  110. Slu = 1<<6, /* Set Link Up */
  111. SspeedMASK = 3<<8, /* Speed Selection */
  112. SspeedSHIFT = 8,
  113. Sspeed10 = 0x00000000, /* 10Mb/s */
  114. Sspeed100 = 0x00000100, /* 100Mb/s */
  115. Sspeed1000 = 0x00000200, /* 1000Mb/s */
  116. Frcspd = 1<<11, /* Force Speed */
  117. Frcdplx = 1<<12, /* Force Duplex */
  118. SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
  119. SwdpinsloSHIFT = 18,
  120. SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
  121. SwdpioloSHIFT = 22,
  122. Devrst = 1<<26, /* Device Reset */
  123. Rfce = 1<<27, /* Receive Flow Control Enable */
  124. Tfce = 1<<28, /* Transmit Flow Control Enable */
  125. Vme = 1<<30, /* VLAN Mode Enable */
  126. Phyrst = 1<<31, /* Phy Reset */
  127. };
  128. enum { /* Status */
  129. Lu = 1<<1, /* Link Up */
  130. Lanid = 3<<2, /* mask for Lan ID. */
  131. Txoff = 1<<4, /* Transmission Paused */
  132. Tbimode = 1<<5, /* TBI Mode Indication */
  133. Phyra = 1<<10, /* PHY Reset Asserted */
  134. GIOme = 1<<19, /* GIO Master Enable Status */
  135. };
  136. enum { /* Eerd */
  137. EEstart = 1<<0, /* Start Read */
  138. EEdone = 1<<1, /* Read done */
  139. };
  140. enum { /* Ctrlext */
  141. Asdchk = 1<<12, /* ASD Check */
  142. Eerst = 1<<13, /* EEPROM Reset */
  143. Spdbyps = 1<<15, /* Speed Select Bypass */
  144. };
  145. enum { /* EEPROM content offsets */
  146. Ea = 0x00, /* Ethernet Address */
  147. Cf = 0x03, /* Compatibility Field */
  148. Icw1 = 0x0A, /* Initialization Control Word 1 */
  149. Sid = 0x0B, /* Subsystem ID */
  150. Svid = 0x0C, /* Subsystem Vendor ID */
  151. Did = 0x0D, /* Device ID */
  152. Vid = 0x0E, /* Vendor ID */
  153. Icw2 = 0x0F, /* Initialization Control Word 2 */
  154. };
  155. enum { /* Mdic */
  156. MDIdMASK = 0x0000FFFF, /* Data */
  157. MDIdSHIFT = 0,
  158. MDIrMASK = 0x001F0000, /* PHY Register Address */
  159. MDIrSHIFT = 16,
  160. MDIpMASK = 0x03E00000, /* PHY Address */
  161. MDIpSHIFT = 21,
  162. MDIwop = 0x04000000, /* Write Operation */
  163. MDIrop = 0x08000000, /* Read Operation */
  164. MDIready = 0x10000000, /* End of Transaction */
  165. MDIie = 0x20000000, /* Interrupt Enable */
  166. MDIe = 0x40000000, /* Error */
  167. };
  168. enum { /* Mdic secondary status register */
  169. Physsr = 17, /* phy secondary status register */
  170. Phyier = 18, /* phy interrupt enable register */
  171. Phypage = 22, /* phy page register */
  172. Rtlink = 1<<10, /* realtime link status */
  173. Phyan = 1<<11, /* phy has autonegotiated */
  174. };
  175. enum { /* Icr, Ics, Ims, Imc */
  176. Txdw = 0x00000001, /* Transmit Descriptor Written Back */
  177. Txqe = 0x00000002, /* Transmit Queue Empty */
  178. Lsc = 0x00000004, /* Link Status Change */
  179. Rxseq = 0x00000008, /* Receive Sequence Error */
  180. Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
  181. Rxo = 0x00000040, /* Receiver Overrun */
  182. Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
  183. Mdac = 0x00000200, /* MDIO Access Completed */
  184. Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
  185. Gpi0 = 0x00000800, /* General Purpose Interrupts */
  186. Gpi1 = 0x00001000,
  187. Gpi2 = 0x00002000,
  188. Gpi3 = 0x00004000,
  189. Ack = 0x00020000, /* Receive ACK frame */
  190. };
  191. enum { /* Txcw */
  192. TxcwFd = 0x00000020, /* Full Duplex */
  193. TxcwHd = 0x00000040, /* Half Duplex */
  194. TxcwPauseMASK = 0x00000180, /* Pause */
  195. TxcwPauseSHIFT = 7,
  196. TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */
  197. TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */
  198. TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
  199. TxcwRfiSHIFT = 12,
  200. TxcwNpr = 0x00008000, /* Next Page Request */
  201. TxcwConfig = 0x40000000, /* Transmit COnfig Control */
  202. TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
  203. };
  204. enum { /* Rctl */
  205. Rrst = 0x00000001, /* Receiver Software Reset */
  206. Ren = 0x00000002, /* Receiver Enable */
  207. Sbp = 0x00000004, /* Store Bad Packets */
  208. Upe = 0x00000008, /* Unicast Promiscuous Enable */
  209. Mpe = 0x00000010, /* Multicast Promiscuous Enable */
  210. Lpe = 0x00000020, /* Long Packet Reception Enable */
  211. LbmMASK = 0x000000C0, /* Loopback Mode */
  212. LbmOFF = 0x00000000, /* No Loopback */
  213. LbmTBI = 0x00000040, /* TBI Loopback */
  214. LbmMII = 0x00000080, /* GMII/MII Loopback */
  215. LbmXCVR = 0x000000C0, /* Transceiver Loopback */
  216. RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
  217. RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
  218. RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
  219. RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
  220. MoMASK = 0x00003000, /* Multicast Offset */
  221. Bam = 0x00008000, /* Broadcast Accept Mode */
  222. BsizeMASK = 0x00030000, /* Receive Buffer Size */
  223. Bsize16384 = 0x00010000, /* Bsex = 1 */
  224. Bsize8192 = 0x00020000, /* Bsex = 1 */
  225. Bsize2048 = 0x00000000,
  226. Bsize1024 = 0x00010000,
  227. Bsize512 = 0x00020000,
  228. Bsize256 = 0x00030000,
  229. BsizeFlex = 0x08000000, /* Flexable Bsize in 1kb increments */
  230. Vfe = 0x00040000, /* VLAN Filter Enable */
  231. Cfien = 0x00080000, /* Canonical Form Indicator Enable */
  232. Cfi = 0x00100000, /* Canonical Form Indicator value */
  233. Dpf = 0x00400000, /* Discard Pause Frames */
  234. Pmcf = 0x00800000, /* Pass MAC Control Frames */
  235. Bsex = 0x02000000, /* Buffer Size Extension */
  236. Secrc = 0x04000000, /* Strip CRC from incoming packet */
  237. };
  238. enum { /* Tctl */
  239. Trst = 0x00000001, /* Transmitter Software Reset */
  240. Ten = 0x00000002, /* Transmit Enable */
  241. Psp = 0x00000008, /* Pad Short Packets */
  242. Mulr = 0x10000000, /* Allow multiple concurrent requests */
  243. CtMASK = 0x00000FF0, /* Collision Threshold */
  244. CtSHIFT = 4,
  245. ColdMASK = 0x003FF000, /* Collision Distance */
  246. ColdSHIFT = 12,
  247. Swxoff = 0x00400000, /* Sofware XOFF Transmission */
  248. Pbe = 0x00800000, /* Packet Burst Enable */
  249. Rtlc = 0x01000000, /* Re-transmit on Late Collision */
  250. Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
  251. };
  252. enum { /* [RT]xdctl */
  253. PthreshMASK = 0x0000003F, /* Prefetch Threshold */
  254. PthreshSHIFT = 0,
  255. HthreshMASK = 0x00003F00, /* Host Threshold */
  256. HthreshSHIFT = 8,
  257. WthreshMASK = 0x003F0000, /* Writeback Threshold */
  258. WthreshSHIFT = 16,
  259. Gran = 0x01000000, /* Granularity */
  260. };
  261. enum { /* Rxcsum */
  262. PcssMASK = 0x00FF, /* Packet Checksum Start */
  263. PcssSHIFT = 0,
  264. Ipofl = 0x0100, /* IP Checksum Off-load Enable */
  265. Tuofl = 0x0200, /* TCP/UDP Checksum Off-load Enable */
  266. };
  267. enum { /* Receive Delay Timer Ring */
  268. DelayMASK = 0xFFFF, /* delay timer in 1.024nS increments */
  269. DelaySHIFT = 0,
  270. Fpd = 0x80000000, /* Flush partial Descriptor Block */
  271. };
  272. typedef struct Rd { /* Receive Descriptor */
  273. uint addr[2];
  274. ushort length;
  275. ushort checksum;
  276. uchar status;
  277. uchar errors;
  278. ushort special;
  279. } Rd;
  280. enum { /* Rd status */
  281. Rdd = 0x01, /* Descriptor Done */
  282. Reop = 0x02, /* End of Packet */
  283. Ixsm = 0x04, /* Ignore Checksum Indication */
  284. Vp = 0x08, /* Packet is 802.1Q (matched VET) */
  285. Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
  286. Ipcs = 0x40, /* IP Checksum Calculated on Packet */
  287. Pif = 0x80, /* Passed in-exact filter */
  288. };
  289. enum { /* Rd errors */
  290. Ce = 0x01, /* CRC Error or Alignment Error */
  291. Se = 0x02, /* Symbol Error */
  292. Seq = 0x04, /* Sequence Error */
  293. Cxe = 0x10, /* Carrier Extension Error */
  294. Tcpe = 0x20, /* TCP/UDP Checksum Error */
  295. Ipe = 0x40, /* IP Checksum Error */
  296. Rxe = 0x80, /* RX Data Error */
  297. };
  298. typedef struct { /* Transmit Descriptor */
  299. uint addr[2]; /* Data */
  300. uint control;
  301. uint status;
  302. } Td;
  303. enum { /* Tdesc control */
  304. LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
  305. LenSHIFT = 0,
  306. DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
  307. DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
  308. PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
  309. Teop = 0x01000000, /* End of Packet (DD) */
  310. PtypeIP = 0x02000000, /* IP Packet Type (CD) */
  311. Ifcs = 0x02000000, /* Insert FCS (DD) */
  312. Tse = 0x04000000, /* TCP Segmentation Enable */
  313. Rs = 0x08000000, /* Report Status */
  314. Rps = 0x10000000, /* Report Status Sent */
  315. Dext = 0x20000000, /* Descriptor Extension */
  316. Vle = 0x40000000, /* VLAN Packet Enable */
  317. Ide = 0x80000000, /* Interrupt Delay Enable */
  318. };
  319. enum { /* Tdesc status */
  320. Tdd = 0x0001, /* Descriptor Done */
  321. Ec = 0x0002, /* Excess Collisions */
  322. Lc = 0x0004, /* Late Collision */
  323. Tu = 0x0008, /* Transmit Underrun */
  324. CssMASK = 0xFF00, /* Checksum Start Field */
  325. CssSHIFT = 8,
  326. };
  327. typedef struct {
  328. ushort *reg;
  329. ulong *reg32;
  330. int sz;
  331. } Flash;
  332. enum {
  333. /* 16 and 32-bit flash registers for ich flash parts */
  334. Bfpr = 0x00/4, /* flash base 0:12; lim 16:28 */
  335. Fsts = 0x04/2, /* flash status; Hsfs */
  336. Fctl = 0x06/2, /* flash control */
  337. Faddr = 0x08/4, /* flash address to r/w */
  338. Fdata = 0x10/4, /* data @ address */
  339. /* status register */
  340. Fdone = 1<<0, /* flash cycle done */
  341. Fcerr = 1<<1, /* cycle error; write 1 to clear */
  342. Ael = 1<<2, /* direct access error log; 1 to clear */
  343. Scip = 1<<5, /* spi cycle in progress */
  344. Fvalid = 1<<14, /* flash descriptor valid */
  345. /* control register */
  346. Fgo = 1<<0, /* start cycle */
  347. Flcycle = 1<<1, /* two bits: r=0; w=2 */
  348. Fdbc = 1<<8, /* bytes to read; 5 bits */
  349. };
  350. enum {
  351. Nrd = 256, /* power of two */
  352. Ntd = 128, /* power of two */
  353. Nrb = 512, /* private receive buffers per Ctlr */
  354. };
  355. enum {
  356. Iany,
  357. i82563,
  358. i82566,
  359. i82571,
  360. i82572,
  361. i82573,
  362. };
  363. static int rbtab[] = {
  364. 0,
  365. 9014,
  366. 1514,
  367. 9234,
  368. 9234,
  369. 8192, /* terrible performance above 8k */
  370. };
  371. static char *tname[] = {
  372. "any",
  373. "i82563",
  374. "i82566",
  375. "i82571",
  376. "i82572",
  377. "i82573",
  378. };
  379. typedef struct Ctlr Ctlr;
  380. struct Ctlr {
  381. int port;
  382. Pcidev *pcidev;
  383. Ctlr *next;
  384. int active;
  385. int started;
  386. int type;
  387. ushort eeprom[0x40];
  388. QLock alock; /* attach */
  389. void *alloc; /* receive/transmit descriptors */
  390. int nrd;
  391. int ntd;
  392. int nrb; /* how many this Ctlr has in the pool */
  393. unsigned rbsz; /* unsigned for % and / by 1024 */
  394. int *nic;
  395. Lock imlock;
  396. int im; /* interrupt mask */
  397. Rendez lrendez;
  398. int lim;
  399. QLock slock;
  400. uint statistics[Nstatistics];
  401. uint lsleep;
  402. uint lintr;
  403. uint rsleep;
  404. uint rintr;
  405. uint txdw;
  406. uint tintr;
  407. uint ixsm;
  408. uint ipcs;
  409. uint tcpcs;
  410. uint speeds[4];
  411. uchar ra[Eaddrlen]; /* receive address */
  412. ulong mta[128]; /* multicast table array */
  413. Rendez rrendez;
  414. int rim;
  415. int rdfree;
  416. Rd *rdba; /* receive descriptor base address */
  417. Block **rb; /* receive buffers */
  418. int rdh; /* receive descriptor head */
  419. int rdt; /* receive descriptor tail */
  420. int rdtr; /* receive delay timer ring value */
  421. int radv; /* receive interrupt absolute delay timer */
  422. Rendez trendez;
  423. QLock tlock;
  424. int tbusy;
  425. Td *tdba; /* transmit descriptor base address */
  426. Block **tb; /* transmit buffers */
  427. int tdh; /* transmit descriptor head */
  428. int tdt; /* transmit descriptor tail */
  429. int fcrtl;
  430. int fcrth;
  431. uint pba; /* packet buffer allocation */
  432. };
  433. #define csr32r(c, r) (*((c)->nic+((r)/4)))
  434. #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
  435. static Ctlr* i82563ctlrhead;
  436. static Ctlr* i82563ctlrtail;
  437. static Lock i82563rblock; /* free receive Blocks */
  438. static Block* i82563rbpool;
  439. static char* statistics[] = {
  440. "CRC Error",
  441. "Alignment Error",
  442. "Symbol Error",
  443. "RX Error",
  444. "Missed Packets",
  445. "Single Collision",
  446. "Excessive Collisions",
  447. "Multiple Collision",
  448. "Late Collisions",
  449. nil,
  450. "Collision",
  451. "Transmit Underrun",
  452. "Defer",
  453. "Transmit - No CRS",
  454. "Sequence Error",
  455. "Carrier Extension Error",
  456. "Receive Error Length",
  457. nil,
  458. "XON Received",
  459. "XON Transmitted",
  460. "XOFF Received",
  461. "XOFF Transmitted",
  462. "FC Received Unsupported",
  463. "Packets Received (64 Bytes)",
  464. "Packets Received (65-127 Bytes)",
  465. "Packets Received (128-255 Bytes)",
  466. "Packets Received (256-511 Bytes)",
  467. "Packets Received (512-1023 Bytes)",
  468. "Packets Received (1024-mtu Bytes)",
  469. "Good Packets Received",
  470. "Broadcast Packets Received",
  471. "Multicast Packets Received",
  472. "Good Packets Transmitted",
  473. nil,
  474. "Good Octets Received",
  475. nil,
  476. "Good Octets Transmitted",
  477. nil,
  478. nil,
  479. nil,
  480. "Receive No Buffers",
  481. "Receive Undersize",
  482. "Receive Fragment",
  483. "Receive Oversize",
  484. "Receive Jabber",
  485. "Management Packets Rx",
  486. "Management Packets Drop",
  487. "Management Packets Tx",
  488. "Total Octets Received",
  489. nil,
  490. "Total Octets Transmitted",
  491. nil,
  492. "Total Packets Received",
  493. "Total Packets Transmitted",
  494. "Packets Transmitted (64 Bytes)",
  495. "Packets Transmitted (65-127 Bytes)",
  496. "Packets Transmitted (128-255 Bytes)",
  497. "Packets Transmitted (256-511 Bytes)",
  498. "Packets Transmitted (512-1023 Bytes)",
  499. "Packets Transmitted (1024-mtu Bytes)",
  500. "Multicast Packets Transmitted",
  501. "Broadcast Packets Transmitted",
  502. "TCP Segmentation Context Transmitted",
  503. "TCP Segmentation Context Fail",
  504. "Interrupt Assertion",
  505. "Interrupt Rx Pkt Timer",
  506. "Interrupt Rx Abs Timer",
  507. "Interrupt Tx Pkt Timer",
  508. "Interrupt Tx Abs Timer",
  509. "Interrupt Tx Queue Empty",
  510. "Interrupt Tx Desc Low",
  511. "Interrupt Rx Min",
  512. "Interrupt Rx Overrun",
  513. };
  514. static long
  515. i82563ifstat(Ether* edev, void* a, long n, ulong offset)
  516. {
  517. Ctlr *ctlr;
  518. char *s, *p, *e, *stat;
  519. int i, r;
  520. uvlong tuvl, ruvl;
  521. ctlr = edev->ctlr;
  522. qlock(&ctlr->slock);
  523. p = s = malloc(2*READSTR);
  524. e = p + 2*READSTR;
  525. for(i = 0; i < Nstatistics; i++){
  526. r = csr32r(ctlr, Statistics + i*4);
  527. if((stat = statistics[i]) == nil)
  528. continue;
  529. switch(i){
  530. case Gorcl:
  531. case Gotcl:
  532. case Torl:
  533. case Totl:
  534. ruvl = r;
  535. ruvl += (uvlong)csr32r(ctlr, Statistics+(i+1)*4) << 32;
  536. tuvl = ruvl;
  537. tuvl += ctlr->statistics[i];
  538. tuvl += (uvlong)ctlr->statistics[i+1] << 32;
  539. if(tuvl == 0)
  540. continue;
  541. ctlr->statistics[i] = tuvl;
  542. ctlr->statistics[i+1] = tuvl >> 32;
  543. p = seprint(p, e, "%s: %llud %llud\n", stat, tuvl, ruvl);
  544. i++;
  545. break;
  546. default:
  547. ctlr->statistics[i] += r;
  548. if(ctlr->statistics[i] == 0)
  549. continue;
  550. p = seprint(p, e, "%s: %ud %ud\n", stat,
  551. ctlr->statistics[i], r);
  552. break;
  553. }
  554. }
  555. p = seprint(p, e, "lintr: %ud %ud\n", ctlr->lintr, ctlr->lsleep);
  556. p = seprint(p, e, "rintr: %ud %ud\n", ctlr->rintr, ctlr->rsleep);
  557. p = seprint(p, e, "tintr: %ud %ud\n", ctlr->tintr, ctlr->txdw);
  558. p = seprint(p, e, "ixcs: %ud %ud %ud\n", ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
  559. p = seprint(p, e, "rdtr: %ud\n", ctlr->rdtr);
  560. p = seprint(p, e, "radv: %ud\n", ctlr->radv);
  561. p = seprint(p, e, "ctrl: %.8ux\n", csr32r(ctlr, Ctrl));
  562. p = seprint(p, e, "ctrlext: %.8ux\n", csr32r(ctlr, Ctrlext));
  563. p = seprint(p, e, "status: %.8ux\n", csr32r(ctlr, Status));
  564. p = seprint(p, e, "txcw: %.8ux\n", csr32r(ctlr, Txcw));
  565. p = seprint(p, e, "txdctl: %.8ux\n", csr32r(ctlr, Txdctl));
  566. p = seprint(p, e, "pba: %.8ux\n", ctlr->pba);
  567. p = seprint(p, e, "speeds: 10:%ud 100:%ud 1000:%ud ?:%ud\n",
  568. ctlr->speeds[0], ctlr->speeds[1], ctlr->speeds[2], ctlr->speeds[3]);
  569. p = seprint(p, e, "type: %s\n", tname[ctlr->type]);
  570. // p = seprint(p, e, "eeprom:");
  571. // for(i = 0; i < 0x40; i++){
  572. // if(i && ((i & 7) == 0))
  573. // p = seprint(p, e, "\n ");
  574. // p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]);
  575. // }
  576. // p = seprint(p, e, "\n");
  577. USED(p);
  578. n = readstr(offset, a, n, s);
  579. free(s);
  580. qunlock(&ctlr->slock);
  581. return n;
  582. }
  583. enum {
  584. CMrdtr,
  585. CMradv,
  586. };
  587. static Cmdtab i82563ctlmsg[] = {
  588. CMrdtr, "rdtr", 2,
  589. CMradv, "radv", 2,
  590. };
  591. static long
  592. i82563ctl(Ether* edev, void* buf, long n)
  593. {
  594. int v;
  595. char *p;
  596. Ctlr *ctlr;
  597. Cmdbuf *cb;
  598. Cmdtab *ct;
  599. if((ctlr = edev->ctlr) == nil)
  600. error(Enonexist);
  601. cb = parsecmd(buf, n);
  602. if(waserror()){
  603. free(cb);
  604. nexterror();
  605. }
  606. ct = lookupcmd(cb, i82563ctlmsg, nelem(i82563ctlmsg));
  607. switch(ct->index){
  608. case CMrdtr:
  609. v = strtol(cb->f[1], &p, 0);
  610. if(v < 0 || p == cb->f[1] || v > 0xFFFF)
  611. error(Ebadarg);
  612. ctlr->rdtr = v;
  613. csr32w(ctlr, Rdtr, v);
  614. break;
  615. case CMradv:
  616. v = strtol(cb->f[1], &p, 0);
  617. if(v < 0 || p == cb->f[1] || v > 0xFFFF)
  618. error(Ebadarg);
  619. ctlr->radv = v;
  620. csr32w(ctlr, Radv, v);
  621. }
  622. free(cb);
  623. poperror();
  624. return n;
  625. }
  626. static void
  627. i82563promiscuous(void* arg, int on)
  628. {
  629. int rctl;
  630. Ctlr *ctlr;
  631. Ether *edev;
  632. edev = arg;
  633. ctlr = edev->ctlr;
  634. rctl = csr32r(ctlr, Rctl);
  635. rctl &= ~MoMASK;
  636. if(on)
  637. rctl |= Upe|Mpe;
  638. else
  639. rctl &= ~(Upe|Mpe);
  640. csr32w(ctlr, Rctl, rctl);
  641. }
  642. static void
  643. i82563multicast(void* arg, uchar* addr, int on)
  644. {
  645. int bit, x;
  646. Ctlr *ctlr;
  647. Ether *edev;
  648. edev = arg;
  649. ctlr = edev->ctlr;
  650. x = addr[5]>>1;
  651. if(ctlr->type == i82566)
  652. x &= 31;
  653. bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
  654. if(on)
  655. ctlr->mta[x] |= 1<<bit;
  656. else
  657. ctlr->mta[x] &= ~(1<<bit);
  658. csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
  659. }
  660. static Block*
  661. i82563rballoc(void)
  662. {
  663. Block *bp;
  664. ilock(&i82563rblock);
  665. if((bp = i82563rbpool) != nil){
  666. i82563rbpool = bp->next;
  667. bp->next = nil;
  668. }
  669. iunlock(&i82563rblock);
  670. return bp;
  671. }
  672. static void
  673. i82563rbfree(Block* b)
  674. {
  675. b->rp = b->wp = (uchar*)PGROUND((uintptr)b->base);
  676. ilock(&i82563rblock);
  677. b->next = i82563rbpool;
  678. i82563rbpool = b;
  679. iunlock(&i82563rblock);
  680. }
  681. static void
  682. i82563im(Ctlr* ctlr, int im)
  683. {
  684. ilock(&ctlr->imlock);
  685. ctlr->im |= im;
  686. csr32w(ctlr, Ims, ctlr->im);
  687. iunlock(&ctlr->imlock);
  688. }
  689. static void
  690. i82563txinit(Ctlr* ctlr)
  691. {
  692. int i, r;
  693. Block *bp;
  694. csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp | 66<<ColdSHIFT | Mulr);
  695. csr32w(ctlr, Tipg, 6<<20 | 8<<10 | 8); /* yb sez: 0x702008 */
  696. csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
  697. csr32w(ctlr, Tdbah, 0);
  698. csr32w(ctlr, Tdlen, ctlr->ntd * sizeof(Td));
  699. ctlr->tdh = PREV(0, ctlr->ntd);
  700. csr32w(ctlr, Tdh, 0);
  701. ctlr->tdt = 0;
  702. csr32w(ctlr, Tdt, 0);
  703. for(i = 0; i < ctlr->ntd; i++){
  704. if((bp = ctlr->tb[i]) != nil){
  705. ctlr->tb[i] = nil;
  706. freeb(bp);
  707. }
  708. memset(&ctlr->tdba[i], 0, sizeof(Td));
  709. }
  710. csr32w(ctlr, Tidv, 128);
  711. r = csr32r(ctlr, Txdctl);
  712. r &= ~WthreshMASK;
  713. r |= 4<<WthreshSHIFT | 4<<PthreshSHIFT;
  714. csr32w(ctlr, Tadv, 64);
  715. csr32w(ctlr, Txdctl, r);
  716. r = csr32r(ctlr, Tctl);
  717. r |= Ten;
  718. csr32w(ctlr, Tctl, r);
  719. // if(ctlr->type == i82671)
  720. // csr32w(ctlr, Tarc0, csr32r(ctlr, Tarc0) | 7<<24); /* yb sez? */
  721. }
  722. #define Next(x, m) (((x)+1) & (m))
  723. static int
  724. i82563cleanup(Ctlr *c)
  725. {
  726. Block *b;
  727. int tdh, m, n;
  728. tdh = c->tdh;
  729. m = c->ntd-1;
  730. while(c->tdba[n = Next(tdh, m)].status & Tdd){
  731. tdh = n;
  732. if((b = c->tb[tdh]) != nil){
  733. c->tb[tdh] = nil;
  734. freeb(b);
  735. }else
  736. iprint("82563 tx underrun!\n");
  737. c->tdba[tdh].status = 0;
  738. }
  739. return c->tdh = tdh;
  740. }
  741. static void
  742. i82563transmit(Ether* edev)
  743. {
  744. Td *td;
  745. Block *bp;
  746. Ctlr *ctlr;
  747. int tdh, tdt, m;
  748. ctlr = edev->ctlr;
  749. qlock(&ctlr->tlock);
  750. /*
  751. * Free any completed packets
  752. */
  753. tdh = i82563cleanup(ctlr);
  754. /*
  755. * Try to fill the ring back up.
  756. */
  757. tdt = ctlr->tdt;
  758. m = ctlr->ntd-1;
  759. for(;;){
  760. if(Next(tdt, m) == tdh){
  761. ctlr->txdw++;
  762. i82563im(ctlr, Txdw);
  763. break;
  764. }
  765. if((bp = qget(edev->oq)) == nil)
  766. break;
  767. td = &ctlr->tdba[tdt];
  768. td->addr[0] = PCIWADDR(bp->rp);
  769. td->control = Ide|Rs|Ifcs|Teop|BLEN(bp);
  770. ctlr->tb[tdt] = bp;
  771. tdt = Next(tdt, m);
  772. }
  773. if(ctlr->tdt != tdt){
  774. ctlr->tdt = tdt;
  775. csr32w(ctlr, Tdt, tdt);
  776. }
  777. qunlock(&ctlr->tlock);
  778. }
  779. static void
  780. i82563replenish(Ctlr* ctlr)
  781. {
  782. Rd *rd;
  783. int rdt, m;
  784. Block *bp;
  785. rdt = ctlr->rdt;
  786. m = ctlr->nrd-1;
  787. while(Next(rdt, m) != ctlr->rdh){
  788. rd = &ctlr->rdba[rdt];
  789. if(ctlr->rb[rdt] != nil){
  790. iprint("82563: tx overrun\n");
  791. break;
  792. }
  793. bp = i82563rballoc();
  794. if(bp == nil){
  795. iprint("82563: no available buffers\n");
  796. break;
  797. }
  798. ctlr->rb[rdt] = bp;
  799. rd->addr[0] = PCIWADDR(bp->rp);
  800. // rd->addr[1] = 0;
  801. rd->status = 0;
  802. ctlr->rdfree++;
  803. rdt = Next(rdt, m);
  804. }
  805. ctlr->rdt = rdt;
  806. csr32w(ctlr, Rdt, rdt);
  807. }
  808. static void
  809. i82563rxinit(Ctlr* ctlr)
  810. {
  811. int i;
  812. Block *bp;
  813. if(ctlr->rbsz <= 2048)
  814. csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
  815. else if(ctlr->rbsz <= 8192)
  816. csr32w(ctlr, Rctl, Lpe|Dpf|Bsize8192|Bsex|Bam|RdtmsHALF|Secrc);
  817. else if(ctlr->rbsz <= 12*1024){
  818. i = ctlr->rbsz / 1024;
  819. if(ctlr->rbsz % 1024)
  820. i++;
  821. csr32w(ctlr, Rctl, Lpe|Dpf|BsizeFlex*i|Bam|RdtmsHALF|Secrc);
  822. }else
  823. csr32w(ctlr, Rctl, Lpe|Dpf|Bsize16384|Bsex|Bam|RdtmsHALF|Secrc);
  824. if(ctlr->type == i82573)
  825. csr32w(ctlr, Ert, 1024/8);
  826. if(ctlr->type == i82566)
  827. csr32w(ctlr, Pbs, 16);
  828. csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
  829. csr32w(ctlr, Rdbah, 0);
  830. csr32w(ctlr, Rdlen, ctlr->nrd * sizeof(Rd));
  831. ctlr->rdh = 0;
  832. csr32w(ctlr, Rdh, 0);
  833. ctlr->rdt = 0;
  834. csr32w(ctlr, Rdt, 0);
  835. ctlr->rdtr = 25;
  836. ctlr->radv = 500;
  837. csr32w(ctlr, Rdtr, ctlr->rdtr);
  838. csr32w(ctlr, Radv, ctlr->radv);
  839. for(i = 0; i < ctlr->nrd; i++)
  840. if((bp = ctlr->rb[i]) != nil){
  841. ctlr->rb[i] = nil;
  842. freeb(bp);
  843. }
  844. i82563replenish(ctlr);
  845. csr32w(ctlr, Rxdctl, 2<<WthreshSHIFT | 2<<PthreshSHIFT);
  846. /*
  847. * Enable checksum offload.
  848. */
  849. csr32w(ctlr, Rxcsum, Tuofl | Ipofl | ETHERHDRSIZE<<PcssSHIFT);
  850. }
  851. static int
  852. i82563rim(void* ctlr)
  853. {
  854. return ((Ctlr*)ctlr)->rim != 0;
  855. }
  856. static void
  857. i82563rproc(void* arg)
  858. {
  859. Rd *rd;
  860. Block *bp;
  861. Ctlr *ctlr;
  862. int r, m, rdh, rim;
  863. Ether *edev;
  864. edev = arg;
  865. ctlr = edev->ctlr;
  866. i82563rxinit(ctlr);
  867. r = csr32r(ctlr, Rctl);
  868. r |= Ren;
  869. csr32w(ctlr, Rctl, r);
  870. m = ctlr->nrd-1;
  871. for(;;){
  872. i82563im(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
  873. ctlr->rsleep++;
  874. // coherence();
  875. sleep(&ctlr->rrendez, i82563rim, ctlr);
  876. rdh = ctlr->rdh;
  877. for(;;){
  878. rd = &ctlr->rdba[rdh];
  879. rim = ctlr->rim;
  880. ctlr->rim = 0;
  881. if(!(rd->status & Rdd))
  882. break;
  883. /*
  884. * Accept eop packets with no errors.
  885. * With no errors and the Ixsm bit set,
  886. * the descriptor status Tpcs and Ipcs bits give
  887. * an indication of whether the checksums were
  888. * calculated and valid.
  889. */
  890. if (bp = ctlr->rb[rdh]) {
  891. if((rd->status & Reop) && rd->errors == 0){
  892. bp->wp += rd->length;
  893. bp->lim = bp->wp; /* lie like a dog. */
  894. if(!(rd->status & Ixsm)){
  895. ctlr->ixsm++;
  896. if(rd->status & Ipcs){
  897. /*
  898. * IP checksum calculated
  899. * (and valid as errors == 0).
  900. */
  901. ctlr->ipcs++;
  902. bp->flag |= Bipck;
  903. }
  904. if(rd->status & Tcpcs){
  905. /*
  906. * TCP/UDP checksum calculated
  907. * (and valid as errors == 0).
  908. */
  909. ctlr->tcpcs++;
  910. bp->flag |= Btcpck|Budpck;
  911. }
  912. bp->checksum = rd->checksum;
  913. bp->flag |= Bpktck;
  914. }
  915. etheriq(edev, bp, 1);
  916. } else
  917. freeb(bp);
  918. ctlr->rb[rdh] = nil;
  919. }
  920. rd->status = 0;
  921. ctlr->rdfree--;
  922. ctlr->rdh = rdh = Next(rdh, m);
  923. if(ctlr->nrd-ctlr->rdfree >= 32 || (rim & Rxdmt0))
  924. i82563replenish(ctlr);
  925. }
  926. }
  927. }
  928. static int
  929. i82563lim(void* c)
  930. {
  931. return ((Ctlr*)c)->lim != 0;
  932. }
  933. static int speedtab[] = {
  934. 10, 100, 1000, 0
  935. };
  936. static uint
  937. phyread(Ctlr *c, int reg)
  938. {
  939. uint phy, i;
  940. csr32w(c, Mdic, MDIrop | 1<<MDIpSHIFT | reg<<MDIrSHIFT);
  941. phy = 0;
  942. for(i = 0; i < 64; i++){
  943. phy = csr32r(c, Mdic);
  944. if(phy & (MDIe|MDIready))
  945. break;
  946. microdelay(1);
  947. }
  948. if((phy & (MDIe|MDIready)) != MDIready)
  949. return ~0;
  950. return phy & 0xffff;
  951. }
  952. static uint
  953. phywrite(Ctlr *c, int reg, ushort val)
  954. {
  955. uint phy, i;
  956. csr32w(c, Mdic, MDIwop | 1<<MDIpSHIFT | reg<<MDIrSHIFT | val);
  957. phy = 0;
  958. for(i = 0; i < 64; i++){
  959. phy = csr32r(c, Mdic);
  960. if(phy & (MDIe|MDIready))
  961. break;
  962. microdelay(1);
  963. }
  964. if((phy & (MDIe|MDIready)) != MDIready)
  965. return ~0;
  966. return 0;
  967. }
  968. static void
  969. i82563lproc(void *v)
  970. {
  971. Ether *e;
  972. Ctlr *c;
  973. uint phy, i;
  974. e = v;
  975. c = e->ctlr;
  976. phy = phyread(c, Phyier);
  977. if(phy != ~0){
  978. phy |= 1<<14;
  979. phywrite(c, Phyier, phy);
  980. }
  981. for(;;){
  982. phy = phyread(c, Physsr);
  983. if(phy == ~0)
  984. goto next;
  985. e->link = (phy & Rtlink) != 0;
  986. i = (phy>>14) & 3;
  987. switch(c->type){
  988. case i82563:
  989. if((phy&Phyan) == 0)
  990. goto next;
  991. break;
  992. case i82571:
  993. case i82572:
  994. i = (i-1) & 3;
  995. break;
  996. }
  997. c->speeds[i]++;
  998. e->mbps = speedtab[i];
  999. next:
  1000. c->lim = 0;
  1001. i82563im(c, Lsc);
  1002. c->lsleep++;
  1003. sleep(&c->lrendez, i82563lim, c);
  1004. }
  1005. }
  1006. static void
  1007. i82563tproc(void *v)
  1008. {
  1009. Ether *e;
  1010. Ctlr *c;
  1011. e = v;
  1012. c = e->ctlr;
  1013. for(;;){
  1014. sleep(&c->trendez, return0, 0);
  1015. i82563transmit(e);
  1016. }
  1017. }
  1018. static void
  1019. i82563attach(Ether* edev)
  1020. {
  1021. Block *bp;
  1022. Ctlr *ctlr;
  1023. char name[KNAMELEN];
  1024. ctlr = edev->ctlr;
  1025. qlock(&ctlr->alock);
  1026. if(ctlr->alloc != nil){
  1027. qunlock(&ctlr->alock);
  1028. return;
  1029. }
  1030. ctlr->nrd = Nrd;
  1031. ctlr->ntd = Ntd;
  1032. ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 255);
  1033. if(ctlr->alloc == nil){
  1034. qunlock(&ctlr->alock);
  1035. return;
  1036. }
  1037. ctlr->rdba = (Rd*)ROUNDUP((ulong)ctlr->alloc, 256);
  1038. ctlr->tdba = (Td*)(ctlr->rdba + ctlr->nrd);
  1039. ctlr->rb = malloc(ctlr->nrd * sizeof(Block*));
  1040. ctlr->tb = malloc(ctlr->ntd * sizeof(Block*));
  1041. if(waserror()){
  1042. while(ctlr->nrb > 0){
  1043. bp = i82563rballoc();
  1044. bp->free = nil;
  1045. freeb(bp);
  1046. ctlr->nrb--;
  1047. }
  1048. free(ctlr->tb);
  1049. ctlr->tb = nil;
  1050. free(ctlr->rb);
  1051. ctlr->rb = nil;
  1052. free(ctlr->alloc);
  1053. ctlr->alloc = nil;
  1054. qunlock(&ctlr->alock);
  1055. nexterror();
  1056. }
  1057. for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){
  1058. if((bp = allocb(ctlr->rbsz + BY2PG)) == nil)
  1059. break;
  1060. bp->free = i82563rbfree;
  1061. freeb(bp);
  1062. }
  1063. snprint(name, sizeof name, "#l%dl", edev->ctlrno);
  1064. kproc(name, i82563lproc, edev);
  1065. snprint(name, sizeof name, "#l%dr", edev->ctlrno);
  1066. kproc(name, i82563rproc, edev);
  1067. snprint(name, sizeof name, "#l%dt", edev->ctlrno);
  1068. kproc(name, i82563tproc, edev);
  1069. i82563txinit(ctlr);
  1070. qunlock(&ctlr->alock);
  1071. poperror();
  1072. }
  1073. static void
  1074. i82563interrupt(Ureg*, void* arg)
  1075. {
  1076. Ctlr *ctlr;
  1077. Ether *edev;
  1078. int icr, im;
  1079. edev = arg;
  1080. ctlr = edev->ctlr;
  1081. ilock(&ctlr->imlock);
  1082. csr32w(ctlr, Imc, ~0);
  1083. im = ctlr->im;
  1084. while(icr = csr32r(ctlr, Icr) & ctlr->im){
  1085. if(icr & Lsc){
  1086. im &= ~Lsc;
  1087. ctlr->lim = icr & Lsc;
  1088. wakeup(&ctlr->lrendez);
  1089. ctlr->lintr++;
  1090. }
  1091. if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack)){
  1092. ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
  1093. im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq|Ack);
  1094. wakeup(&ctlr->rrendez);
  1095. ctlr->rintr++;
  1096. }
  1097. if(icr & Txdw){
  1098. im &= ~Txdw;
  1099. ctlr->tintr++;
  1100. wakeup(&ctlr->trendez);
  1101. }
  1102. }
  1103. ctlr->im = im;
  1104. csr32w(ctlr, Ims, im);
  1105. iunlock(&ctlr->imlock);
  1106. }
  1107. static int
  1108. i82563detach(Ctlr* ctlr)
  1109. {
  1110. int r, timeo;
  1111. /* balance rx/tx packet buffer */
  1112. if(ctlr->rbsz > 8192 && (ctlr->type == i82563 || ctlr->type == i82571 ||
  1113. ctlr->type == i82572)){
  1114. ctlr->pba = csr32r(ctlr, Pba);
  1115. r = ctlr->pba >> 16;
  1116. r += ctlr->pba & 0xffff;
  1117. r >>= 1;
  1118. csr32w(ctlr, Pba, r);
  1119. } else if(ctlr->type == i82573 && ctlr->rbsz > 1514)
  1120. csr32w(ctlr, Pba, 14);
  1121. ctlr->pba = csr32r(ctlr, Pba);
  1122. /*
  1123. * Perform a device reset to get the chip back to the
  1124. * power-on state, followed by an EEPROM reset to read
  1125. * the defaults for some internal registers.
  1126. */
  1127. csr32w(ctlr, Imc, ~0);
  1128. csr32w(ctlr, Rctl, 0);
  1129. csr32w(ctlr, Tctl, 0);
  1130. delay(10);
  1131. r = csr32r(ctlr, Ctrl);
  1132. if(ctlr->type == i82566)
  1133. r |= Phyrst;
  1134. csr32w(ctlr, Ctrl, Devrst | r);
  1135. delay(1);
  1136. for(timeo = 0; timeo < 1000; timeo++){
  1137. if(!(csr32r(ctlr, Ctrl) & Devrst))
  1138. break;
  1139. delay(1);
  1140. }
  1141. if(csr32r(ctlr, Ctrl) & Devrst)
  1142. return -1;
  1143. r = csr32r(ctlr, Ctrl);
  1144. csr32w(ctlr, Ctrl, Slu|r);
  1145. r = csr32r(ctlr, Ctrlext);
  1146. csr32w(ctlr, Ctrlext, r|Eerst);
  1147. delay(1);
  1148. for(timeo = 0; timeo < 1000; timeo++){
  1149. if(!(csr32r(ctlr, Ctrlext) & Eerst))
  1150. break;
  1151. delay(1);
  1152. }
  1153. if(csr32r(ctlr, Ctrlext) & Eerst)
  1154. return -1;
  1155. csr32w(ctlr, Imc, ~0);
  1156. delay(1);
  1157. for(timeo = 0; timeo < 1000; timeo++){
  1158. if(!csr32r(ctlr, Icr))
  1159. break;
  1160. delay(1);
  1161. }
  1162. if(csr32r(ctlr, Icr))
  1163. return -1;
  1164. return 0;
  1165. }
  1166. static void
  1167. i82563shutdown(Ether* ether)
  1168. {
  1169. i82563detach(ether->ctlr);
  1170. }
  1171. static ushort
  1172. eeread(Ctlr *ctlr, int adr)
  1173. {
  1174. csr32w(ctlr, Eerd, EEstart | adr << 2);
  1175. while ((csr32r(ctlr, Eerd) & EEdone) == 0)
  1176. ;
  1177. return csr32r(ctlr, Eerd) >> 16;
  1178. }
  1179. static int
  1180. eeload(Ctlr *ctlr)
  1181. {
  1182. ushort sum;
  1183. int data, adr;
  1184. sum = 0;
  1185. for (adr = 0; adr < 0x40; adr++) {
  1186. data = eeread(ctlr, adr);
  1187. ctlr->eeprom[adr] = data;
  1188. sum += data;
  1189. }
  1190. return sum;
  1191. }
  1192. static int
  1193. fcycle(Ctlr *, Flash *f)
  1194. {
  1195. ushort s, i;
  1196. s = f->reg[Fsts];
  1197. if((s&Fvalid) == 0)
  1198. return -1;
  1199. f->reg[Fsts] |= Fcerr | Ael;
  1200. for(i = 0; i < 10; i++){
  1201. if((s&Scip) == 0)
  1202. return 0;
  1203. delay(1);
  1204. s = f->reg[Fsts];
  1205. }
  1206. return -1;
  1207. }
  1208. static int
  1209. fread(Ctlr *c, Flash *f, int ladr)
  1210. {
  1211. ushort s;
  1212. delay(1);
  1213. if(fcycle(c, f) == -1)
  1214. return -1;
  1215. f->reg[Fsts] |= Fdone;
  1216. f->reg32[Faddr] = ladr;
  1217. /* setup flash control register */
  1218. s = f->reg[Fctl];
  1219. s &= ~(0x1f << 8);
  1220. s |= (2-1) << 8; /* 2 bytes */
  1221. s &= ~(2*Flcycle); /* read */
  1222. f->reg[Fctl] = s | Fgo;
  1223. while((f->reg[Fsts] & Fdone) == 0)
  1224. ;
  1225. if(f->reg[Fsts] & (Fcerr|Ael))
  1226. return -1;
  1227. return f->reg32[Fdata] & 0xffff;
  1228. }
  1229. static int
  1230. fload(Ctlr *c)
  1231. {
  1232. ulong data, io, r, adr;
  1233. ushort sum;
  1234. Flash f;
  1235. io = c->pcidev->mem[1].bar & ~0x0f;
  1236. f.reg = vmap(io, c->pcidev->mem[1].size);
  1237. if(f.reg == nil)
  1238. return -1;
  1239. f.reg32 = (ulong*)f.reg;
  1240. f.sz = f.reg32[Bfpr];
  1241. if(csr32r(c, Eec) & (1<<22)){
  1242. r = (f.sz >> 16) & 0x1fff;
  1243. r = (r+1) << 12;
  1244. }else
  1245. r = (f.sz & 0x1fff) << 12;
  1246. sum = 0;
  1247. for (adr = 0; adr < 0x40; adr++) {
  1248. data = fread(c, &f, r + adr*2);
  1249. if(data == -1)
  1250. break;
  1251. c->eeprom[adr] = data;
  1252. sum += data;
  1253. }
  1254. vunmap(f.reg, c->pcidev->mem[1].size);
  1255. return sum;
  1256. }
  1257. static int
  1258. i82563reset(Ctlr *ctlr)
  1259. {
  1260. int i, r;
  1261. if(i82563detach(ctlr))
  1262. return -1;
  1263. if(ctlr->type == i82566)
  1264. r = fload(ctlr);
  1265. else
  1266. r = eeload(ctlr);
  1267. if (r != 0 && r != 0xBABA){
  1268. print("%s: bad EEPROM checksum - %#.4ux\n",
  1269. tname[ctlr->type], r);
  1270. return -1;
  1271. }
  1272. for(i = Ea; i < Eaddrlen/2; i++){
  1273. ctlr->ra[2*i] = ctlr->eeprom[i];
  1274. ctlr->ra[2*i+1] = ctlr->eeprom[i] >> 8;
  1275. }
  1276. r = (csr32r(ctlr, Status) & Lanid) >> 2;
  1277. ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */
  1278. r = ctlr->ra[3]<<24 | ctlr->ra[2]<<16 | ctlr->ra[1]<<8 | ctlr->ra[0];
  1279. csr32w(ctlr, Ral, r);
  1280. r = 0x80000000 | ctlr->ra[5]<<8 | ctlr->ra[4];
  1281. csr32w(ctlr, Rah, r);
  1282. for(i = 1; i < 16; i++){
  1283. csr32w(ctlr, Ral+i*8, 0);
  1284. csr32w(ctlr, Rah+i*8, 0);
  1285. }
  1286. memset(ctlr->mta, 0, sizeof(ctlr->mta));
  1287. for(i = 0; i < 128; i++)
  1288. csr32w(ctlr, Mta + i*4, 0);
  1289. csr32w(ctlr, Fcal, 0x00C28001);
  1290. csr32w(ctlr, Fcah, 0x0100);
  1291. csr32w(ctlr, Fct, 0x8808);
  1292. csr32w(ctlr, Fcttv, 0x0100);
  1293. csr32w(ctlr, Fcrtl, ctlr->fcrtl);
  1294. csr32w(ctlr, Fcrth, ctlr->fcrth);
  1295. return 0;
  1296. }
  1297. static void
  1298. i82563pci(void)
  1299. {
  1300. int type;
  1301. ulong io;
  1302. void *mem;
  1303. Pcidev *p;
  1304. Ctlr *ctlr;
  1305. p = nil;
  1306. while(p = pcimatch(p, 0x8086, 0)){
  1307. switch(p->did){
  1308. default:
  1309. continue;
  1310. case 0x1096:
  1311. case 0x10ba:
  1312. type = i82563;
  1313. break;
  1314. case 0x1049: /* mm */
  1315. case 0x104a: /* dm */
  1316. case 0x104d: /* v */
  1317. type = i82566;
  1318. break;
  1319. case 0x10a4:
  1320. case 0x105e:
  1321. type = i82571;
  1322. break;
  1323. case 0x10b9: /* sic, 82572 */
  1324. type = i82572;
  1325. break;
  1326. case 0x108b: /* e */
  1327. case 0x108c: /* e (iamt) */
  1328. case 0x109a: /* l */
  1329. type = i82573;
  1330. break;
  1331. }
  1332. io = p->mem[0].bar & ~0x0F;
  1333. mem = vmap(io, p->mem[0].size);
  1334. if(mem == nil){
  1335. print("%s: can't map %.8lux\n", tname[type],
  1336. p->mem[0].bar);
  1337. continue;
  1338. }
  1339. ctlr = malloc(sizeof(Ctlr));
  1340. ctlr->port = io;
  1341. ctlr->pcidev = p;
  1342. ctlr->type = type;
  1343. ctlr->rbsz = rbtab[type];
  1344. ctlr->nic = mem;
  1345. if(i82563reset(ctlr)){
  1346. free(ctlr);
  1347. continue;
  1348. }
  1349. pcisetbme(p);
  1350. if(i82563ctlrhead != nil)
  1351. i82563ctlrtail->next = ctlr;
  1352. else
  1353. i82563ctlrhead = ctlr;
  1354. i82563ctlrtail = ctlr;
  1355. }
  1356. }
  1357. static int
  1358. pnp(Ether* edev, int type)
  1359. {
  1360. Ctlr *ctlr;
  1361. static int done;
  1362. if(!done) {
  1363. i82563pci();
  1364. done = 1;
  1365. }
  1366. /*
  1367. * Any adapter matches if no edev->port is supplied,
  1368. * otherwise the ports must match.
  1369. */
  1370. for(ctlr = i82563ctlrhead; ctlr != nil; ctlr = ctlr->next){
  1371. if(ctlr->active)
  1372. continue;
  1373. if(type != Iany && ctlr->type != type)
  1374. continue;
  1375. if(edev->port == 0 || edev->port == ctlr->port){
  1376. ctlr->active = 1;
  1377. break;
  1378. }
  1379. }
  1380. if(ctlr == nil)
  1381. return -1;
  1382. edev->ctlr = ctlr;
  1383. edev->port = ctlr->port;
  1384. edev->irq = ctlr->pcidev->intl;
  1385. edev->tbdf = ctlr->pcidev->tbdf;
  1386. edev->mbps = 1000;
  1387. edev->maxmtu = ctlr->rbsz;
  1388. memmove(edev->ea, ctlr->ra, Eaddrlen);
  1389. /*
  1390. * Linkage to the generic ethernet driver.
  1391. */
  1392. edev->attach = i82563attach;
  1393. edev->transmit = i82563transmit;
  1394. edev->interrupt = i82563interrupt;
  1395. edev->ifstat = i82563ifstat;
  1396. edev->ctl = i82563ctl;
  1397. edev->arg = edev;
  1398. edev->promiscuous = i82563promiscuous;
  1399. edev->shutdown = i82563shutdown;
  1400. edev->multicast = i82563multicast;
  1401. return 0;
  1402. }
  1403. static int
  1404. anypnp(Ether *e)
  1405. {
  1406. return pnp(e, Iany);
  1407. }
  1408. static int
  1409. i82563pnp(Ether *e)
  1410. {
  1411. return pnp(e, i82563);
  1412. }
  1413. static int
  1414. i82566pnp(Ether *e)
  1415. {
  1416. return pnp(e, i82566);
  1417. }
  1418. static int
  1419. i82571pnp(Ether *e)
  1420. {
  1421. return pnp(e, i82571);
  1422. }
  1423. static int
  1424. i82572pnp(Ether *e)
  1425. {
  1426. return pnp(e, i82572);
  1427. }
  1428. static int
  1429. i82573pnp(Ether *e)
  1430. {
  1431. return pnp(e, i82573);
  1432. }
  1433. void
  1434. ether82563link(void)
  1435. {
  1436. /* recognise lots of model numbers for debugging assistance */
  1437. addethercard("i82563", i82563pnp);
  1438. addethercard("i82566", i82566pnp);
  1439. addethercard("i82571", i82571pnp);
  1440. addethercard("i82572", i82572pnp);
  1441. addethercard("i82573", i82573pnp);
  1442. addethercard("igbepcie", anypnp);
  1443. }