l.s 29 KB

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  1. #include "mem.h"
  2. #include "/sys/src/boot/pc/x16.h"
  3. #undef DELAY
  4. #define PADDR(a) ((a) & ~KZERO)
  5. #define KADDR(a) (KZERO|(a))
  6. /*
  7. * Some machine instructions not handled by 8[al].
  8. */
  9. #define OP16 BYTE $0x66
  10. #define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
  11. #define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
  12. #define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
  13. #define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
  14. #define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) */
  15. #define HLT BYTE $0xF4
  16. #define INVLPG BYTE $0x0F; BYTE $0x01; BYTE $0x39 /* INVLPG (%ecx) */
  17. /*
  18. * Macros for calculating offsets within the page directory base
  19. * and page tables. Note that these are assembler-specific hence
  20. * the '<<2'.
  21. */
  22. #define PDO(a) (((((a))>>22) & 0x03FF)<<2)
  23. #define PTO(a) (((((a))>>12) & 0x03FF)<<2)
  24. /*
  25. * For backwards compatiblity with 9load - should go away when 9load is changed
  26. * 9load currently sets up the mmu, however the first 16MB of memory is identity
  27. * mapped, so behave as if the mmu was not setup
  28. */
  29. TEXT _startKADDR(SB), $0
  30. MOVL $_startPADDR(SB), AX
  31. ANDL $~KZERO, AX
  32. JMP* AX
  33. /*
  34. * Must be 4-byte aligned.
  35. */
  36. TEXT _multibootheader(SB), $0
  37. LONG $0x1BADB002 /* magic */
  38. LONG $0x00010003 /* flags */
  39. LONG $-(0x1BADB002 + 0x00010003) /* checksum */
  40. LONG $_multibootheader-KZERO(SB) /* header_addr */
  41. LONG $_startKADDR-KZERO(SB) /* load_addr */
  42. LONG $edata-KZERO(SB) /* load_end_addr */
  43. LONG $end-KZERO(SB) /* bss_end_addr */
  44. LONG $_startKADDR-KZERO(SB) /* entry_addr */
  45. LONG $0 /* mode_type */
  46. LONG $0 /* width */
  47. LONG $0 /* height */
  48. LONG $0 /* depth */
  49. /*
  50. * In protected mode with paging turned off and segment registers setup
  51. * to linear map all memory. Entered via a jump to PADDR(entry),
  52. * the physical address of the virtual kernel entry point of KADDR(entry).
  53. * Make the basic page tables for processor 0. Six pages are needed for
  54. * the basic set:
  55. * a page directory;
  56. * page tables for mapping the first 8MB of physical memory to KZERO;
  57. * a page for the GDT;
  58. * virtual and physical pages for mapping the Mach structure.
  59. * The remaining PTEs will be allocated later when memory is sized.
  60. * An identity mmu map is also needed for the switch to virtual mode.
  61. * This identity mapping is removed once the MMU is going and the JMP has
  62. * been made to virtual memory.
  63. */
  64. TEXT _startPADDR(SB), $0
  65. CLI /* make sure interrupts are off */
  66. /* set up the gdt so we have sane plan 9 style gdts. */
  67. MOVL $tgdtptr(SB), AX
  68. ANDL $~KZERO, AX
  69. MOVL (AX), GDTR
  70. MOVW $1, AX
  71. MOVW AX, MSW
  72. /* clear prefetch queue (weird code to avoid optimizations) */
  73. DELAY
  74. /* set segs to something sane (avoid traps later) */
  75. MOVW $(1<<3), AX
  76. MOVW AX, DS
  77. MOVW AX, SS
  78. MOVW AX, ES
  79. MOVW AX, FS
  80. MOVW AX, GS
  81. /* JMP $(2<<3):$mode32bit(SB) /**/
  82. BYTE $0xEA
  83. LONG $mode32bit-KZERO(SB)
  84. WORD $(2<<3)
  85. /*
  86. * gdt to get us to 32-bit/segmented/unpaged mode
  87. */
  88. TEXT tgdt(SB), $0
  89. /* null descriptor */
  90. LONG $0
  91. LONG $0
  92. /* data segment descriptor for 4 gigabytes (PL 0) */
  93. LONG $(0xFFFF)
  94. LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
  95. /* exec segment descriptor for 4 gigabytes (PL 0) */
  96. LONG $(0xFFFF)
  97. LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
  98. /*
  99. * pointer to initial gdt
  100. * Note the -KZERO which puts the physical address in the gdtptr.
  101. * that's needed as we start executing in physical addresses.
  102. */
  103. TEXT tgdtptr(SB), $0
  104. WORD $(3*8)
  105. LONG $tgdt-KZERO(SB)
  106. TEXT m0rgdtptr(SB), $0
  107. WORD $(NGDT*8-1)
  108. LONG $(CPU0GDT-KZERO)
  109. TEXT m0gdtptr(SB), $0
  110. WORD $(NGDT*8-1)
  111. LONG $CPU0GDT
  112. TEXT m0idtptr(SB), $0
  113. WORD $(256*8-1)
  114. LONG $IDTADDR
  115. TEXT mode32bit(SB), $0
  116. /* At this point, the GDT setup is done. */
  117. MOVL $PADDR(CPU0PDB), DI /* clear 4 pages for the tables etc. */
  118. XORL AX, AX
  119. MOVL $(4*BY2PG), CX
  120. SHRL $2, CX
  121. CLD
  122. REP; STOSL
  123. MOVL $PADDR(CPU0PDB), AX
  124. ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
  125. MOVL $PADDR(CPU0PTE), (AX) /* PTE's for KZERO */
  126. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  127. ORL BX, (AX)
  128. ADDL $4, AX
  129. MOVL $PADDR(CPU0PTE1), (AX) /* PTE's for KZERO+4MB */
  130. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  131. ORL BX, (AX)
  132. MOVL $PADDR(CPU0PTE), AX /* first page of page table */
  133. MOVL $1024, CX /* 1024 pages in 4MB */
  134. _setpte:
  135. MOVL BX, (AX)
  136. ADDL $(1<<PGSHIFT), BX
  137. ADDL $4, AX
  138. LOOP _setpte
  139. MOVL $PADDR(CPU0PTE1), AX /* second page of page table */
  140. MOVL $1024, CX /* 1024 pages in 4MB */
  141. _setpte1:
  142. MOVL BX, (AX)
  143. ADDL $(1<<PGSHIFT), BX
  144. ADDL $4, AX
  145. LOOP _setpte1
  146. MOVL $PADDR(CPU0PTE), AX
  147. ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
  148. MOVL $PADDR(CPU0MACH), (AX) /* PTE for Mach */
  149. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  150. ORL BX, (AX)
  151. /*
  152. * Now ready to use the new map. Make sure the processor options are what is wanted.
  153. * It is necessary on some processors to immediately follow mode switching with a JMP instruction
  154. * to clear the prefetch queues.
  155. */
  156. MOVL $PADDR(CPU0PDB), CX /* load address of page directory */
  157. MOVL (PDO(KZERO))(CX), DX /* double-map KZERO at 0 */
  158. MOVL DX, (PDO(0))(CX)
  159. MOVL CX, CR3
  160. DELAY /* JMP .+2 */
  161. MOVL CR0, DX
  162. ORL $0x80010000, DX /* PG|WP */
  163. ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
  164. MOVL $_startpg(SB), AX /* this is a virtual address */
  165. MOVL DX, CR0 /* turn on paging */
  166. JMP* AX /* jump to the virtual nirvana */
  167. /*
  168. * Basic machine environment set, can clear BSS and create a stack.
  169. * The stack starts at the top of the page containing the Mach structure.
  170. * The x86 architecture forces the use of the same virtual address for
  171. * each processor's Mach structure, so the global Mach pointer 'm' can
  172. * be initialised here.
  173. */
  174. TEXT _startpg(SB), $0
  175. MOVL $0, (PDO(0))(CX) /* undo double-map of KZERO at 0 */
  176. MOVL CX, CR3 /* load and flush the mmu */
  177. _clearbss:
  178. MOVL $edata(SB), DI
  179. XORL AX, AX
  180. MOVL $end(SB), CX
  181. SUBL DI, CX /* end-edata bytes */
  182. SHRL $2, CX /* end-edata doublewords */
  183. CLD
  184. REP; STOSL /* clear BSS */
  185. MOVL $MACHADDR, SP
  186. MOVL SP, m(SB) /* initialise global Mach pointer */
  187. MOVL $0, 0(SP) /* initialise m->machno */
  188. ADDL $(MACHSIZE-4), SP /* initialise stack */
  189. /*
  190. * Need to do one final thing to ensure a clean machine environment,
  191. * clear the EFLAGS register, which can only be done once there is a stack.
  192. */
  193. MOVL $0, AX
  194. PUSHL AX
  195. POPFL
  196. CALL main(SB)
  197. /*
  198. * Park a processor. Should never fall through a return from main to here,
  199. * should only be called by application processors when shutting down.
  200. */
  201. TEXT idle(SB), $0
  202. _idle:
  203. STI
  204. HLT
  205. JMP _idle
  206. /*
  207. * Save registers.
  208. */
  209. TEXT saveregs(SB), $0
  210. /* appease 8l */
  211. SUBL $32, SP
  212. POPL AX
  213. POPL AX
  214. POPL AX
  215. POPL AX
  216. POPL AX
  217. POPL AX
  218. POPL AX
  219. POPL AX
  220. PUSHL AX
  221. PUSHL BX
  222. PUSHL CX
  223. PUSHL DX
  224. PUSHL BP
  225. PUSHL DI
  226. PUSHL SI
  227. PUSHFL
  228. XCHGL 32(SP), AX /* swap return PC and saved flags */
  229. XCHGL 0(SP), AX
  230. XCHGL 32(SP), AX
  231. RET
  232. TEXT restoreregs(SB), $0
  233. /* appease 8l */
  234. PUSHL AX
  235. PUSHL AX
  236. PUSHL AX
  237. PUSHL AX
  238. PUSHL AX
  239. PUSHL AX
  240. PUSHL AX
  241. PUSHL AX
  242. ADDL $32, SP
  243. XCHGL 32(SP), AX /* swap return PC and saved flags */
  244. XCHGL 0(SP), AX
  245. XCHGL 32(SP), AX
  246. POPFL
  247. POPL SI
  248. POPL DI
  249. POPL BP
  250. POPL DX
  251. POPL CX
  252. POPL BX
  253. POPL AX
  254. RET
  255. /*
  256. * Assumed to be in protected mode at time of call.
  257. * Switch to real mode, execute an interrupt, and
  258. * then switch back to protected mode.
  259. *
  260. * Assumes:
  261. *
  262. * - no device interrupts are going to come in
  263. * - 0-16MB is identity mapped in page tables
  264. * - realmode() has copied us down from 0x100000 to 0x8000
  265. * - can use code segment 0x0800 in real mode
  266. * to get at l.s code
  267. * - l.s code is less than 1 page
  268. */
  269. #define RELOC (RMCODE-KTZERO)
  270. TEXT realmodeidtptr(SB), $0
  271. WORD $(4*256-1)
  272. LONG $0
  273. TEXT realmode0(SB), $0
  274. CALL saveregs(SB)
  275. /* switch to low code address */
  276. LEAL physcode-KZERO(SB), AX
  277. JMP *AX
  278. TEXT physcode(SB), $0
  279. /* switch to low stack */
  280. MOVL SP, AX
  281. MOVL $0x7C00, SP
  282. PUSHL AX
  283. /* change gdt to physical pointer */
  284. MOVL m0rgdtptr-KZERO(SB), GDTR
  285. /* load IDT with real-mode version*/
  286. MOVL realmodeidtptr-KZERO(SB), IDTR
  287. /* edit INT $0x00 instruction below */
  288. MOVL $(RMUADDR-KZERO+48), AX /* &rmu.trap */
  289. MOVL (AX), AX
  290. MOVB AX, realmodeintrinst+(-KZERO+1+RELOC)(SB)
  291. /* disable paging */
  292. MOVL CR0, AX
  293. ANDL $0x7FFFFFFF, AX
  294. MOVL AX, CR0
  295. /* JMP .+2 to clear prefetch queue*/
  296. BYTE $0xEB; BYTE $0x00
  297. /* jump to 16-bit code segment */
  298. /* JMPFAR SELECTOR(KESEG16, SELGDT, 0):$again16bit(SB) /**/
  299. BYTE $0xEA
  300. LONG $again16bit-KZERO(SB)
  301. WORD $SELECTOR(KESEG16, SELGDT, 0)
  302. TEXT again16bit(SB), $0
  303. /*
  304. * Now in 16-bit compatibility mode.
  305. * These are 32-bit instructions being interpreted
  306. * as 16-bit instructions. I'm being lazy and
  307. * not using the macros because I know when
  308. * the 16- and 32-bit instructions look the same
  309. * or close enough.
  310. */
  311. /* disable protected mode and jump to real mode cs */
  312. OPSIZE; MOVL CR0, AX
  313. OPSIZE; XORL BX, BX
  314. OPSIZE; INCL BX
  315. OPSIZE; XORL BX, AX
  316. OPSIZE; MOVL AX, CR0
  317. /* JMPFAR 0x0800:now16real */
  318. BYTE $0xEA
  319. WORD $now16real-KZERO(SB)
  320. WORD $0x0800
  321. TEXT now16real(SB), $0
  322. /* copy the registers for the bios call */
  323. LWI(0x0000, rAX)
  324. MOVW AX,SS
  325. LWI(RMUADDR, rBP)
  326. /* offsets are in Ureg */
  327. LXW(44, xBP, rAX)
  328. MOVW AX, DS
  329. LXW(40, xBP, rAX)
  330. MOVW AX, ES
  331. OPSIZE; LXW(0, xBP, rDI)
  332. OPSIZE; LXW(4, xBP, rSI)
  333. OPSIZE; LXW(16, xBP, rBX)
  334. OPSIZE; LXW(20, xBP, rDX)
  335. OPSIZE; LXW(24, xBP, rCX)
  336. OPSIZE; LXW(28, xBP, rAX)
  337. CLC
  338. TEXT realmodeintrinst(SB), $0
  339. INT $0x00
  340. /* save the registers after the call */
  341. LWI(0x7bfc, rSP)
  342. OPSIZE; PUSHFL
  343. OPSIZE; PUSHL AX
  344. LWI(0, rAX)
  345. MOVW AX,SS
  346. LWI(RMUADDR, rBP)
  347. OPSIZE; SXW(rDI, 0, xBP)
  348. OPSIZE; SXW(rSI, 4, xBP)
  349. OPSIZE; SXW(rBX, 16, xBP)
  350. OPSIZE; SXW(rDX, 20, xBP)
  351. OPSIZE; SXW(rCX, 24, xBP)
  352. OPSIZE; POPL AX
  353. OPSIZE; SXW(rAX, 28, xBP)
  354. MOVW DS, AX
  355. OPSIZE; SXW(rAX, 44, xBP)
  356. MOVW ES, AX
  357. OPSIZE; SXW(rAX, 40, xBP)
  358. OPSIZE; POPL AX
  359. OPSIZE; SXW(rAX, 64, xBP) /* flags */
  360. /* re-enter protected mode and jump to 32-bit code */
  361. OPSIZE; MOVL $1, AX
  362. OPSIZE; MOVL AX, CR0
  363. /* JMPFAR SELECTOR(KESEG, SELGDT, 0):$again32bit(SB) /**/
  364. OPSIZE
  365. BYTE $0xEA
  366. LONG $again32bit-KZERO(SB)
  367. WORD $SELECTOR(KESEG, SELGDT, 0)
  368. TEXT again32bit(SB), $0
  369. MOVW $SELECTOR(KDSEG, SELGDT, 0),AX
  370. MOVW AX,DS
  371. MOVW AX,SS
  372. MOVW AX,ES
  373. MOVW AX,FS
  374. MOVW AX,GS
  375. /* enable paging and jump to kzero-address code */
  376. MOVL CR0, AX
  377. ORL $0x80010000, AX /* PG|WP */
  378. MOVL AX, CR0
  379. LEAL again32kzero(SB), AX
  380. JMP* AX
  381. TEXT again32kzero(SB), $0
  382. /* breathe a sigh of relief - back in 32-bit protected mode */
  383. /* switch to old stack */
  384. PUSHL AX /* match popl below for 8l */
  385. MOVL $0x7BFC, SP
  386. POPL SP
  387. /* restore idt */
  388. MOVL m0idtptr(SB),IDTR
  389. /* restore gdt */
  390. MOVL m0gdtptr(SB), GDTR
  391. CALL restoreregs(SB)
  392. RET
  393. /*
  394. * BIOS32.
  395. */
  396. TEXT bios32call(SB), $0
  397. MOVL ci+0(FP), BP
  398. MOVL 0(BP), AX
  399. MOVL 4(BP), BX
  400. MOVL 8(BP), CX
  401. MOVL 12(BP), DX
  402. MOVL 16(BP), SI
  403. MOVL 20(BP), DI
  404. PUSHL BP
  405. MOVL 12(SP), BP /* ptr */
  406. BYTE $0xFF; BYTE $0x5D; BYTE $0x00 /* CALL FAR 0(BP) */
  407. POPL BP
  408. MOVL DI, 20(BP)
  409. MOVL SI, 16(BP)
  410. MOVL DX, 12(BP)
  411. MOVL CX, 8(BP)
  412. MOVL BX, 4(BP)
  413. MOVL AX, 0(BP)
  414. XORL AX, AX
  415. JCC _bios32xxret
  416. INCL AX
  417. _bios32xxret:
  418. RET
  419. /*
  420. * Port I/O.
  421. * in[bsl] input a byte|short|long
  422. * ins[bsl] input a string of bytes|shorts|longs
  423. * out[bsl] output a byte|short|long
  424. * outs[bsl] output a string of bytes|shorts|longs
  425. */
  426. TEXT inb(SB), $0
  427. MOVL port+0(FP), DX
  428. XORL AX, AX
  429. INB
  430. RET
  431. TEXT insb(SB), $0
  432. MOVL port+0(FP), DX
  433. MOVL address+4(FP), DI
  434. MOVL count+8(FP), CX
  435. CLD
  436. REP; INSB
  437. RET
  438. TEXT ins(SB), $0
  439. MOVL port+0(FP), DX
  440. XORL AX, AX
  441. OP16; INL
  442. RET
  443. TEXT inss(SB), $0
  444. MOVL port+0(FP), DX
  445. MOVL address+4(FP), DI
  446. MOVL count+8(FP), CX
  447. CLD
  448. REP; OP16; INSL
  449. RET
  450. TEXT inl(SB), $0
  451. MOVL port+0(FP), DX
  452. INL
  453. RET
  454. TEXT insl(SB), $0
  455. MOVL port+0(FP), DX
  456. MOVL address+4(FP), DI
  457. MOVL count+8(FP), CX
  458. CLD
  459. REP; INSL
  460. RET
  461. TEXT outb(SB), $0
  462. MOVL port+0(FP), DX
  463. MOVL byte+4(FP), AX
  464. OUTB
  465. RET
  466. TEXT outsb(SB), $0
  467. MOVL port+0(FP), DX
  468. MOVL address+4(FP), SI
  469. MOVL count+8(FP), CX
  470. CLD
  471. REP; OUTSB
  472. RET
  473. TEXT outs(SB), $0
  474. MOVL port+0(FP), DX
  475. MOVL short+4(FP), AX
  476. OP16; OUTL
  477. RET
  478. TEXT outss(SB), $0
  479. MOVL port+0(FP), DX
  480. MOVL address+4(FP), SI
  481. MOVL count+8(FP), CX
  482. CLD
  483. REP; OP16; OUTSL
  484. RET
  485. TEXT outl(SB), $0
  486. MOVL port+0(FP), DX
  487. MOVL long+4(FP), AX
  488. OUTL
  489. RET
  490. TEXT outsl(SB), $0
  491. MOVL port+0(FP), DX
  492. MOVL address+4(FP), SI
  493. MOVL count+8(FP), CX
  494. CLD
  495. REP; OUTSL
  496. RET
  497. /*
  498. * Read/write various system registers.
  499. * CR4 and the 'model specific registers' should only be read/written
  500. * after it has been determined the processor supports them
  501. */
  502. TEXT lgdt(SB), $0 /* GDTR - global descriptor table */
  503. MOVL gdtptr+0(FP), AX
  504. MOVL (AX), GDTR
  505. RET
  506. TEXT lidt(SB), $0 /* IDTR - interrupt descriptor table */
  507. MOVL idtptr+0(FP), AX
  508. MOVL (AX), IDTR
  509. RET
  510. TEXT ltr(SB), $0 /* TR - task register */
  511. MOVL tptr+0(FP), AX
  512. MOVW AX, TASK
  513. RET
  514. TEXT getcr0(SB), $0 /* CR0 - processor control */
  515. MOVL CR0, AX
  516. RET
  517. TEXT getcr2(SB), $0 /* CR2 - page fault linear address */
  518. MOVL CR2, AX
  519. RET
  520. TEXT getcr3(SB), $0 /* CR3 - page directory base */
  521. MOVL CR3, AX
  522. RET
  523. TEXT putcr3(SB), $0
  524. MOVL cr3+0(FP), AX
  525. MOVL AX, CR3
  526. RET
  527. TEXT getcr4(SB), $0 /* CR4 - extensions */
  528. MOVL CR4, AX
  529. RET
  530. TEXT putcr4(SB), $0
  531. MOVL cr4+0(FP), AX
  532. MOVL AX, CR4
  533. RET
  534. TEXT invlpg(SB), $0
  535. /* 486+ only */
  536. MOVL va+0(FP), CX
  537. INVLPG
  538. RET
  539. TEXT _cycles(SB), $0 /* time stamp counter */
  540. RDTSC
  541. MOVL vlong+0(FP), CX /* &vlong */
  542. MOVL AX, 0(CX) /* lo */
  543. MOVL DX, 4(CX) /* hi */
  544. RET
  545. /*
  546. * stub for:
  547. * time stamp counter; low-order 32 bits of 64-bit cycle counter
  548. * Runs at fasthz/4 cycles per second (m->clkin>>3)
  549. */
  550. TEXT lcycles(SB),1,$0
  551. RDTSC
  552. RET
  553. TEXT rdmsr(SB), $0 /* model-specific register */
  554. MOVL index+0(FP), CX
  555. RDMSR
  556. MOVL vlong+4(FP), CX /* &vlong */
  557. MOVL AX, 0(CX) /* lo */
  558. MOVL DX, 4(CX) /* hi */
  559. RET
  560. TEXT wrmsr(SB), $0
  561. MOVL index+0(FP), CX
  562. MOVL lo+4(FP), AX
  563. MOVL hi+8(FP), DX
  564. WRMSR
  565. RET
  566. /*
  567. * Try to determine the CPU type which requires fiddling with EFLAGS.
  568. * If the Id bit can be toggled then the CPUID instruction can be used
  569. * to determine CPU identity and features. First have to check if it's
  570. * a 386 (Ac bit can't be set). If it's not a 386 and the Id bit can't be
  571. * toggled then it's an older 486 of some kind.
  572. *
  573. * cpuid(id[], &ax, &dx);
  574. */
  575. TEXT cpuid(SB), $0
  576. MOVL $0x240000, AX
  577. PUSHL AX
  578. POPFL /* set Id|Ac */
  579. PUSHFL
  580. POPL BX /* retrieve value */
  581. MOVL $0, AX
  582. PUSHL AX
  583. POPFL /* clear Id|Ac, EFLAGS initialised */
  584. PUSHFL
  585. POPL AX /* retrieve value */
  586. XORL BX, AX
  587. TESTL $0x040000, AX /* Ac */
  588. JZ _cpu386 /* can't set this bit on 386 */
  589. TESTL $0x200000, AX /* Id */
  590. JZ _cpu486 /* can't toggle this bit on some 486 */
  591. MOVL $0, AX
  592. CPUID
  593. MOVL id+0(FP), BP
  594. MOVL BX, 0(BP) /* "Genu" "Auth" "Cyri" */
  595. MOVL DX, 4(BP) /* "ineI" "enti" "xIns" */
  596. MOVL CX, 8(BP) /* "ntel" "cAMD" "tead" */
  597. MOVL $1, AX
  598. CPUID
  599. JMP _cpuid
  600. _cpu486:
  601. MOVL $0x400, AX
  602. MOVL $0, DX
  603. JMP _cpuid
  604. _cpu386:
  605. MOVL $0x300, AX
  606. MOVL $0, DX
  607. _cpuid:
  608. MOVL ax+4(FP), BP
  609. MOVL AX, 0(BP)
  610. MOVL dx+8(FP), BP
  611. MOVL DX, 0(BP)
  612. RET
  613. /*
  614. * Basic timing loop to determine CPU frequency.
  615. */
  616. TEXT aamloop(SB), $0
  617. MOVL count+0(FP), CX
  618. _aamloop:
  619. AAM
  620. LOOP _aamloop
  621. RET
  622. /*
  623. * Floating point.
  624. * Note: the encodings for the FCLEX, FINIT, FSAVE, FSTCW, FSENV and FSTSW
  625. * instructions do NOT have the WAIT prefix byte (i.e. they act like their
  626. * FNxxx variations) so WAIT instructions must be explicitly placed in the
  627. * code as necessary.
  628. */
  629. #define FPOFF(l) ;\
  630. MOVL CR0, AX ;\
  631. ANDL $0xC, AX /* EM, TS */ ;\
  632. CMPL AX, $0x8 ;\
  633. JEQ l ;\
  634. WAIT ;\
  635. l: ;\
  636. MOVL CR0, AX ;\
  637. ANDL $~0x4, AX /* EM=0 */ ;\
  638. ORL $0x28, AX /* NE=1, TS=1 */ ;\
  639. MOVL AX, CR0
  640. #define FPON ;\
  641. MOVL CR0, AX ;\
  642. ANDL $~0xC, AX /* EM=0, TS=0 */ ;\
  643. MOVL AX, CR0
  644. TEXT fpoff(SB), $0 /* disable */
  645. FPOFF(l1)
  646. RET
  647. TEXT fpinit(SB), $0 /* enable and init */
  648. FPON
  649. FINIT
  650. WAIT
  651. /* setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL) */
  652. /* note that low 6 bits are masks, not enables, on this chip */
  653. PUSHW $0x0232
  654. FLDCW 0(SP)
  655. POPW AX
  656. WAIT
  657. RET
  658. TEXT fpsave(SB), $0 /* save state and disable */
  659. MOVL p+0(FP), AX
  660. FSAVE 0(AX) /* no WAIT */
  661. FPOFF(l2)
  662. RET
  663. TEXT fprestore(SB), $0 /* enable and restore state */
  664. FPON
  665. MOVL p+0(FP), AX
  666. FRSTOR 0(AX)
  667. WAIT
  668. RET
  669. TEXT fpstatus(SB), $0 /* get floating point status */
  670. FSTSW AX
  671. RET
  672. TEXT fpenv(SB), $0 /* save state without waiting */
  673. MOVL p+0(FP), AX
  674. FSTENV 0(AX)
  675. RET
  676. TEXT fpclear(SB), $0 /* clear pending exceptions */
  677. FPON
  678. FCLEX /* no WAIT */
  679. FPOFF(l3)
  680. RET
  681. /*
  682. */
  683. TEXT splhi(SB), $0
  684. shi:
  685. PUSHFL
  686. POPL AX
  687. TESTL $0x200, AX
  688. JZ alreadyhi
  689. MOVL $(MACHADDR+0x04), CX /* save PC in m->splpc */
  690. MOVL (SP), BX
  691. MOVL BX, (CX)
  692. alreadyhi:
  693. CLI
  694. RET
  695. TEXT spllo(SB), $0
  696. slo:
  697. PUSHFL
  698. POPL AX
  699. TESTL $0x200, AX
  700. JNZ alreadylo
  701. MOVL $(MACHADDR+0x04), CX /* clear m->splpc */
  702. MOVL $0, (CX)
  703. alreadylo:
  704. STI
  705. RET
  706. TEXT splx(SB), $0
  707. MOVL s+0(FP), AX
  708. TESTL $0x200, AX
  709. JNZ slo
  710. JMP shi
  711. TEXT spldone(SB), $0
  712. RET
  713. TEXT islo(SB), $0
  714. PUSHFL
  715. POPL AX
  716. ANDL $0x200, AX /* interrupt enable flag */
  717. RET
  718. /*
  719. * Test-And-Set
  720. */
  721. TEXT tas(SB), $0
  722. MOVL $0xDEADDEAD, AX
  723. MOVL lock+0(FP), BX
  724. XCHGL AX, (BX) /* lock->key */
  725. RET
  726. TEXT _xinc(SB), $0 /* void _xinc(long*); */
  727. MOVL l+0(FP), AX
  728. LOCK; INCL 0(AX)
  729. RET
  730. TEXT _xdec(SB), $0 /* long _xdec(long*); */
  731. MOVL l+0(FP), BX
  732. XORL AX, AX
  733. LOCK; DECL 0(BX)
  734. JLT _xdeclt
  735. JGT _xdecgt
  736. RET
  737. _xdecgt:
  738. INCL AX
  739. RET
  740. _xdeclt:
  741. DECL AX
  742. RET
  743. TEXT mb386(SB), $0
  744. POPL AX /* return PC */
  745. PUSHFL
  746. PUSHL CS
  747. PUSHL AX
  748. IRETL
  749. TEXT mb586(SB), $0
  750. XORL AX, AX
  751. CPUID
  752. RET
  753. TEXT sfence(SB), $0
  754. BYTE $0x0f
  755. BYTE $0xae
  756. BYTE $0xf8
  757. RET
  758. TEXT lfence(SB), $0
  759. BYTE $0x0f
  760. BYTE $0xae
  761. BYTE $0xe8
  762. RET
  763. TEXT mfence(SB), $0
  764. BYTE $0x0f
  765. BYTE $0xae
  766. BYTE $0xf0
  767. RET
  768. TEXT xchgw(SB), $0
  769. MOVL v+4(FP), AX
  770. MOVL p+0(FP), BX
  771. XCHGW AX, (BX)
  772. RET
  773. TEXT cmpswap486(SB), $0
  774. MOVL addr+0(FP), BX
  775. MOVL old+4(FP), AX
  776. MOVL new+8(FP), CX
  777. LOCK
  778. BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
  779. JNZ didnt
  780. MOVL $1, AX
  781. RET
  782. didnt:
  783. XORL AX,AX
  784. RET
  785. TEXT mul64fract(SB), $0
  786. /*
  787. * Multiply two 64-bit number s and keep the middle 64 bits from the 128-bit result
  788. * See ../port/tod.c for motivation.
  789. */
  790. MOVL r+0(FP), CX
  791. XORL BX, BX /* BX = 0 */
  792. MOVL a+8(FP), AX
  793. MULL b+16(FP) /* a1*b1 */
  794. MOVL AX, 4(CX) /* r2 = lo(a1*b1) */
  795. MOVL a+8(FP), AX
  796. MULL b+12(FP) /* a1*b0 */
  797. MOVL AX, 0(CX) /* r1 = lo(a1*b0) */
  798. ADDL DX, 4(CX) /* r2 += hi(a1*b0) */
  799. MOVL a+4(FP), AX
  800. MULL b+16(FP) /* a0*b1 */
  801. ADDL AX, 0(CX) /* r1 += lo(a0*b1) */
  802. ADCL DX, 4(CX) /* r2 += hi(a0*b1) + carry */
  803. MOVL a+4(FP), AX
  804. MULL b+12(FP) /* a0*b0 */
  805. ADDL DX, 0(CX) /* r1 += hi(a0*b0) */
  806. ADCL BX, 4(CX) /* r2 += carry */
  807. RET
  808. /*
  809. * label consists of a stack pointer and a PC
  810. */
  811. TEXT gotolabel(SB), $0
  812. MOVL label+0(FP), AX
  813. MOVL 0(AX), SP /* restore sp */
  814. MOVL 4(AX), AX /* put return pc on the stack */
  815. MOVL AX, 0(SP)
  816. MOVL $1, AX /* return 1 */
  817. RET
  818. TEXT setlabel(SB), $0
  819. MOVL label+0(FP), AX
  820. MOVL SP, 0(AX) /* store sp */
  821. MOVL 0(SP), BX /* store return pc */
  822. MOVL BX, 4(AX)
  823. MOVL $0, AX /* return 0 */
  824. RET
  825. /*
  826. * Attempt at power saving. -rsc
  827. */
  828. TEXT halt(SB), $0
  829. CLI
  830. CMPL nrdy(SB), $0
  831. JEQ _nothingready
  832. STI
  833. RET
  834. _nothingready:
  835. STI
  836. HLT
  837. RET
  838. /*
  839. * Interrupt/exception handling.
  840. * Each entry in the vector table calls either _strayintr or _strayintrx depending
  841. * on whether an error code has been automatically pushed onto the stack
  842. * (_strayintrx) or not, in which case a dummy entry must be pushed before retrieving
  843. * the trap type from the vector table entry and placing it on the stack as part
  844. * of the Ureg structure.
  845. * The size of each entry in the vector table (6 bytes) is known in trapinit().
  846. */
  847. TEXT _strayintr(SB), $0
  848. PUSHL AX /* save AX */
  849. MOVL 4(SP), AX /* return PC from vectortable(SB) */
  850. JMP intrcommon
  851. TEXT _strayintrx(SB), $0
  852. XCHGL AX, (SP) /* swap AX with vectortable CALL PC */
  853. intrcommon:
  854. PUSHL DS /* save DS */
  855. PUSHL $(KDSEL)
  856. POPL DS /* fix up DS */
  857. MOVBLZX (AX), AX /* trap type -> AX */
  858. XCHGL AX, 4(SP) /* exchange trap type with saved AX */
  859. PUSHL ES /* save ES */
  860. PUSHL $(KDSEL)
  861. POPL ES /* fix up ES */
  862. PUSHL FS /* save the rest of the Ureg struct */
  863. PUSHL GS
  864. PUSHAL
  865. PUSHL SP /* Ureg* argument to trap */
  866. CALL trap(SB)
  867. TEXT forkret(SB), $0
  868. POPL AX
  869. POPAL
  870. POPL GS
  871. POPL FS
  872. POPL ES
  873. POPL DS
  874. ADDL $8, SP /* pop error code and trap type */
  875. IRETL
  876. TEXT vectortable(SB), $0
  877. CALL _strayintr(SB); BYTE $0x00 /* divide error */
  878. CALL _strayintr(SB); BYTE $0x01 /* debug exception */
  879. CALL _strayintr(SB); BYTE $0x02 /* NMI interrupt */
  880. CALL _strayintr(SB); BYTE $0x03 /* breakpoint */
  881. CALL _strayintr(SB); BYTE $0x04 /* overflow */
  882. CALL _strayintr(SB); BYTE $0x05 /* bound */
  883. CALL _strayintr(SB); BYTE $0x06 /* invalid opcode */
  884. CALL _strayintr(SB); BYTE $0x07 /* no coprocessor available */
  885. CALL _strayintrx(SB); BYTE $0x08 /* double fault */
  886. CALL _strayintr(SB); BYTE $0x09 /* coprocessor segment overflow */
  887. CALL _strayintrx(SB); BYTE $0x0A /* invalid TSS */
  888. CALL _strayintrx(SB); BYTE $0x0B /* segment not available */
  889. CALL _strayintrx(SB); BYTE $0x0C /* stack exception */
  890. CALL _strayintrx(SB); BYTE $0x0D /* general protection error */
  891. CALL _strayintrx(SB); BYTE $0x0E /* page fault */
  892. CALL _strayintr(SB); BYTE $0x0F /* */
  893. CALL _strayintr(SB); BYTE $0x10 /* coprocessor error */
  894. CALL _strayintrx(SB); BYTE $0x11 /* alignment check */
  895. CALL _strayintr(SB); BYTE $0x12 /* machine check */
  896. CALL _strayintr(SB); BYTE $0x13
  897. CALL _strayintr(SB); BYTE $0x14
  898. CALL _strayintr(SB); BYTE $0x15
  899. CALL _strayintr(SB); BYTE $0x16
  900. CALL _strayintr(SB); BYTE $0x17
  901. CALL _strayintr(SB); BYTE $0x18
  902. CALL _strayintr(SB); BYTE $0x19
  903. CALL _strayintr(SB); BYTE $0x1A
  904. CALL _strayintr(SB); BYTE $0x1B
  905. CALL _strayintr(SB); BYTE $0x1C
  906. CALL _strayintr(SB); BYTE $0x1D
  907. CALL _strayintr(SB); BYTE $0x1E
  908. CALL _strayintr(SB); BYTE $0x1F
  909. CALL _strayintr(SB); BYTE $0x20 /* VectorLAPIC */
  910. CALL _strayintr(SB); BYTE $0x21
  911. CALL _strayintr(SB); BYTE $0x22
  912. CALL _strayintr(SB); BYTE $0x23
  913. CALL _strayintr(SB); BYTE $0x24
  914. CALL _strayintr(SB); BYTE $0x25
  915. CALL _strayintr(SB); BYTE $0x26
  916. CALL _strayintr(SB); BYTE $0x27
  917. CALL _strayintr(SB); BYTE $0x28
  918. CALL _strayintr(SB); BYTE $0x29
  919. CALL _strayintr(SB); BYTE $0x2A
  920. CALL _strayintr(SB); BYTE $0x2B
  921. CALL _strayintr(SB); BYTE $0x2C
  922. CALL _strayintr(SB); BYTE $0x2D
  923. CALL _strayintr(SB); BYTE $0x2E
  924. CALL _strayintr(SB); BYTE $0x2F
  925. CALL _strayintr(SB); BYTE $0x30
  926. CALL _strayintr(SB); BYTE $0x31
  927. CALL _strayintr(SB); BYTE $0x32
  928. CALL _strayintr(SB); BYTE $0x33
  929. CALL _strayintr(SB); BYTE $0x34
  930. CALL _strayintr(SB); BYTE $0x35
  931. CALL _strayintr(SB); BYTE $0x36
  932. CALL _strayintr(SB); BYTE $0x37
  933. CALL _strayintr(SB); BYTE $0x38
  934. CALL _strayintr(SB); BYTE $0x39
  935. CALL _strayintr(SB); BYTE $0x3A
  936. CALL _strayintr(SB); BYTE $0x3B
  937. CALL _strayintr(SB); BYTE $0x3C
  938. CALL _strayintr(SB); BYTE $0x3D
  939. CALL _strayintr(SB); BYTE $0x3E
  940. CALL _strayintr(SB); BYTE $0x3F
  941. CALL _syscallintr(SB); BYTE $0x40 /* VectorSYSCALL */
  942. CALL _strayintr(SB); BYTE $0x41
  943. CALL _strayintr(SB); BYTE $0x42
  944. CALL _strayintr(SB); BYTE $0x43
  945. CALL _strayintr(SB); BYTE $0x44
  946. CALL _strayintr(SB); BYTE $0x45
  947. CALL _strayintr(SB); BYTE $0x46
  948. CALL _strayintr(SB); BYTE $0x47
  949. CALL _strayintr(SB); BYTE $0x48
  950. CALL _strayintr(SB); BYTE $0x49
  951. CALL _strayintr(SB); BYTE $0x4A
  952. CALL _strayintr(SB); BYTE $0x4B
  953. CALL _strayintr(SB); BYTE $0x4C
  954. CALL _strayintr(SB); BYTE $0x4D
  955. CALL _strayintr(SB); BYTE $0x4E
  956. CALL _strayintr(SB); BYTE $0x4F
  957. CALL _strayintr(SB); BYTE $0x50
  958. CALL _strayintr(SB); BYTE $0x51
  959. CALL _strayintr(SB); BYTE $0x52
  960. CALL _strayintr(SB); BYTE $0x53
  961. CALL _strayintr(SB); BYTE $0x54
  962. CALL _strayintr(SB); BYTE $0x55
  963. CALL _strayintr(SB); BYTE $0x56
  964. CALL _strayintr(SB); BYTE $0x57
  965. CALL _strayintr(SB); BYTE $0x58
  966. CALL _strayintr(SB); BYTE $0x59
  967. CALL _strayintr(SB); BYTE $0x5A
  968. CALL _strayintr(SB); BYTE $0x5B
  969. CALL _strayintr(SB); BYTE $0x5C
  970. CALL _strayintr(SB); BYTE $0x5D
  971. CALL _strayintr(SB); BYTE $0x5E
  972. CALL _strayintr(SB); BYTE $0x5F
  973. CALL _strayintr(SB); BYTE $0x60
  974. CALL _strayintr(SB); BYTE $0x61
  975. CALL _strayintr(SB); BYTE $0x62
  976. CALL _strayintr(SB); BYTE $0x63
  977. CALL _strayintr(SB); BYTE $0x64
  978. CALL _strayintr(SB); BYTE $0x65
  979. CALL _strayintr(SB); BYTE $0x66
  980. CALL _strayintr(SB); BYTE $0x67
  981. CALL _strayintr(SB); BYTE $0x68
  982. CALL _strayintr(SB); BYTE $0x69
  983. CALL _strayintr(SB); BYTE $0x6A
  984. CALL _strayintr(SB); BYTE $0x6B
  985. CALL _strayintr(SB); BYTE $0x6C
  986. CALL _strayintr(SB); BYTE $0x6D
  987. CALL _strayintr(SB); BYTE $0x6E
  988. CALL _strayintr(SB); BYTE $0x6F
  989. CALL _strayintr(SB); BYTE $0x70
  990. CALL _strayintr(SB); BYTE $0x71
  991. CALL _strayintr(SB); BYTE $0x72
  992. CALL _strayintr(SB); BYTE $0x73
  993. CALL _strayintr(SB); BYTE $0x74
  994. CALL _strayintr(SB); BYTE $0x75
  995. CALL _strayintr(SB); BYTE $0x76
  996. CALL _strayintr(SB); BYTE $0x77
  997. CALL _strayintr(SB); BYTE $0x78
  998. CALL _strayintr(SB); BYTE $0x79
  999. CALL _strayintr(SB); BYTE $0x7A
  1000. CALL _strayintr(SB); BYTE $0x7B
  1001. CALL _strayintr(SB); BYTE $0x7C
  1002. CALL _strayintr(SB); BYTE $0x7D
  1003. CALL _strayintr(SB); BYTE $0x7E
  1004. CALL _strayintr(SB); BYTE $0x7F
  1005. CALL _strayintr(SB); BYTE $0x80 /* Vector[A]PIC */
  1006. CALL _strayintr(SB); BYTE $0x81
  1007. CALL _strayintr(SB); BYTE $0x82
  1008. CALL _strayintr(SB); BYTE $0x83
  1009. CALL _strayintr(SB); BYTE $0x84
  1010. CALL _strayintr(SB); BYTE $0x85
  1011. CALL _strayintr(SB); BYTE $0x86
  1012. CALL _strayintr(SB); BYTE $0x87
  1013. CALL _strayintr(SB); BYTE $0x88
  1014. CALL _strayintr(SB); BYTE $0x89
  1015. CALL _strayintr(SB); BYTE $0x8A
  1016. CALL _strayintr(SB); BYTE $0x8B
  1017. CALL _strayintr(SB); BYTE $0x8C
  1018. CALL _strayintr(SB); BYTE $0x8D
  1019. CALL _strayintr(SB); BYTE $0x8E
  1020. CALL _strayintr(SB); BYTE $0x8F
  1021. CALL _strayintr(SB); BYTE $0x90
  1022. CALL _strayintr(SB); BYTE $0x91
  1023. CALL _strayintr(SB); BYTE $0x92
  1024. CALL _strayintr(SB); BYTE $0x93
  1025. CALL _strayintr(SB); BYTE $0x94
  1026. CALL _strayintr(SB); BYTE $0x95
  1027. CALL _strayintr(SB); BYTE $0x96
  1028. CALL _strayintr(SB); BYTE $0x97
  1029. CALL _strayintr(SB); BYTE $0x98
  1030. CALL _strayintr(SB); BYTE $0x99
  1031. CALL _strayintr(SB); BYTE $0x9A
  1032. CALL _strayintr(SB); BYTE $0x9B
  1033. CALL _strayintr(SB); BYTE $0x9C
  1034. CALL _strayintr(SB); BYTE $0x9D
  1035. CALL _strayintr(SB); BYTE $0x9E
  1036. CALL _strayintr(SB); BYTE $0x9F
  1037. CALL _strayintr(SB); BYTE $0xA0
  1038. CALL _strayintr(SB); BYTE $0xA1
  1039. CALL _strayintr(SB); BYTE $0xA2
  1040. CALL _strayintr(SB); BYTE $0xA3
  1041. CALL _strayintr(SB); BYTE $0xA4
  1042. CALL _strayintr(SB); BYTE $0xA5
  1043. CALL _strayintr(SB); BYTE $0xA6
  1044. CALL _strayintr(SB); BYTE $0xA7
  1045. CALL _strayintr(SB); BYTE $0xA8
  1046. CALL _strayintr(SB); BYTE $0xA9
  1047. CALL _strayintr(SB); BYTE $0xAA
  1048. CALL _strayintr(SB); BYTE $0xAB
  1049. CALL _strayintr(SB); BYTE $0xAC
  1050. CALL _strayintr(SB); BYTE $0xAD
  1051. CALL _strayintr(SB); BYTE $0xAE
  1052. CALL _strayintr(SB); BYTE $0xAF
  1053. CALL _strayintr(SB); BYTE $0xB0
  1054. CALL _strayintr(SB); BYTE $0xB1
  1055. CALL _strayintr(SB); BYTE $0xB2
  1056. CALL _strayintr(SB); BYTE $0xB3
  1057. CALL _strayintr(SB); BYTE $0xB4
  1058. CALL _strayintr(SB); BYTE $0xB5
  1059. CALL _strayintr(SB); BYTE $0xB6
  1060. CALL _strayintr(SB); BYTE $0xB7
  1061. CALL _strayintr(SB); BYTE $0xB8
  1062. CALL _strayintr(SB); BYTE $0xB9
  1063. CALL _strayintr(SB); BYTE $0xBA
  1064. CALL _strayintr(SB); BYTE $0xBB
  1065. CALL _strayintr(SB); BYTE $0xBC
  1066. CALL _strayintr(SB); BYTE $0xBD
  1067. CALL _strayintr(SB); BYTE $0xBE
  1068. CALL _strayintr(SB); BYTE $0xBF
  1069. CALL _strayintr(SB); BYTE $0xC0
  1070. CALL _strayintr(SB); BYTE $0xC1
  1071. CALL _strayintr(SB); BYTE $0xC2
  1072. CALL _strayintr(SB); BYTE $0xC3
  1073. CALL _strayintr(SB); BYTE $0xC4
  1074. CALL _strayintr(SB); BYTE $0xC5
  1075. CALL _strayintr(SB); BYTE $0xC6
  1076. CALL _strayintr(SB); BYTE $0xC7
  1077. CALL _strayintr(SB); BYTE $0xC8
  1078. CALL _strayintr(SB); BYTE $0xC9
  1079. CALL _strayintr(SB); BYTE $0xCA
  1080. CALL _strayintr(SB); BYTE $0xCB
  1081. CALL _strayintr(SB); BYTE $0xCC
  1082. CALL _strayintr(SB); BYTE $0xCD
  1083. CALL _strayintr(SB); BYTE $0xCE
  1084. CALL _strayintr(SB); BYTE $0xCF
  1085. CALL _strayintr(SB); BYTE $0xD0
  1086. CALL _strayintr(SB); BYTE $0xD1
  1087. CALL _strayintr(SB); BYTE $0xD2
  1088. CALL _strayintr(SB); BYTE $0xD3
  1089. CALL _strayintr(SB); BYTE $0xD4
  1090. CALL _strayintr(SB); BYTE $0xD5
  1091. CALL _strayintr(SB); BYTE $0xD6
  1092. CALL _strayintr(SB); BYTE $0xD7
  1093. CALL _strayintr(SB); BYTE $0xD8
  1094. CALL _strayintr(SB); BYTE $0xD9
  1095. CALL _strayintr(SB); BYTE $0xDA
  1096. CALL _strayintr(SB); BYTE $0xDB
  1097. CALL _strayintr(SB); BYTE $0xDC
  1098. CALL _strayintr(SB); BYTE $0xDD
  1099. CALL _strayintr(SB); BYTE $0xDE
  1100. CALL _strayintr(SB); BYTE $0xDF
  1101. CALL _strayintr(SB); BYTE $0xE0
  1102. CALL _strayintr(SB); BYTE $0xE1
  1103. CALL _strayintr(SB); BYTE $0xE2
  1104. CALL _strayintr(SB); BYTE $0xE3
  1105. CALL _strayintr(SB); BYTE $0xE4
  1106. CALL _strayintr(SB); BYTE $0xE5
  1107. CALL _strayintr(SB); BYTE $0xE6
  1108. CALL _strayintr(SB); BYTE $0xE7
  1109. CALL _strayintr(SB); BYTE $0xE8
  1110. CALL _strayintr(SB); BYTE $0xE9
  1111. CALL _strayintr(SB); BYTE $0xEA
  1112. CALL _strayintr(SB); BYTE $0xEB
  1113. CALL _strayintr(SB); BYTE $0xEC
  1114. CALL _strayintr(SB); BYTE $0xED
  1115. CALL _strayintr(SB); BYTE $0xEE
  1116. CALL _strayintr(SB); BYTE $0xEF
  1117. CALL _strayintr(SB); BYTE $0xF0
  1118. CALL _strayintr(SB); BYTE $0xF1
  1119. CALL _strayintr(SB); BYTE $0xF2
  1120. CALL _strayintr(SB); BYTE $0xF3
  1121. CALL _strayintr(SB); BYTE $0xF4
  1122. CALL _strayintr(SB); BYTE $0xF5
  1123. CALL _strayintr(SB); BYTE $0xF6
  1124. CALL _strayintr(SB); BYTE $0xF7
  1125. CALL _strayintr(SB); BYTE $0xF8
  1126. CALL _strayintr(SB); BYTE $0xF9
  1127. CALL _strayintr(SB); BYTE $0xFA
  1128. CALL _strayintr(SB); BYTE $0xFB
  1129. CALL _strayintr(SB); BYTE $0xFC
  1130. CALL _strayintr(SB); BYTE $0xFD
  1131. CALL _strayintr(SB); BYTE $0xFE
  1132. CALL _strayintr(SB); BYTE $0xFF