sdiahci.c 38 KB

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  1. /*
  2. * intel/amd ahci sata controller
  3. * copyright © 2007 coraid, inc.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #include "../port/sd.h"
  13. #include "ahci.h"
  14. #define dprint(...) if(debug) iprint(__VA_ARGS__); else USED(debug)
  15. #define idprint(...) if(prid) print(__VA_ARGS__); else USED(prid)
  16. #define aprint(...) if(datapi) print(__VA_ARGS__); else USED(datapi)
  17. #define Tname(c) tname[(c)->type]
  18. enum {
  19. NCtlr = 4,
  20. NCtlrdrv= 32,
  21. NDrive = NCtlr*NCtlrdrv,
  22. Read = 0,
  23. Write,
  24. };
  25. /* pci space configuration */
  26. enum {
  27. Pmap = 0x90,
  28. Ppcs = 0x91,
  29. Prev = 0xa8,
  30. };
  31. enum {
  32. Tesb,
  33. Tich,
  34. Tsb600,
  35. };
  36. #define Intel(x) ((x) == Tesb || (x) == Tich)
  37. static char *tname[] = {
  38. "63xxesb",
  39. "ich",
  40. "sb600",
  41. };
  42. enum {
  43. Dnull,
  44. Dmissing,
  45. Dnew,
  46. Dready,
  47. Derror,
  48. Dreset,
  49. Doffline,
  50. Dportreset,
  51. Dlast,
  52. };
  53. static char *diskstates[Dlast] = {
  54. "null",
  55. "missing",
  56. "new",
  57. "ready",
  58. "error",
  59. "reset",
  60. "offline",
  61. "portreset",
  62. };
  63. extern SDifc sdiahciifc;
  64. typedef struct Ctlr Ctlr;
  65. enum {
  66. DMautoneg,
  67. DMsatai,
  68. DMsataii,
  69. };
  70. static char *modename[] = {
  71. "auto",
  72. "satai",
  73. "sataii",
  74. };
  75. static char *flagname[] = {
  76. "llba",
  77. "smart",
  78. "power",
  79. "nop",
  80. "atapi",
  81. "atapi16",
  82. };
  83. typedef struct {
  84. Lock;
  85. Ctlr *ctlr;
  86. SDunit *unit;
  87. char name[10];
  88. Aport *port;
  89. Aportm portm;
  90. Aportc portc; /* redundant ptr to port and portm. */
  91. uchar mediachange;
  92. uchar state;
  93. uchar smartrs;
  94. uvlong sectors;
  95. ulong intick;
  96. ulong lastseen;
  97. int wait;
  98. uchar mode; /* DMautoneg, satai or sataii. */
  99. uchar active;
  100. char serial[20+1];
  101. char firmware[8+1];
  102. char model[40+1];
  103. ushort info[0x200];
  104. int driveno; /* ctlr*NCtlrdrv + unit */
  105. /* controller port # != driveno when not all ports are enabled */
  106. int portno;
  107. } Drive;
  108. struct Ctlr {
  109. Lock;
  110. int type;
  111. int enabled;
  112. SDev *sdev;
  113. Pcidev *pci;
  114. uchar *mmio;
  115. ulong *lmmio;
  116. Ahba *hba;
  117. Drive rawdrive[NCtlrdrv];
  118. Drive* drive[NCtlrdrv];
  119. int ndrive;
  120. };
  121. static Ctlr iactlr[NCtlr];
  122. static SDev sdevs[NCtlr];
  123. static int niactlr;
  124. static Drive *iadrive[NDrive];
  125. static int niadrive;
  126. static int debug;
  127. static int prid = 1;
  128. static int datapi;
  129. static char stab[] = {
  130. [0] 'i', 'm',
  131. [8] 't', 'c', 'p', 'e',
  132. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  133. };
  134. static void
  135. serrstr(ulong r, char *s, char *e)
  136. {
  137. int i;
  138. e -= 3;
  139. for(i = 0; i < nelem(stab) && s < e; i++)
  140. if(r & (1<<i) && stab[i]){
  141. *s++ = stab[i];
  142. if(SerrBad & (1<<i))
  143. *s++ = '*';
  144. }
  145. *s = 0;
  146. }
  147. static char ntab[] = "0123456789abcdef";
  148. static void
  149. preg(uchar *reg, int n)
  150. {
  151. int i;
  152. char buf[25*3+1], *e;
  153. e = buf;
  154. for(i = 0; i < n; i++){
  155. *e++ = ntab[reg[i]>>4];
  156. *e++ = ntab[reg[i]&0xf];
  157. *e++ = ' ';
  158. }
  159. *e++ = '\n';
  160. *e = 0;
  161. dprint(buf);
  162. }
  163. static void
  164. dreg(char *s, Aport *p)
  165. {
  166. dprint("%stask=%lux; cmd=%lux; ci=%lux; is=%lux\n", s, p->task, p->cmd,
  167. p->ci, p->isr);
  168. }
  169. static void
  170. esleep(int ms)
  171. {
  172. if(waserror())
  173. return;
  174. tsleep(&up->sleep, return0, 0, ms);
  175. poperror();
  176. }
  177. typedef struct {
  178. Aport *p;
  179. int i;
  180. }Asleep;
  181. static int
  182. ahciclear(void *v)
  183. {
  184. Asleep *s;
  185. s = v;
  186. return (s->p->ci & s->i) == 0;
  187. }
  188. static void
  189. aesleep(Aportm *m, Asleep *a, int ms)
  190. {
  191. if(waserror())
  192. return;
  193. tsleep(m, ahciclear, a, ms);
  194. poperror();
  195. }
  196. static int
  197. ahciwait(Aportc *c, int ms)
  198. {
  199. Asleep as;
  200. Aport *p;
  201. p = c->p;
  202. p->ci = 1;
  203. as.p = p;
  204. as.i = 1;
  205. aesleep(c->m, &as, ms);
  206. if((p->task&1) == 0 && p->ci == 0)
  207. return 0;
  208. dreg("ahciwait timeout ", c->p);
  209. return -1;
  210. }
  211. static int
  212. nop(Aportc *pc)
  213. {
  214. uchar *c;
  215. Actab *t;
  216. Alist *l;
  217. if((pc->m->feat & Dnop) == 0)
  218. return -1;
  219. t = pc->m->ctab;
  220. c = t->cfis;
  221. memset(c, 0, 0x20);
  222. c[0] = 0x27;
  223. c[1] = 0x80;
  224. c[2] = 0x00;
  225. c[7] = 0xa0; /* obsolete device bits */
  226. l = pc->m->list;
  227. l->flags = Lwrite | 0x5;
  228. l->len = 0;
  229. l->ctab = PCIWADDR(t);
  230. l->ctabhi = 0;
  231. return ahciwait(pc, 3*1000);
  232. }
  233. static int
  234. setfeatures(Aportc *pc, uchar f)
  235. {
  236. uchar *c;
  237. Actab *t;
  238. Alist *l;
  239. t = pc->m->ctab;
  240. c = t->cfis;
  241. memset(c, 0, 0x20);
  242. c[0] = 0x27;
  243. c[1] = 0x80;
  244. c[2] = 0xef;
  245. c[3] = f;
  246. c[7] = 0xa0; /* obsolete device bits */
  247. l = pc->m->list;
  248. l->flags = Lwrite | 0x5;
  249. l->len = 0;
  250. l->ctab = PCIWADDR(t);
  251. l->ctabhi = 0;
  252. return ahciwait(pc, 3*1000);
  253. }
  254. static int
  255. setudmamode(Aportc *pc, uchar f)
  256. {
  257. uchar *c;
  258. Actab *t;
  259. Alist *l;
  260. /* hack */
  261. if((pc->p->sig >> 16) == 0xeb14)
  262. return 0;
  263. t = pc->m->ctab;
  264. c = t->cfis;
  265. memset(c, 0, 0x20);
  266. c[0] = 0x27;
  267. c[1] = 0x80;
  268. c[2] = 0xef;
  269. c[3] = 3; /* set transfer mode */
  270. c[7] = 0xa0; /* obsolete device bits */
  271. c[12] = 0x40 | f; /* sector count */
  272. l = pc->m->list;
  273. l->flags = Lwrite | 0x5;
  274. l->len = 0;
  275. l->ctab = PCIWADDR(t);
  276. l->ctabhi = 0;
  277. return ahciwait(pc, 3*1000);
  278. }
  279. static void
  280. asleep(int ms)
  281. {
  282. if(up == nil)
  283. delay(ms);
  284. else
  285. esleep(ms);
  286. }
  287. static int
  288. ahciportreset(Aportc *c)
  289. {
  290. ulong *cmd, i;
  291. Aport *p;
  292. p = c->p;
  293. cmd = &p->cmd;
  294. *cmd &= ~(Afre|Ast);
  295. for(i = 0; i < 500; i += 25){
  296. if((*cmd&Acr) == 0)
  297. break;
  298. asleep(25);
  299. }
  300. p->sctl = 1|(p->sctl&~7);
  301. delay(1);
  302. p->sctl &= ~7;
  303. return 0;
  304. }
  305. static int
  306. smart(Aportc *pc, int n)
  307. {
  308. uchar *c;
  309. Actab *t;
  310. Alist *l;
  311. if((pc->m->feat&Dsmart) == 0)
  312. return -1;
  313. t = pc->m->ctab;
  314. c = t->cfis;
  315. memset(c, 0, 0x20);
  316. c[0] = 0x27;
  317. c[1] = 0x80;
  318. c[2] = 0xb0;
  319. c[3] = 0xd8 + n; /* able smart */
  320. c[5] = 0x4f;
  321. c[6] = 0xc2;
  322. c[7] = 0xa0;
  323. l = pc->m->list;
  324. l->flags = Lwrite | 0x5;
  325. l->len = 0;
  326. l->ctab = PCIWADDR(t);
  327. l->ctabhi = 0;
  328. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  329. dprint("smart fail %lux\n", pc->p->task);
  330. // preg(pc->m->fis.r, 20);
  331. return -1;
  332. }
  333. if(n)
  334. return 0;
  335. return 1;
  336. }
  337. static int
  338. smartrs(Aportc *pc)
  339. {
  340. uchar *c;
  341. Actab *t;
  342. Alist *l;
  343. t = pc->m->ctab;
  344. c = t->cfis;
  345. memset(c, 0, 0x20);
  346. c[0] = 0x27;
  347. c[1] = 0x80;
  348. c[2] = 0xb0;
  349. c[3] = 0xda; /* return smart status */
  350. c[5] = 0x4f;
  351. c[6] = 0xc2;
  352. c[7] = 0xa0;
  353. l = pc->m->list;
  354. l->flags = Lwrite | 0x5;
  355. l->len = 0;
  356. l->ctab = PCIWADDR(t);
  357. l->ctabhi = 0;
  358. c = pc->m->fis.r;
  359. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  360. dprint("smart fail %lux\n", pc->p->task);
  361. preg(c, 20);
  362. return -1;
  363. }
  364. if(c[5] == 0x4f && c[6] == 0xc2)
  365. return 1;
  366. return 0;
  367. }
  368. static int
  369. ahciflushcache(Aportc *pc)
  370. {
  371. uchar *c, llba;
  372. Actab *t;
  373. Alist *l;
  374. static uchar tab[2] = {0xe7, 0xea};
  375. llba = pc->m->feat&Dllba? 1: 0;
  376. t = pc->m->ctab;
  377. c = t->cfis;
  378. memset(c, 0, 0x20);
  379. c[0] = 0x27;
  380. c[1] = 0x80;
  381. c[2] = tab[llba];
  382. c[7] = 0xa0;
  383. l = pc->m->list;
  384. l->flags = Lwrite | 0x5;
  385. l->len = 0;
  386. l->ctab = PCIWADDR(t);
  387. l->ctabhi = 0;
  388. if(ahciwait(pc, 60000) == -1 || pc->p->task & (1|32)){
  389. dprint("ahciflushcache fail %lux\n", pc->p->task);
  390. // preg( pc->m->fis.r, 20);
  391. return -1;
  392. }
  393. return 0;
  394. }
  395. static ushort
  396. gbit16(void *a)
  397. {
  398. ushort j;
  399. uchar *i;
  400. i = a;
  401. j = i[1] << 8;
  402. j |= i[0];
  403. return j;
  404. }
  405. static ulong
  406. gbit32(void *a)
  407. {
  408. ulong j;
  409. uchar *i;
  410. i = a;
  411. j = i[3] << 24;
  412. j |= i[2] << 16;
  413. j |= i[1] << 8;
  414. j |= i[0];
  415. return j;
  416. }
  417. static uvlong
  418. gbit64(void *a)
  419. {
  420. uchar *i;
  421. i = a;
  422. return (uvlong)gbit32(i+4) << 32 | gbit32(a);
  423. }
  424. static int
  425. ahciidentify0(Aportc *pc, void *id, int atapi)
  426. {
  427. uchar *c;
  428. Actab *t;
  429. Alist *l;
  430. Aprdt *p;
  431. static uchar tab[] = { 0xec, 0xa1, };
  432. t = pc->m->ctab;
  433. c = t->cfis;
  434. memset(c, 0, 0x20);
  435. c[0] = 0x27;
  436. c[1] = 0x80;
  437. c[2] = tab[atapi];
  438. c[7] = 0xa0; /* obsolete device bits */
  439. l = pc->m->list;
  440. l->flags = 1<<16 | 0x5;
  441. l->len = 0;
  442. l->ctab = PCIWADDR(t);
  443. l->ctabhi = 0;
  444. memset(id, 0, 0x100);
  445. p = &t->prdt;
  446. p->dba = PCIWADDR(id);
  447. p->dbahi = 0;
  448. p->count = 1<<31 | (0x200-2) | 1;
  449. return ahciwait(pc, 3*1000);
  450. }
  451. static vlong
  452. ahciidentify(Aportc *pc, ushort *id)
  453. {
  454. int i, sig;
  455. vlong s;
  456. Aportm *m;
  457. m = pc->m;
  458. m->feat = 0;
  459. m->smart = 0;
  460. i = 0;
  461. sig = pc->p->sig >> 16;
  462. if(sig == 0xeb14){
  463. m->feat |= Datapi;
  464. i = 1;
  465. }
  466. if(ahciidentify0(pc, id, i) == -1)
  467. return -1;
  468. i = gbit16(id+83) | gbit16(id+86);
  469. if(i & (1<<10)){
  470. m->feat |= Dllba;
  471. s = gbit64(id+100);
  472. }else
  473. s = gbit32(id+60);
  474. if(m->feat&Datapi){
  475. i = gbit16(id+0);
  476. if(i&1)
  477. m->feat |= Datapi16;
  478. }
  479. i = gbit16(id+83);
  480. if((i>>14) == 1) {
  481. if(i & (1<<3))
  482. m->feat |= Dpower;
  483. i = gbit16(id+82);
  484. if(i & 1)
  485. m->feat |= Dsmart;
  486. if(i & (1<<14))
  487. m->feat |= Dnop;
  488. }
  489. return s;
  490. }
  491. static int
  492. ahciquiet(Aport *a)
  493. {
  494. ulong *p, i;
  495. p = &a->cmd;
  496. *p &= ~Ast;
  497. for(i = 0; i < 500; i += 50){
  498. if((*p & Acr) == 0)
  499. goto stop;
  500. asleep(50);
  501. }
  502. return -1;
  503. stop:
  504. if((a->task & (ASdrq|ASbsy)) == 0){
  505. *p |= Ast;
  506. return 0;
  507. }
  508. *p |= Aclo;
  509. for(i = 0; i < 500; i += 50){
  510. if((*p & Aclo) == 0)
  511. goto stop1;
  512. asleep(50);
  513. }
  514. return -1;
  515. stop1:
  516. /* extra check */
  517. dprint("clo clear %lx\n", a->task);
  518. if(a->task & ASbsy)
  519. return -1;
  520. *p |= Ast;
  521. return 0;
  522. }
  523. static int
  524. ahcicomreset(Aportc *pc)
  525. {
  526. uchar *c;
  527. Actab *t;
  528. Alist *l;
  529. dprint("ahcicomreset\n");
  530. dreg("comreset ", pc->p);
  531. if(ahciquiet(pc->p) == -1){
  532. dprint("ahciquiet fails\n");
  533. return -1;
  534. }
  535. dreg("comreset ", pc->p);
  536. t = pc->m->ctab;
  537. c = t->cfis;
  538. memset(c, 0, 0x20);
  539. c[0] = 0x27;
  540. c[1] = 0x00;
  541. c[7] = 0xa0; /* obsolete device bits */
  542. c[15] = 1<<2; /* srst */
  543. l = pc->m->list;
  544. l->flags = Lclear | Lreset | 0x5;
  545. l->len = 0;
  546. l->ctab = PCIWADDR(t);
  547. l->ctabhi = 0;
  548. if(ahciwait(pc, 500) == -1){
  549. dprint("first command in comreset fails\n");
  550. return -1;
  551. }
  552. microdelay(250);
  553. dreg("comreset ", pc->p);
  554. memset(c, 0, 0x20);
  555. c[0] = 0x27;
  556. c[1] = 0x00;
  557. c[7] = 0xa0; /* obsolete device bits */
  558. l = pc->m->list;
  559. l->flags = Lwrite | 0x5;
  560. l->len = 0;
  561. l->ctab = PCIWADDR(t);
  562. l->ctabhi = 0;
  563. if(ahciwait(pc, 150) == -1){
  564. dprint("second command in comreset fails\n");
  565. return -1;
  566. }
  567. dreg("comreset ", pc->p);
  568. return 0;
  569. }
  570. static int
  571. ahciidle(Aport *port)
  572. {
  573. ulong *p, i, r;
  574. p = &port->cmd;
  575. if((*p & Arun) == 0)
  576. return 0;
  577. *p &= ~Ast;
  578. r = 0;
  579. for(i = 0; i < 500; i += 25){
  580. if((*p & Acr) == 0)
  581. goto stop;
  582. asleep(25);
  583. }
  584. r = -1;
  585. stop:
  586. if((*p & Afre) == 0)
  587. return r;
  588. *p &= ~Afre;
  589. for(i = 0; i < 500; i += 25){
  590. if((*p & Afre) == 0)
  591. return 0;
  592. asleep(25);
  593. }
  594. return -1;
  595. }
  596. /*
  597. * § 6.2.2.1 first part; comreset handled by reset disk.
  598. * - remainder is handled by configdisk.
  599. * - ahcirecover is a quick recovery from a failed command.
  600. */
  601. static int
  602. ahciswreset(Aportc *pc)
  603. {
  604. int i;
  605. i = ahciidle(pc->p);
  606. pc->p->cmd |= Afre;
  607. if(i == -1)
  608. return -1;
  609. if(pc->p->task & (ASdrq|ASbsy))
  610. return -1;
  611. return 0;
  612. }
  613. static int
  614. ahcirecover(Aportc *pc)
  615. {
  616. ahciswreset(pc);
  617. pc->p->cmd |= Ast;
  618. if(setudmamode(pc, 5) == -1)
  619. return -1;
  620. return 0;
  621. }
  622. static void*
  623. malign(int size, int align)
  624. {
  625. void *v;
  626. v = xspanalloc(size, align, 0);
  627. memset(v, 0, size);
  628. return v;
  629. }
  630. static void
  631. setupfis(Afis *f)
  632. {
  633. f->base = malign(0x100, 0x100);
  634. f->d = f->base + 0;
  635. f->p = f->base + 0x20;
  636. f->r = f->base + 0x40;
  637. f->u = f->base + 0x60;
  638. f->devicebits = (ulong*)(f->base + 0x58);
  639. }
  640. static void
  641. ahciwakeup(Aport *p)
  642. {
  643. ushort s;
  644. s = p->sstatus;
  645. if((s & 0xF00) != 0x600)
  646. return;
  647. if((s & 7) != 1){ /* not (device, no phy) */
  648. iprint("ahci: slumbering drive unwakeable %ux\n", s);
  649. return;
  650. }
  651. p->sctl = 3*Aipm | 0*Aspd | Adet;
  652. delay(1);
  653. p->sctl &= ~7;
  654. // iprint("ahci: wake %ux -> %ux\n", s, p->sstatus);
  655. }
  656. static int
  657. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  658. {
  659. Aportm *m;
  660. Aport *p;
  661. p = c->p;
  662. m = c->m;
  663. if(m->list == 0){
  664. setupfis(&m->fis);
  665. m->list = malign(sizeof *m->list, 1024);
  666. m->ctab = malign(sizeof *m->ctab, 128);
  667. }
  668. if(p->sstatus & 3 && h->cap & Hsss){
  669. /* device connected & staggered spin-up */
  670. dprint("configdrive: spinning up ... [%lux]\n", p->sstatus);
  671. p->cmd |= Apod|Asud;
  672. asleep(1400);
  673. }
  674. p->serror = SerrAll;
  675. p->list = PCIWADDR(m->list);
  676. p->listhi = 0;
  677. p->fis = PCIWADDR(m->fis.base);
  678. p->fishi = 0;
  679. p->cmd |= Afre|Ast;
  680. if((p->sstatus & 0xF0F) == 0x601) /* drive coming up in slumbering? */
  681. ahciwakeup(p);
  682. /* disable power managment sequence from book. */
  683. p->sctl = (3*Aipm) | (mode*Aspd) | 0*Adet;
  684. p->cmd &= ~Aalpe;
  685. p->ie = IEM;
  686. return 0;
  687. }
  688. static int
  689. ahcienable(Ahba *h)
  690. {
  691. h->ghc |= Hie;
  692. return 0;
  693. }
  694. static int
  695. ahcidisable(Ahba *h)
  696. {
  697. h->ghc &= ~Hie;
  698. return 0;
  699. }
  700. static int
  701. countbits(ulong u)
  702. {
  703. int i, n;
  704. n = 0;
  705. for(i = 0; i < 32; i++)
  706. if(u & (1<<i))
  707. n++;
  708. return n;
  709. }
  710. static int
  711. ahciconf(Ctlr *ctlr)
  712. {
  713. Ahba *h;
  714. ulong u;
  715. h = ctlr->hba = (Ahba*)ctlr->mmio;
  716. u = h->cap;
  717. if((u&Hsam) == 0)
  718. h->ghc |= Hae;
  719. print("#S/sd%c: ahci: port %#p: hba sss %ld; ncs %ld; coal %ld; "
  720. "mports %ld; led %ld; clo %ld; ems %ld\n",
  721. ctlr->sdev->idno, h,
  722. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  723. (u>>24) & 1, (u>>6) & 1);
  724. return countbits(h->pi);
  725. }
  726. static int
  727. ahcihbareset(Ahba *h)
  728. {
  729. int wait;
  730. h->ghc |= 1;
  731. for(wait = 0; wait < 1000; wait += 100){
  732. if(h->ghc == 0)
  733. return 0;
  734. delay(100);
  735. }
  736. return -1;
  737. }
  738. static void
  739. idmove(char *p, ushort *a, int n)
  740. {
  741. int i;
  742. char *op, *e;
  743. op = p;
  744. for(i = 0; i < n/2; i++){
  745. *p++ = a[i] >> 8;
  746. *p++ = a[i];
  747. }
  748. *p = 0;
  749. while(p > op && *--p == ' ')
  750. *p = 0;
  751. e = p;
  752. p = op;
  753. while(*p == ' ')
  754. p++;
  755. memmove(op, p, n - (e - p));
  756. }
  757. static int
  758. identify(Drive *d)
  759. {
  760. ushort *id;
  761. vlong osectors, s;
  762. uchar oserial[21];
  763. SDunit *u;
  764. id = d->info;
  765. s = ahciidentify(&d->portc, id);
  766. if(s == -1){
  767. d->state = Derror;
  768. return -1;
  769. }
  770. osectors = d->sectors;
  771. memmove(oserial, d->serial, sizeof d->serial);
  772. d->sectors = s;
  773. d->smartrs = 0;
  774. idmove(d->serial, id+10, 20);
  775. idmove(d->firmware, id+23, 8);
  776. idmove(d->model, id+27, 40);
  777. u = d->unit;
  778. memset(u->inquiry, 0, sizeof u->inquiry);
  779. u->inquiry[2] = 2;
  780. u->inquiry[3] = 2;
  781. u->inquiry[4] = sizeof u->inquiry - 4;
  782. memmove(u->inquiry+8, d->model, 40);
  783. if((osectors == 0 || osectors != s) &&
  784. memcmp(oserial, d->serial, sizeof oserial) != 0){
  785. d->mediachange = 1;
  786. u->sectors = 0;
  787. }
  788. return 0;
  789. }
  790. static void
  791. clearci(Aport *p)
  792. {
  793. if(p->cmd & Ast) {
  794. p->cmd &= ~Ast;
  795. p->cmd |= Ast;
  796. }
  797. }
  798. static void
  799. updatedrive(Drive *d)
  800. {
  801. ulong cause, serr, s0, pr, ewake;
  802. char *name;
  803. Aport *p;
  804. static ulong last;
  805. pr = 1;
  806. ewake = 0;
  807. p = d->port;
  808. cause = p->isr;
  809. serr = p->serror;
  810. p->isr = cause;
  811. name = "??";
  812. if(d->unit && d->unit->name)
  813. name = d->unit->name;
  814. if(p->ci == 0){
  815. d->portm.flag |= Fdone;
  816. wakeup(&d->portm);
  817. pr = 0;
  818. }else if(cause & Adps)
  819. pr = 0;
  820. if(cause & Ifatal){
  821. ewake = 1;
  822. dprint("Fatal\n");
  823. }
  824. if(cause & Adhrs){
  825. if(p->task & 33){
  826. dprint("Adhrs cause = %lux; serr = %lux; task=%lux\n",
  827. cause, serr, p->task);
  828. d->portm.flag |= Ferror;
  829. ewake = 1;
  830. }
  831. pr = 0;
  832. }
  833. if(p->task & 1 && last != cause)
  834. dprint("err ca %lux serr %lux task %lux sstat %lux\n",
  835. cause, serr, p->task, p->sstatus);
  836. if(pr)
  837. dprint("%s: upd %lux ta %lux\n", name, cause, p->task);
  838. if(cause & (Aprcs|Aifs)){
  839. s0 = d->state;
  840. switch(p->sstatus & 7){
  841. case 0: /* no device */
  842. d->state = Dmissing;
  843. break;
  844. case 1: /* device but no phy comm. */
  845. if((p->sstatus & 0xF00) == 0x600)
  846. d->state = Dnew; /* slumbering */
  847. else
  848. d->state = Derror;
  849. break;
  850. case 3: /* device & phy comm. estab. */
  851. /* power mgnt crap for suprise removal */
  852. p->ie |= Aprcs|Apcs; /* is this required? */
  853. d->state = Dreset;
  854. break;
  855. case 4: /* phy off-line */
  856. d->state = Doffline;
  857. break;
  858. }
  859. dprint("%s: %s → %s [Apcrs] %lux\n", name, diskstates[s0],
  860. diskstates[d->state], p->sstatus);
  861. /* print pulled message here. */
  862. if(s0 == Dready && d->state != Dready)
  863. idprint("%s: pulled\n", name);
  864. if(d->state != Dready)
  865. d->portm.flag |= Ferror;
  866. ewake = 1;
  867. }
  868. p->serror = serr;
  869. if(ewake){
  870. clearci(p);
  871. wakeup(&d->portm);
  872. }
  873. last = cause;
  874. }
  875. static void
  876. pstatus(Drive *d, ulong s)
  877. {
  878. /*
  879. * bogus code because the first interrupt is currently dropped.
  880. * likely my fault. serror is maybe cleared at the wrong time.
  881. */
  882. switch(s){
  883. case 0: /* no device */
  884. d->state = Dmissing;
  885. break;
  886. case 1: /* device but no phy. comm. */
  887. break;
  888. case 2: /* should this be missing? need testcase. */
  889. dprint("pstatus 2\n");
  890. /* fallthrough */
  891. case 3: /* device & phy. comm. */
  892. d->wait = 0;
  893. d->state = Dnew;
  894. break;
  895. case 4: /* offline */
  896. d->state = Doffline;
  897. break;
  898. case 6: /* ? not sure this makes sense. TODO */
  899. d->state = Dnew;
  900. break;
  901. }
  902. }
  903. static int
  904. configdrive(Drive *d)
  905. {
  906. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  907. return -1;
  908. ilock(d);
  909. pstatus(d, d->port->sstatus & 7);
  910. iunlock(d);
  911. return 0;
  912. }
  913. static void
  914. resetdisk(Drive *d)
  915. {
  916. uint state, det, stat;
  917. Aport *p;
  918. p = d->port;
  919. det = p->sctl & 7;
  920. stat = p->sstatus & 7;
  921. state = (p->cmd>>28) & 0xf;
  922. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  923. if(stat != 3){ /* device absent or phy not communicating? */
  924. ilock(d);
  925. d->state = Dportreset;
  926. iunlock(d);
  927. return;
  928. }
  929. ilock(d);
  930. state = d->state;
  931. if(d->state != Dready || d->state != Dnew)
  932. d->portm.flag |= Ferror;
  933. clearci(p); /* satisfy sleep condition. */
  934. wakeup(&d->portm);
  935. d->state = Derror;
  936. iunlock(d);
  937. qlock(&d->portm);
  938. if(p->cmd&Ast && ahciswreset(&d->portc) == -1){
  939. ilock(d);
  940. d->state = Dportreset; /* get a bigger stick. */
  941. iunlock(d);
  942. } else {
  943. ilock(d);
  944. d->state = Dmissing;
  945. iunlock(d);
  946. configdrive(d);
  947. }
  948. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  949. qunlock(&d->portm);
  950. }
  951. static int
  952. newdrive(Drive *d)
  953. {
  954. char *name, *s;
  955. Aportc *c;
  956. Aportm *m;
  957. c = &d->portc;
  958. m = &d->portm;
  959. name = d->unit->name;
  960. if(name == 0)
  961. name = "??";
  962. if(d->port->task == 0x80)
  963. return -1;
  964. qlock(c->m);
  965. if(setudmamode(c, 5) == -1){
  966. dprint("%s: can't set udma mode\n", name);
  967. goto lose;
  968. }
  969. if(identify(d) == -1){
  970. dprint("%s: identify failure\n", name);
  971. goto lose;
  972. }
  973. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  974. m->feat &= ~Dpower;
  975. if(ahcirecover(c) == -1)
  976. goto lose;
  977. }
  978. ilock(d);
  979. d->state = Dready;
  980. iunlock(d);
  981. qunlock(c->m);
  982. s = "";
  983. if(m->feat & Dllba)
  984. s = "L";
  985. idprint("%s: %sLBA %,lld sectors\n", d->unit->name, s, d->sectors);
  986. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  987. d->mediachange? "[mediachange]": "");
  988. return 0;
  989. lose:
  990. idprint("%s: can't be initialized\n", d->unit->name);
  991. ilock(d);
  992. d->state = Dnull;
  993. iunlock(d);
  994. qunlock(c->m);
  995. return -1;
  996. }
  997. enum {
  998. Nms = 256,
  999. Mphywait = 2*1024/Nms - 1,
  1000. Midwait = 16*1024/Nms - 1,
  1001. Mcomrwait = 64*1024/Nms - 1,
  1002. };
  1003. static void
  1004. westerndigitalhung(Drive *d)
  1005. {
  1006. if((d->portm.feat&Datapi) == 0 && d->active &&
  1007. TK2MS(MACHP(0)->ticks - d->intick) > 5000){
  1008. dprint("%s: drive hung; resetting [%lux] ci=%lx\n",
  1009. d->unit->name, d->port->task, d->port->ci);
  1010. d->state = Dreset;
  1011. }
  1012. }
  1013. static ushort olds[NCtlr*NCtlrdrv];
  1014. static int
  1015. doportreset(Drive *d)
  1016. {
  1017. int i;
  1018. i = -1;
  1019. qlock(&d->portm);
  1020. if(ahciportreset(&d->portc) == -1)
  1021. dprint("ahciportreset fails\n");
  1022. else
  1023. i = 0;
  1024. qunlock(&d->portm);
  1025. dprint("portreset → %s [task %lux]\n",
  1026. diskstates[d->state], d->port->task);
  1027. return i;
  1028. }
  1029. static void
  1030. checkdrive(Drive *d, int i)
  1031. {
  1032. ushort s;
  1033. char *name;
  1034. ilock(d);
  1035. name = d->unit->name;
  1036. s = d->port->sstatus;
  1037. if(s)
  1038. d->lastseen = MACHP(0)->ticks;
  1039. if(s != olds[i]){
  1040. dprint("%s: status: %04ux -> %04ux: %s\n",
  1041. name, olds[i], s, diskstates[d->state]);
  1042. olds[i] = s;
  1043. d->wait = 0;
  1044. }
  1045. westerndigitalhung(d);
  1046. switch(d->state){
  1047. case Dnull:
  1048. case Dready:
  1049. break;
  1050. case Dmissing:
  1051. case Dnew:
  1052. switch(s & 0x107){
  1053. case 1: /* no device (pm), device but no phy. comm. */
  1054. ahciwakeup(d->port);
  1055. /* fall through */
  1056. case 0: /* no device */
  1057. break;
  1058. default:
  1059. dprint("%s: unknown status %04ux\n", name, s);
  1060. /* fall through */
  1061. case 0x100: /* active, no device */
  1062. if(++d->wait&Mphywait)
  1063. break;
  1064. reset:
  1065. if(++d->mode > DMsataii)
  1066. d->mode = 0;
  1067. if(d->mode == DMsatai){ /* we tried everything */
  1068. d->state = Dportreset;
  1069. goto portreset;
  1070. }
  1071. dprint("%s: reset; new mode %s\n", name,
  1072. modename[d->mode]);
  1073. iunlock(d);
  1074. resetdisk(d);
  1075. ilock(d);
  1076. break;
  1077. case 0x103: /* active, device, phy. comm. */
  1078. if((++d->wait&Midwait) == 0){
  1079. dprint("%s: slow reset %04ux task=%lux; %d\n",
  1080. name, s, d->port->task, d->wait);
  1081. goto reset;
  1082. }
  1083. s = (uchar)d->port->task;
  1084. if(s == 0x7f || ((d->port->sig >> 16) != 0xeb14 &&
  1085. (s & ~0x17) != (1<<6)))
  1086. break;
  1087. iunlock(d);
  1088. newdrive(d);
  1089. ilock(d);
  1090. break;
  1091. }
  1092. break;
  1093. case Doffline:
  1094. if(d->wait++ & Mcomrwait)
  1095. break;
  1096. /* fallthrough */
  1097. case Derror:
  1098. case Dreset:
  1099. dprint("%s: reset [%s]: mode %d; status %04ux\n",
  1100. name, diskstates[d->state], d->mode, s);
  1101. iunlock(d);
  1102. resetdisk(d);
  1103. ilock(d);
  1104. break;
  1105. case Dportreset:
  1106. portreset:
  1107. if(d->wait++ & 0xff && (s & 0x100) == 0)
  1108. break;
  1109. /* device is active */
  1110. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  1111. name, diskstates[d->state], d->mode, s);
  1112. d->portm.flag |= Ferror;
  1113. clearci(d->port);
  1114. wakeup(&d->portm);
  1115. if((s & 7) == 0){ /* no device */
  1116. d->state = Dmissing;
  1117. break;
  1118. }
  1119. iunlock(d);
  1120. doportreset(d);
  1121. ilock(d);
  1122. break;
  1123. }
  1124. iunlock(d);
  1125. }
  1126. static void
  1127. satakproc(void*)
  1128. {
  1129. int i;
  1130. memset(olds, 0xff, sizeof olds);
  1131. for(;;){
  1132. tsleep(&up->sleep, return0, 0, Nms);
  1133. for(i = 0; i < niadrive; i++)
  1134. checkdrive(iadrive[i], i);
  1135. }
  1136. }
  1137. static void
  1138. iainterrupt(Ureg*, void *a)
  1139. {
  1140. int i;
  1141. ulong cause, m;
  1142. Ctlr *c;
  1143. Drive *d;
  1144. c = a;
  1145. ilock(c);
  1146. cause = c->hba->isr;
  1147. for(i = 0; i < c->ndrive; i++){
  1148. m = 1 << i;
  1149. if((cause & m) == 0)
  1150. continue;
  1151. d = c->rawdrive + i;
  1152. ilock(d);
  1153. if(d->port->isr && c->hba->pi & m)
  1154. updatedrive(d);
  1155. c->hba->isr = m;
  1156. iunlock(d);
  1157. }
  1158. iunlock(c);
  1159. }
  1160. static int
  1161. iaverify(SDunit *u)
  1162. {
  1163. Ctlr *c;
  1164. Drive *d;
  1165. c = u->dev->ctlr;
  1166. d = c->drive[u->subno];
  1167. ilock(c);
  1168. ilock(d);
  1169. d->unit = u;
  1170. iunlock(d);
  1171. iunlock(c);
  1172. checkdrive(d, d->driveno);
  1173. return 1;
  1174. }
  1175. static int
  1176. iaenable(SDev *s)
  1177. {
  1178. char name[32];
  1179. Ctlr *c;
  1180. static int once;
  1181. c = s->ctlr;
  1182. ilock(c);
  1183. if(!c->enabled) {
  1184. if(once == 0) {
  1185. once = 1;
  1186. kproc("iasata", satakproc, 0);
  1187. }
  1188. if(c->ndrive == 0)
  1189. panic("iaenable: zero s->ctlr->ndrive");
  1190. pcisetbme(c->pci);
  1191. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1192. intrenable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1193. /* supposed to squelch leftover interrupts here. */
  1194. ahcienable(c->hba);
  1195. c->enabled = 1;
  1196. }
  1197. iunlock(c);
  1198. return 1;
  1199. }
  1200. static int
  1201. iadisable(SDev *s)
  1202. {
  1203. char name[32];
  1204. Ctlr *c;
  1205. c = s->ctlr;
  1206. ilock(c);
  1207. ahcidisable(c->hba);
  1208. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1209. intrdisable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1210. c->enabled = 0;
  1211. iunlock(c);
  1212. return 1;
  1213. }
  1214. static int
  1215. iaonline(SDunit *unit)
  1216. {
  1217. int r;
  1218. Ctlr *c;
  1219. Drive *d;
  1220. c = unit->dev->ctlr;
  1221. d = c->drive[unit->subno];
  1222. r = 0;
  1223. if(d->portm.feat & Datapi && d->mediachange){
  1224. r = scsionline(unit);
  1225. if(r > 0)
  1226. d->mediachange = 0;
  1227. return r;
  1228. }
  1229. ilock(d);
  1230. if(d->mediachange){
  1231. r = 2;
  1232. d->mediachange = 0;
  1233. /* devsd resets this after online is called; why? */
  1234. unit->sectors = d->sectors;
  1235. unit->secsize = 512;
  1236. } else if(d->state == Dready)
  1237. r = 1;
  1238. iunlock(d);
  1239. return r;
  1240. }
  1241. /* returns locked list! */
  1242. static Alist*
  1243. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1244. {
  1245. uchar *c, acmd, dir, llba;
  1246. Alist *l;
  1247. Actab *t;
  1248. Aprdt *p;
  1249. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35, };
  1250. dir = *cmd != 0x28;
  1251. llba = m->feat&Dllba? 1: 0;
  1252. acmd = tab[dir][llba];
  1253. qlock(m);
  1254. l = m->list;
  1255. t = m->ctab;
  1256. c = t->cfis;
  1257. c[0] = 0x27;
  1258. c[1] = 0x80;
  1259. c[2] = acmd;
  1260. c[3] = 0;
  1261. c[4] = lba; /* sector lba low 7:0 */
  1262. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1263. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1264. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1265. if(llba == 0)
  1266. c[7] |= (lba>>24) & 7;
  1267. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1268. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1269. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1270. c[11] = 0; /* features (exp); */
  1271. c[12] = n; /* sector count */
  1272. c[13] = n >> 8; /* sector count (exp) */
  1273. c[14] = 0; /* r */
  1274. c[15] = 0; /* control */
  1275. *(ulong*)(c + 16) = 0;
  1276. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1277. if(dir == Write)
  1278. l->flags |= Lwrite;
  1279. l->len = 0;
  1280. l->ctab = PCIWADDR(t);
  1281. l->ctabhi = 0;
  1282. p = &t->prdt;
  1283. p->dba = PCIWADDR(data);
  1284. p->dbahi = 0;
  1285. p->count = 1<<31 | (512*n - 2) | 1;
  1286. return l;
  1287. }
  1288. static Alist*
  1289. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1290. {
  1291. int fill, len;
  1292. uchar *c;
  1293. Alist *l;
  1294. Actab *t;
  1295. Aprdt *p;
  1296. qlock(m);
  1297. l = m->list;
  1298. t = m->ctab;
  1299. c = t->cfis;
  1300. fill = m->feat&Datapi16? 16: 12;
  1301. if((len = r->clen) > fill)
  1302. len = fill;
  1303. memmove(t->atapi, r->cmd, len);
  1304. memset(t->atapi+len, 0, fill-len);
  1305. c[0] = 0x27;
  1306. c[1] = 0x80;
  1307. c[2] = 0xa0;
  1308. if(n != 0)
  1309. c[3] = 1; /* dma */
  1310. else
  1311. c[3] = 0; /* features (exp); */
  1312. c[4] = 0; /* sector lba low 7:0 */
  1313. c[5] = n; /* cylinder low lba mid 15:8 */
  1314. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1315. c[7] = 0xa0; /* obsolete device bits */
  1316. *(ulong*)(c + 8) = 0;
  1317. *(ulong*)(c + 12) = 0;
  1318. *(ulong*)(c + 16) = 0;
  1319. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1320. if(r->write != 0 && data)
  1321. l->flags |= Lwrite;
  1322. l->len = 0;
  1323. l->ctab = PCIWADDR(t);
  1324. l->ctabhi = 0;
  1325. if(data == 0)
  1326. return l;
  1327. p = &t->prdt;
  1328. p->dba = PCIWADDR(data);
  1329. p->dbahi = 0;
  1330. p->count = 1<<31 | (n - 2) | 1;
  1331. return l;
  1332. }
  1333. static int
  1334. waitready(Drive *d)
  1335. {
  1336. ulong s, i, δ;
  1337. for(i = 0; i < 15000; i += 250){
  1338. if(d->state == Dreset || d->state == Dportreset ||
  1339. d->state == Dnew)
  1340. return 1;
  1341. δ = MACHP(0)->ticks - d->lastseen;
  1342. if(d->state == Dnull || δ > 10*1000)
  1343. return -1;
  1344. ilock(d);
  1345. s = d->port->sstatus;
  1346. iunlock(d);
  1347. if((s & 0x700) == 0 && δ > 1500)
  1348. return -1; /* no detect */
  1349. if(d->state == Dready && (s & 7) == 3)
  1350. return 0; /* ready, present & phy. comm. */
  1351. esleep(250);
  1352. }
  1353. print("%s: not responding; offline\n", d->unit->name);
  1354. ilock(d);
  1355. d->state = Doffline;
  1356. iunlock(d);
  1357. return -1;
  1358. }
  1359. static int
  1360. lockready(Drive *d)
  1361. {
  1362. int i;
  1363. qlock(&d->portm);
  1364. while ((i = waitready(d)) == 1) {
  1365. qunlock(&d->portm);
  1366. esleep(1);
  1367. qlock(&d->portm);
  1368. }
  1369. return i;
  1370. }
  1371. static int
  1372. flushcache(Drive *d)
  1373. {
  1374. int i;
  1375. i = -1;
  1376. if(lockready(d) == 0)
  1377. i = ahciflushcache(&d->portc);
  1378. qunlock(&d->portm);
  1379. return i;
  1380. }
  1381. static int
  1382. iariopkt(SDreq *r, Drive *d)
  1383. {
  1384. int n, count, try, max, flag, task;
  1385. char *name;
  1386. uchar *cmd, *data;
  1387. Aport *p;
  1388. Asleep as;
  1389. cmd = r->cmd;
  1390. name = d->unit->name;
  1391. p = d->port;
  1392. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1393. r->dlen, r->data);
  1394. if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1395. return sdmodesense(r, cmd, d->info, sizeof d->info);
  1396. r->rlen = 0;
  1397. count = r->dlen;
  1398. max = 65536;
  1399. try = 0;
  1400. retry:
  1401. data = r->data;
  1402. n = count;
  1403. if(n > max)
  1404. n = max;
  1405. d->active++;
  1406. ahcibuildpkt(&d->portm, r, data, n);
  1407. switch(waitready(d)){
  1408. case -1:
  1409. qunlock(&d->portm);
  1410. return SDeio;
  1411. case 1:
  1412. qunlock(&d->portm);
  1413. esleep(1);
  1414. goto retry;
  1415. }
  1416. ilock(d);
  1417. d->portm.flag = 0;
  1418. iunlock(d);
  1419. p->ci = 1;
  1420. as.p = p;
  1421. as.i = 1;
  1422. d->intick = MACHP(0)->ticks;
  1423. while(waserror())
  1424. ;
  1425. sleep(&d->portm, ahciclear, &as);
  1426. poperror();
  1427. ilock(d);
  1428. flag = d->portm.flag;
  1429. task = d->port->task;
  1430. iunlock(d);
  1431. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1432. d->port->ci = 0; /* clearci? */
  1433. ahcirecover(&d->portc);
  1434. task = d->port->task;
  1435. flag &= ~Fdone; /* either an error or do-over */
  1436. }
  1437. d->active--;
  1438. qunlock(&d->portm);
  1439. if(flag == 0){
  1440. if(++try == 10){
  1441. print("%s: bad disk\n", name);
  1442. r->status = SDcheck;
  1443. return SDcheck;
  1444. }
  1445. print("%s: retry\n", name);
  1446. goto retry;
  1447. }
  1448. if(flag & Ferror){
  1449. if((task&Eidnf) == 0)
  1450. print("%s: i/o error %ux\n", name, task);
  1451. r->status = SDcheck;
  1452. return SDcheck;
  1453. }
  1454. data += n;
  1455. r->rlen = data - (uchar*)r->data;
  1456. r->status = SDok;
  1457. return SDok;
  1458. }
  1459. static int
  1460. iario(SDreq *r)
  1461. {
  1462. int i, n, count, try, max, flag, task;
  1463. vlong lba;
  1464. char *name;
  1465. uchar *cmd, *data;
  1466. Aport *p;
  1467. Asleep as;
  1468. Ctlr *c;
  1469. Drive *d;
  1470. SDunit *unit;
  1471. unit = r->unit;
  1472. c = unit->dev->ctlr;
  1473. d = c->drive[unit->subno];
  1474. if(d->portm.feat & Datapi)
  1475. return iariopkt(r, d);
  1476. cmd = r->cmd;
  1477. name = d->unit->name;
  1478. p = d->port;
  1479. if(r->cmd[0] == 0x35 || r->cmd[0] == 0x91){
  1480. if(flushcache(d) == 0)
  1481. return sdsetsense(r, SDok, 0, 0, 0);
  1482. return sdsetsense(r, SDcheck, 3, 0xc, 2);
  1483. }
  1484. if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1485. r->status = i;
  1486. return i;
  1487. }
  1488. if(*cmd != 0x28 && *cmd != 0x2a){
  1489. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1490. r->status = SDcheck;
  1491. return SDcheck;
  1492. }
  1493. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1494. count = cmd[7]<<8 | cmd[8];
  1495. if(r->data == nil)
  1496. return SDok;
  1497. if(r->dlen < count * unit->secsize)
  1498. count = r->dlen / unit->secsize;
  1499. max = 128;
  1500. try = 0;
  1501. retry:
  1502. data = r->data;
  1503. while(count > 0){
  1504. n = count;
  1505. if(n > max)
  1506. n = max;
  1507. d->active++;
  1508. ahcibuild(&d->portm, cmd, data, n, lba);
  1509. switch(waitready(d)){
  1510. case -1:
  1511. qunlock(&d->portm);
  1512. return SDeio;
  1513. case 1:
  1514. qunlock(&d->portm);
  1515. esleep(1);
  1516. goto retry;
  1517. }
  1518. ilock(d);
  1519. d->portm.flag = 0;
  1520. iunlock(d);
  1521. p->ci = 1;
  1522. as.p = p;
  1523. as.i = 1;
  1524. d->intick = MACHP(0)->ticks;
  1525. while(waserror())
  1526. ;
  1527. sleep(&d->portm, ahciclear, &as);
  1528. poperror();
  1529. ilock(d);
  1530. flag = d->portm.flag;
  1531. task = d->port->task;
  1532. iunlock(d);
  1533. if(task & (Efatal<<8) ||
  1534. task & (ASbsy|ASdrq) && d->state == Dready){
  1535. d->port->ci = 0; /* @? */
  1536. ahcirecover(&d->portc);
  1537. task = d->port->task;
  1538. }
  1539. d->active--;
  1540. qunlock(&d->portm);
  1541. if(flag == 0){
  1542. if(++try == 10){
  1543. print("%s: bad disk\n", name);
  1544. r->status = SDeio;
  1545. return SDeio;
  1546. }
  1547. iprint("%s: retry %lld\n", name, lba);
  1548. goto retry;
  1549. }
  1550. if(flag & Ferror){
  1551. iprint("%s: i/o error %ux @%,lld\n", name, task, lba);
  1552. r->status = SDeio;
  1553. return SDeio;
  1554. }
  1555. count -= n;
  1556. lba += n;
  1557. data += n * unit->secsize;
  1558. }
  1559. r->rlen = data - (uchar*)r->data;
  1560. r->status = SDok;
  1561. return SDok;
  1562. }
  1563. /*
  1564. * configure drives 0-5 as ahci sata (c.f. errata)
  1565. */
  1566. static int
  1567. iaahcimode(Pcidev *p)
  1568. {
  1569. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91), pcicfgr8(p, 92),
  1570. pcicfgr8(p, 93));
  1571. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1572. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1573. return 0;
  1574. }
  1575. static void
  1576. iasetupahci(Ctlr *c)
  1577. {
  1578. /* disable cmd block decoding. */
  1579. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1580. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1581. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1582. c->lmmio[0xc/4] = (1 << 6) - 1; /* 5 ports. (supposedly ro pi reg.) */
  1583. /* enable ahci mode; from ich9 datasheet */
  1584. pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
  1585. }
  1586. static SDev*
  1587. iapnp(void)
  1588. {
  1589. int i, n, nunit, type;
  1590. ulong io;
  1591. Ctlr *c;
  1592. Drive *d;
  1593. Pcidev *p;
  1594. SDev *head, *tail, *s;
  1595. static int done;
  1596. if(done++)
  1597. return nil;
  1598. p = nil;
  1599. head = tail = nil;
  1600. loop:
  1601. while((p = pcimatch(p, 0, 0)) != nil){
  1602. if(p->vid == 0x8086 && (p->did & 0xfffc) == 0x2680)
  1603. type = Tesb;
  1604. else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x27c4)
  1605. type = Tich; /* 82801g[bh]m */
  1606. else if(p->vid == 0x1002 && p->did == 0x4380)
  1607. type = Tsb600;
  1608. else
  1609. continue;
  1610. if (p->mem[Abar].bar == 0)
  1611. continue;
  1612. if(niactlr == NCtlr){
  1613. print("%spnp: too many controllers\n", tname[type]);
  1614. break;
  1615. }
  1616. c = iactlr + niactlr;
  1617. s = sdevs + niactlr;
  1618. memset(c, 0, sizeof *c);
  1619. memset(s, 0, sizeof *s);
  1620. io = p->mem[Abar].bar & ~0xf;
  1621. c->mmio = vmap(io, p->mem[Abar].size);
  1622. if(c->mmio == 0){
  1623. print("%s: address 0x%luX in use did=%x\n",
  1624. Tname(c), io, p->did);
  1625. continue;
  1626. }
  1627. c->lmmio = (ulong*)c->mmio;
  1628. c->pci = p;
  1629. c->type = type;
  1630. s->ifc = &sdiahciifc;
  1631. s->idno = 'E' + niactlr;
  1632. s->ctlr = c;
  1633. c->sdev = s;
  1634. if(Intel(c->type) && p->did != 0x2681)
  1635. iasetupahci(c);
  1636. nunit = ahciconf(c);
  1637. // ahcihbareset((Ahba*)c->mmio);
  1638. if(Intel(c->type) && iaahcimode(p) == -1)
  1639. break;
  1640. if(nunit < 1){
  1641. vunmap(c->mmio, p->mem[Abar].size);
  1642. continue;
  1643. }
  1644. c->ndrive = s->nunit = nunit;
  1645. i = (c->hba->cap >> 21) & 1;
  1646. print("#S/sd%c: %s: sata-%s with %d ports\n", s->idno,
  1647. Tname(c), "I\0II" + i*2, nunit);
  1648. /* map the drives -- they don't all need to be enabled. */
  1649. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1650. n = 0;
  1651. for(i = 0; i < NCtlrdrv; i++) {
  1652. d = c->rawdrive + i;
  1653. d->portno = i;
  1654. d->driveno = -1;
  1655. d->sectors = 0;
  1656. d->ctlr = c;
  1657. if((c->hba->pi & (1<<i)) == 0)
  1658. continue;
  1659. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1660. d->portc.p = d->port;
  1661. d->portc.m = &d->portm;
  1662. d->driveno = n++;
  1663. c->drive[d->driveno] = d;
  1664. iadrive[niadrive + d->driveno] = d;
  1665. }
  1666. for(i = 0; i < n; i++)
  1667. if(ahciidle(c->drive[i]->port) == -1){
  1668. dprint("%s: port %d wedged; abort\n",
  1669. Tname(c), i);
  1670. goto loop;
  1671. }
  1672. for(i = 0; i < n; i++){
  1673. c->drive[i]->mode = DMsatai;
  1674. configdrive(c->drive[i]);
  1675. }
  1676. niadrive += nunit;
  1677. niactlr++;
  1678. if(head)
  1679. tail->next = s;
  1680. else
  1681. head = s;
  1682. tail = s;
  1683. }
  1684. return head;
  1685. }
  1686. static char* smarttab[] = {
  1687. "unset",
  1688. "error",
  1689. "threshold exceeded",
  1690. "normal"
  1691. };
  1692. static char *
  1693. pflag(char *s, char *e, uchar f)
  1694. {
  1695. uchar i;
  1696. for(i = 0; i < 8; i++)
  1697. if(f & (1 << i))
  1698. s = seprint(s, e, "%s ", flagname[i]);
  1699. return seprint(s, e, "\n");
  1700. }
  1701. static int
  1702. iarctl(SDunit *u, char *p, int l)
  1703. {
  1704. char buf[32];
  1705. char *e, *op;
  1706. Aport *o;
  1707. Ctlr *c;
  1708. Drive *d;
  1709. if((c = u->dev->ctlr) == nil)
  1710. return 0;
  1711. d = c->drive[u->subno];
  1712. o = d->port;
  1713. e = p+l;
  1714. op = p;
  1715. if(d->state == Dready){
  1716. p = seprint(p, e, "model\t%s\n", d->model);
  1717. p = seprint(p, e, "serial\t%s\n", d->serial);
  1718. p = seprint(p, e, "firm\t%s\n", d->firmware);
  1719. if(d->smartrs == 0xff)
  1720. p = seprint(p, e, "smart\tenable error\n");
  1721. else if(d->smartrs == 0)
  1722. p = seprint(p, e, "smart\tdisabled\n");
  1723. else
  1724. p = seprint(p, e, "smart\t%s\n",
  1725. smarttab[d->portm.smart]);
  1726. p = seprint(p, e, "flag\t");
  1727. p = pflag(p, e, d->portm.feat);
  1728. }else
  1729. p = seprint(p, e, "no disk present [%s]\n", diskstates[d->state]);
  1730. serrstr(o->serror, buf, buf + sizeof buf - 1);
  1731. p = seprint(p, e, "reg\ttask %lux cmd %lux serr %lux %s ci %lux is %lux; "
  1732. "sig %lux sstatus %04lux\n", o->task, o->cmd, o->serror, buf,
  1733. o->ci, o->isr, o->sig, o->sstatus);
  1734. p = seprint(p, e, "geometry %llud 512\n", d->sectors);
  1735. return p - op;
  1736. }
  1737. static void
  1738. runflushcache(Drive *d)
  1739. {
  1740. long t0;
  1741. t0 = MACHP(0)->ticks;
  1742. if(flushcache(d) != 0)
  1743. error(Eio);
  1744. dprint("flush in %ldms\n", MACHP(0)->ticks - t0);
  1745. }
  1746. static void
  1747. forcemode(Drive *d, char *mode)
  1748. {
  1749. int i;
  1750. for(i = 0; i < nelem(modename); i++)
  1751. if(strcmp(mode, modename[i]) == 0)
  1752. break;
  1753. if(i == nelem(modename))
  1754. i = 0;
  1755. ilock(d);
  1756. d->mode = i;
  1757. iunlock(d);
  1758. }
  1759. static void
  1760. runsmartable(Drive *d, int i)
  1761. {
  1762. if(waserror()){
  1763. qunlock(&d->portm);
  1764. d->smartrs = 0;
  1765. nexterror();
  1766. }
  1767. if(lockready(d) == -1)
  1768. error(Eio);
  1769. d->smartrs = smart(&d->portc, i);
  1770. d->portm.smart = 0;
  1771. qunlock(&d->portm);
  1772. poperror();
  1773. }
  1774. static void
  1775. forcestate(Drive *d, char *state)
  1776. {
  1777. int i;
  1778. for(i = 0; i < nelem(diskstates); i++)
  1779. if(strcmp(state, diskstates[i]) == 0)
  1780. break;
  1781. if(i == nelem(diskstates))
  1782. i = 0;
  1783. ilock(d);
  1784. d->state = i;
  1785. if(i == Dnull){
  1786. d->mediachange = 1;
  1787. if(d->unit)
  1788. d->unit->sectors = 0; /* force disk to disappear. */
  1789. }
  1790. iunlock(d);
  1791. }
  1792. static int
  1793. iawctl(SDunit *u, Cmdbuf *cmd)
  1794. {
  1795. char **f;
  1796. Ctlr *c;
  1797. Drive *d;
  1798. uint i;
  1799. c = u->dev->ctlr;
  1800. d = c->drive[u->subno];
  1801. f = cmd->f;
  1802. if(strcmp(f[0], "flushcache") == 0)
  1803. runflushcache(d);
  1804. else if(strcmp(f[0], "identify") == 0){
  1805. i = strtoul(f[1]? f[1]: "0", 0, 0);
  1806. if(i > 0xff)
  1807. i = 0;
  1808. dprint("%04d %ux\n", i, d->info[i]);
  1809. }else if(strcmp(f[0], "mode") == 0)
  1810. forcemode(d, f[1]? f[1]: "satai");
  1811. else if(strcmp(f[0], "nop") == 0){
  1812. if((d->portm.feat & Dnop) == 0){
  1813. cmderror(cmd, "no drive support");
  1814. return -1;
  1815. }
  1816. if(waserror()){
  1817. qunlock(&d->portm);
  1818. nexterror();
  1819. }
  1820. if(lockready(d) == -1)
  1821. error(Eio);
  1822. nop(&d->portc);
  1823. qunlock(&d->portm);
  1824. poperror();
  1825. }else if(strcmp(f[0], "reset") == 0)
  1826. forcestate(d, "reset");
  1827. else if(strcmp(f[0], "smart") == 0){
  1828. if(d->smartrs == 0){
  1829. cmderror(cmd, "smart not enabled");
  1830. return -1;
  1831. }
  1832. if(waserror()){
  1833. qunlock(&d->portm);
  1834. d->smartrs = 0;
  1835. nexterror();
  1836. }
  1837. if(lockready(d) == -1)
  1838. error(Eio);
  1839. d->portm.smart = 2 + smartrs(&d->portc);
  1840. qunlock(&d->portm);
  1841. poperror();
  1842. }else if(strcmp(f[0], "smartdisable") == 0)
  1843. runsmartable(d, 1);
  1844. else if(strcmp(f[0], "smartenable") == 0)
  1845. runsmartable(d, 0);
  1846. else if(strcmp(f[0], "state") == 0)
  1847. forcestate(d, f[1]? f[1]: "null");
  1848. else{
  1849. cmderror(cmd, Ebadctl);
  1850. return -1;
  1851. }
  1852. return 0;
  1853. }
  1854. static char *
  1855. portr(char *p, char *e, uint x)
  1856. {
  1857. int i, a;
  1858. p[0] = 0;
  1859. a = -1;
  1860. for(i = 0; i < 32; i++){
  1861. if((x & (1<<i)) == 0){
  1862. if(a != -1 && i - 1 != a)
  1863. p = seprint(p, e, "-%d", i - 1);
  1864. a = -1;
  1865. continue;
  1866. }
  1867. if(a == -1){
  1868. if(i > 0)
  1869. p = seprint(p, e, ", ");
  1870. p = seprint(p, e, "%d", a = i);
  1871. }
  1872. }
  1873. if(a != -1 && i - 1 != a)
  1874. p = seprint(p, e, "-%d", i - 1);
  1875. return p;
  1876. }
  1877. /* must emit exactly one line per controller (sd(3)) */
  1878. static char*
  1879. iartopctl(SDev *sdev, char *p, char *e)
  1880. {
  1881. ulong cap;
  1882. char pr[25];
  1883. Ahba *hba;
  1884. Ctlr *ctlr;
  1885. #define has(x, str) if(cap & (x)) p = seprint(p, e, "%s ", (str))
  1886. ctlr = sdev->ctlr;
  1887. hba = ctlr->hba;
  1888. p = seprint(p, e, "sd%c ahci port %#p: ", sdev->idno, hba);
  1889. cap = hba->cap;
  1890. has(Hs64a, "64a");
  1891. has(Hsalp, "alp");
  1892. has(Hsam, "am");
  1893. has(Hsclo, "clo");
  1894. has(Hcccs, "coal");
  1895. has(Hems, "ems");
  1896. has(Hsal, "led");
  1897. has(Hsmps, "mps");
  1898. has(Hsncq, "ncq");
  1899. has(Hssntf, "ntf");
  1900. has(Hspm, "pm");
  1901. has(Hpsc, "pslum");
  1902. has(Hssc, "slum");
  1903. has(Hsss, "ss");
  1904. has(Hsxs, "sxs");
  1905. portr(pr, pr + sizeof pr, hba->pi);
  1906. return seprint(p, e,
  1907. "iss %ld ncs %ld np %ld; ghc %lux isr %lux pi %lux %s ver %lux\n",
  1908. (cap>>20) & 0xf, (cap>>8) & 0x1f, 1 + (cap & 0x1f),
  1909. hba->ghc, hba->isr, hba->pi, pr, hba->ver);
  1910. #undef has
  1911. }
  1912. static int
  1913. iawtopctl(SDev *, Cmdbuf *cmd)
  1914. {
  1915. int *v;
  1916. char **f;
  1917. f = cmd->f;
  1918. v = 0;
  1919. if(strcmp(f[0], "debug") == 0)
  1920. v = &debug;
  1921. else if(strcmp(f[0], "idprint") == 0)
  1922. v = &prid;
  1923. else if(strcmp(f[0], "aprint") == 0)
  1924. v = &datapi;
  1925. else
  1926. cmderror(cmd, Ebadctl);
  1927. switch(cmd->nf){
  1928. default:
  1929. cmderror(cmd, Ebadarg);
  1930. case 1:
  1931. *v ^= 1;
  1932. break;
  1933. case 2:
  1934. *v = (strcmp(f[1], "on") == 0);
  1935. break;
  1936. }
  1937. return 0;
  1938. }
  1939. SDifc sdiahciifc = {
  1940. "iahci",
  1941. iapnp,
  1942. nil, /* legacy */
  1943. iaenable,
  1944. iadisable,
  1945. iaverify,
  1946. iaonline,
  1947. iario,
  1948. iarctl,
  1949. iawctl,
  1950. scsibio,
  1951. nil, /* probe */
  1952. nil, /* clear */
  1953. iartopctl,
  1954. iawtopctl,
  1955. };