ether8003.c 6.3 KB

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  1. #include "u.h"
  2. #include "lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "etherif.h"
  8. #include "ether8390.h"
  9. /*
  10. * Western Digital/Standard Microsystems Corporation cards (WD80[01]3).
  11. * Also handles 8216 cards (Elite Ultra).
  12. * Configuration code based on that provided by SMC a long time ago.
  13. */
  14. enum { /* 83C584 Bus Interface Controller */
  15. Msr = 0x00, /* Memory Select Register */
  16. Icr = 0x01, /* Interface Configuration Register */
  17. Iar = 0x02, /* I/O Address Register */
  18. Bio = 0x03, /* BIOS ROM Address Register */
  19. Ear = 0x03, /* EEROM Address Register (shared with Bio) */
  20. Irr = 0x04, /* Interrupt Request Register */
  21. Hcr = 0x04, /* 8216 hardware control */
  22. Laar = 0x05, /* LA Address Register */
  23. Ijr = 0x06, /* Initialisation Jumpers */
  24. Gp2 = 0x07, /* General Purpose Data Register */
  25. Lar = 0x08, /* LAN Address Registers */
  26. Id = 0x0E, /* Card ID byte */
  27. Cksum = 0x0F, /* Checksum */
  28. };
  29. enum { /* Msr */
  30. Rst = 0x80, /* software reset */
  31. Menb = 0x40, /* memory enable */
  32. };
  33. enum { /* Icr */
  34. Bit16 = 0x01, /* 16-bit bus */
  35. Other = 0x02, /* other register access */
  36. Ir2 = 0x04, /* IR2 */
  37. Msz = 0x08, /* SRAM size */
  38. Rla = 0x10, /* recall LAN address */
  39. Rx7 = 0x20, /* recall all but I/O and LAN address */
  40. Rio = 0x40, /* recall I/O address from EEROM */
  41. Sto = 0x80, /* non-volatile EEROM store */
  42. };
  43. enum { /* Laar */
  44. ZeroWS16 = 0x20, /* zero wait states for 16-bit ops */
  45. L16en = 0x40, /* enable 16-bit LAN operation */
  46. M16en = 0x80, /* enable 16-bit memory access */
  47. };
  48. enum { /* Ijr */
  49. Ienable = 0x01, /* 8216 interrupt enable */
  50. };
  51. /*
  52. * Mapping from configuration bits to interrupt level.
  53. */
  54. static int irq8003[8] = {
  55. 9, 3, 5, 7, 10, 11, 15, 4,
  56. };
  57. static int irq8216[8] = {
  58. 0, 9, 3, 5, 7, 10, 11, 15,
  59. };
  60. static void
  61. reset8003(Ether* ether, uchar ea[Eaddrlen], uchar ic[8])
  62. {
  63. Dp8390 *ctlr;
  64. ulong port;
  65. ctlr = ether->ctlr;
  66. port = ether->port;
  67. /*
  68. * Check for old, dumb 8003E, which doesn't have an interface
  69. * chip. Only Msr exists out of the 1st eight registers, reads
  70. * of the others just alias the 2nd eight registers, the LAN
  71. * address ROM. Can check Icr, Irr and Laar against the ethernet
  72. * address read above and if they match it's an 8003E (or an
  73. * 8003EBT, 8003S, 8003SH or 8003WT, doesn't matter), in which
  74. * case the default irq gets used.
  75. */
  76. if(memcmp(&ea[1], &ic[1], 5) == 0){
  77. memset(ic, 0, sizeof(ic));
  78. ic[Msr] = (((ulong)ether->mem)>>13) & 0x3F;
  79. }
  80. else{
  81. /*
  82. * As a final sanity check for the 8013EBT, which doesn't have
  83. * the 83C584 interface chip, but has 2 real registers, write Gp2
  84. * and if it reads back the same, it's not an 8013EBT.
  85. */
  86. outb(port+Gp2, 0xAA);
  87. inb(port+Msr); /* wiggle bus */
  88. if(inb(port+Gp2) != 0xAA){
  89. memset(ic, 0, sizeof(ic));
  90. ic[Msr] = (((ulong)ether->mem)>>13) & 0x3F;
  91. }
  92. else
  93. ether->irq = irq8003[((ic[Irr]>>5) & 0x3)|(ic[Icr] & 0x4)];
  94. /*
  95. * Check if 16-bit card.
  96. * If Bit16 is read/write, then it's an 8-bit card.
  97. * If Bit16 is set, it's in a 16-bit slot.
  98. */
  99. outb(port+Icr, ic[Icr]^Bit16);
  100. inb(port+Msr); /* wiggle bus */
  101. if((inb(port+Icr) & Bit16) == (ic[Icr] & Bit16)){
  102. ctlr->width = 2;
  103. ic[Icr] &= ~Bit16;
  104. }
  105. outb(port+Icr, ic[Icr]);
  106. if(ctlr->width == 2 && (inb(port+Icr) & Bit16) == 0)
  107. ctlr->width = 1;
  108. }
  109. ether->mem = (ulong)KADDR((ic[Msr] & 0x3F)<<13);
  110. if(ctlr->width == 2)
  111. ether->mem |= (ic[Laar] & 0x1F)<<19;
  112. else
  113. ether->mem |= 0x80000;
  114. if(ic[Icr] & (1<<3))
  115. ether->size = 32*1024;
  116. if(ctlr->width == 2)
  117. ether->size <<= 1;
  118. /*
  119. * Enable interface RAM, set interface width.
  120. */
  121. outb(port+Msr, ic[Msr]|Menb);
  122. if(ctlr->width == 2)
  123. outb(port+Laar, ic[Laar]|L16en|M16en|ZeroWS16);
  124. }
  125. static void
  126. reset8216(Ether* ether, uchar[8])
  127. {
  128. uchar hcr, irq, x;
  129. ulong addr, port;
  130. Dp8390 *ctlr;
  131. ctlr = ether->ctlr;
  132. port = ether->port;
  133. ctlr->width = 2;
  134. /*
  135. * Switch to the alternate register set and retrieve the memory
  136. * and irq information.
  137. */
  138. hcr = inb(port+Hcr);
  139. outb(port+Hcr, 0x80|hcr);
  140. addr = inb(port+0x0B) & 0xFF;
  141. irq = inb(port+0x0D);
  142. outb(port+Hcr, hcr);
  143. ether->mem = (ulong)KADDR(0xC0000+((((addr>>2) & 0x30)|(addr & 0x0F))<<13));
  144. ether->size = 8192*(1<<((addr>>4) & 0x03));
  145. ether->irq = irq8216[((irq>>4) & 0x04)|((irq>>2) & 0x03)];
  146. /*
  147. * Enable interface RAM, set interface width, and enable interrupts.
  148. */
  149. x = inb(port+Msr) & ~Rst;
  150. outb(port+Msr, Menb|x);
  151. x = inb(port+Laar);
  152. outb(port+Laar, M16en|x);
  153. outb(port+Ijr, Ienable);
  154. }
  155. /*
  156. * Get configuration parameters, enable memory.
  157. * There are opportunities here for buckets of code, try to resist.
  158. */
  159. int
  160. wd8003reset(Ether* ether)
  161. {
  162. int i;
  163. uchar ea[Eaddrlen], ic[8], id, nullea[Eaddrlen], sum;
  164. ulong port;
  165. Dp8390 *ctlr;
  166. /*
  167. * Set up the software configuration.
  168. * Use defaults for port, irq, mem and size if not specified.
  169. * Defaults are set for the dumb 8003E which can't be
  170. * autoconfigured.
  171. */
  172. if(ether->port == 0)
  173. ether->port = 0x280;
  174. if(ether->irq == 0)
  175. ether->irq = 3;
  176. if(ether->mem == 0)
  177. ether->mem = 0xD0000;
  178. if(ether->size == 0)
  179. ether->size = 8*1024;
  180. /*
  181. * Look for the interface. Read the LAN address ROM
  182. * and validate the checksum - the sum of all 8 bytes
  183. * should be 0xFF.
  184. * At the same time, get the (possible) interface chip
  185. * registers, they'll be used later to check for aliasing.
  186. */
  187. port = ether->port;
  188. sum = 0;
  189. for(i = 0; i < sizeof(ea); i++){
  190. ea[i] = inb(port+Lar+i);
  191. sum += ea[i];
  192. ic[i] = inb(port+i);
  193. }
  194. id = inb(port+Id);
  195. sum += id;
  196. sum += inb(port+Cksum);
  197. if(sum != 0xFF)
  198. return -1;
  199. ether->ctlr = malloc(sizeof(Dp8390));
  200. ctlr = ether->ctlr;
  201. ctlr->ram = 1;
  202. if((id & 0xFE) == 0x2A)
  203. reset8216(ether, ic);
  204. else
  205. reset8003(ether, ea, ic);
  206. /*
  207. * Set the DP8390 ring addresses.
  208. */
  209. ctlr->port = port+0x10;
  210. ctlr->tstart = 0;
  211. ctlr->pstart = HOWMANY(sizeof(Etherpkt), Dp8390BufSz);
  212. ctlr->pstop = HOWMANY(ether->size, Dp8390BufSz);
  213. /*
  214. * Finally, init the 8390, set the ethernet address
  215. * and claim the memory used.
  216. */
  217. dp8390reset(ether);
  218. memset(nullea, 0, Eaddrlen);
  219. if(memcmp(nullea, ether->ea, Eaddrlen) == 0){
  220. for(i = 0; i < sizeof(ether->ea); i++)
  221. ether->ea[i] = ea[i];
  222. }
  223. dp8390setea(ether);
  224. if(umbrwmalloc(PADDR(ether->mem), ether->size, 0) == 0)
  225. print("ether8003: warning - 0x%luX unavailable", PADDR(ether->mem));
  226. return 0;
  227. }