etherrhine.c 12 KB

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  1. /*
  2. Via Rhine driver, written for VT6102.
  3. Uses the ethermii to control PHY.
  4. Currently always copies on both, tx and rx.
  5. rx side could be copy-free, and tx-side might be made
  6. (almost) copy-free by using (possibly) two descriptors (if it allows
  7. arbitrary tx lengths, which it should..): first for alignment and
  8. second for rest of the frame. Rx-part should be worth doing.
  9. */
  10. #include "u.h"
  11. #include "lib.h"
  12. #include "mem.h"
  13. #include "dat.h"
  14. #include "fns.h"
  15. #include "io.h"
  16. typedef struct QLock { int r; } QLock;
  17. #define qlock(i) while(0)
  18. #define qunlock(i) while(0)
  19. #define iprint print
  20. #include "etherif.h"
  21. #include "ethermii.h"
  22. enum {
  23. Ntxd = 4,
  24. Nrxd = 4,
  25. Nwait = 50,
  26. BIGSTR = 8192,
  27. };
  28. typedef struct Desc Desc;
  29. typedef struct Ctlr Ctlr;
  30. struct Desc {
  31. ulong stat;
  32. ulong size;
  33. ulong addr;
  34. ulong next;
  35. char *buf;
  36. ulong pad[3];
  37. };
  38. struct Ctlr {
  39. Pcidev *pci;
  40. int attached;
  41. int txused;
  42. int txhead;
  43. int txtail;
  44. int rxtail;
  45. ulong port;
  46. Mii mii;
  47. Desc *txd; /* wants to be aligned on 16-byte boundary */
  48. Desc *rxd;
  49. QLock attachlck;
  50. Lock tlock;
  51. };
  52. #define ior8(c, r) (inb((c)->port+(r)))
  53. #define iow8(c, r, b) (outb((c)->port+(r), (int)(b)))
  54. #define ior16(c, r) (ins((c)->port+(r)))
  55. #define ior32(c, r) (inl((c)->port+(r)))
  56. #define iow16(c, r, w) (outs((c)->port+(r), (ushort)(w)))
  57. #define iow32(c, r, l) (outl((c)->port+(r), (ulong)(l)))
  58. /* names used everywhere else */
  59. #define csr8r ior8
  60. #define csr8w iow8
  61. #define csr16r ior16
  62. #define csr16w iow16
  63. #define csr32r ior32
  64. #define csr32w iow32
  65. enum Regs {
  66. Eaddr = 0x0,
  67. Rcr = 0x6,
  68. Tcr = 0x7,
  69. Cr = 0x8,
  70. Isr = 0xc,
  71. Imr = 0xe,
  72. McastAddr = 0x10,
  73. RxdAddr = 0x18,
  74. TxdAddr = 0x1C,
  75. Bcr0 = 0x6E, /* Bus Control */
  76. Bcr1 = 0x6F,
  77. RhineMiiPhy = 0x6C,
  78. RhineMiiSr = 0x6D,
  79. RhineMiiCr = 0x70,
  80. RhineMiiAddr = 0x71,
  81. RhineMiiData = 0x72,
  82. Eecsr = 0x74,
  83. ConfigB = 0x79,
  84. ConfigD = 0x7B,
  85. MiscCr = 0x80,
  86. HwSticky = 0x83,
  87. MiscIsr = 0x84,
  88. MiscImr = 0x86,
  89. WolCrSet = 0xA0,
  90. WolCfgSet = 0xA1,
  91. WolCgSet = 0xA3,
  92. WolCrClr = 0xA4,
  93. PwrCfgClr = 0xA5,
  94. WolCgClr = 0xA7,
  95. };
  96. enum { /* Rcr */
  97. Sep = 0x01, /* Accept Error Packets */
  98. Ar = 0x02, /* Accept Small Packets */
  99. Am = 0x04, /* Accept Multicast */
  100. Ab = 0x08, /* Accept Broadcast */
  101. RxBcast = Ab,
  102. Prom = 0x10, /* Accept Physical Address Packets */
  103. RxProm = Prom,
  104. RrftMASK = 0xE0, /* Receive FIFO Threshold */
  105. RrftSHIFT = 5,
  106. Rrft64 = 0<<RrftSHIFT,
  107. Rrft32 = 1<<RrftSHIFT,
  108. Rrft128 = 2<<RrftSHIFT,
  109. Rrft256 = 3<<RrftSHIFT,
  110. Rrft512 = 4<<RrftSHIFT,
  111. Rrft768 = 5<<RrftSHIFT,
  112. Rrft1024 = 6<<RrftSHIFT,
  113. RrftSAF = 7<<RrftSHIFT,
  114. };
  115. enum { /* Tcr */
  116. Lb0 = 0x02, /* Loopback Mode */
  117. Lb1 = 0x04,
  118. Ofset = 0x08, /* Back-off Priority Selection */
  119. RtsfMASK = 0xE0, /* Transmit FIFO Threshold */
  120. RtsfSHIFT = 5,
  121. Rtsf128 = 0<<RtsfSHIFT,
  122. Rtsf256 = 1<<RtsfSHIFT,
  123. Rtsf512 = 2<<RtsfSHIFT,
  124. Rtsf1024 = 3<<RtsfSHIFT,
  125. RtsfSAF = 7<<RtsfSHIFT,
  126. };
  127. enum Crbits {
  128. Init = 1<<0,
  129. Start = 1<<1,
  130. Stop = 1<<2,
  131. RxOn = 1<<3,
  132. TxOn = 1<<4,
  133. Tdmd = 1<<5,
  134. Rdmd = 1<<6,
  135. EarlyRx = 1<<8,
  136. Reserved0 = 1<<9,
  137. FullDuplex = 1<<10,
  138. NoAutoPoll = 1<<11,
  139. Reserved1 = 1<<12,
  140. Tdmd1 = 1<<13,
  141. Rdmd1 = 1<<14,
  142. Reset = 1<<15,
  143. };
  144. enum Isrbits {
  145. RxOk = 1<<0,
  146. TxOk = 1<<1,
  147. RxErr = 1<<2,
  148. TxErr = 1<<3,
  149. TxBufUdf = 1<<4,
  150. RxBufLinkErr = 1<<5,
  151. BusErr = 1<<6,
  152. CrcOvf = 1<<7,
  153. EarlyRxInt = 1<<8,
  154. TxFifoUdf = 1<<9,
  155. RxFifoOvf = 1<<10,
  156. TxPktRace = 1<<11,
  157. NoRxbuf = 1<<12,
  158. TxCollision = 1<<13,
  159. PortCh = 1<<14,
  160. GPInt = 1<<15,
  161. };
  162. enum { /* Bcr0 */
  163. DmaMASK = 0x07, /* DMA Length */
  164. DmaSHIFT = 0,
  165. Dma32 = 0<<DmaSHIFT,
  166. Dma64 = 1<<DmaSHIFT,
  167. Dma128 = 2<<DmaSHIFT,
  168. Dma256 = 3<<DmaSHIFT,
  169. Dma512 = 4<<DmaSHIFT,
  170. Dma1024 = 5<<DmaSHIFT,
  171. DmaSAF = 7<<DmaSHIFT,
  172. CrftMASK = 0x38, /* Rx FIFO Threshold */
  173. CrftSHIFT = 3,
  174. Crft64 = 1<<CrftSHIFT,
  175. Crft128 = 2<<CrftSHIFT,
  176. Crft256 = 3<<CrftSHIFT,
  177. Crft512 = 4<<CrftSHIFT,
  178. Crft1024 = 5<<CrftSHIFT,
  179. CrftSAF = 7<<CrftSHIFT,
  180. Extled = 0x40, /* Extra LED Support Control */
  181. Med2 = 0x80, /* Medium Select Control */
  182. };
  183. enum { /* Bcr1 */
  184. PotMASK = 0x07, /* Polling Timer Interval */
  185. PotSHIFT = 0,
  186. CtftMASK = 0x38, /* Tx FIFO Threshold */
  187. CtftSHIFT = 3,
  188. Ctft64 = 1<<CtftSHIFT,
  189. Ctft128 = 2<<CtftSHIFT,
  190. Ctft256 = 3<<CtftSHIFT,
  191. Ctft512 = 4<<CtftSHIFT,
  192. Ctft1024 = 5<<CtftSHIFT,
  193. CtftSAF = 7<<CtftSHIFT,
  194. };
  195. enum Eecsrbits {
  196. EeAutoLoad = 1<<5,
  197. };
  198. enum Descbits {
  199. OwnNic = 1<<31, /* stat */
  200. TxAbort = 1<<8, /* stat */
  201. TxError = 1<<15, /* stat */
  202. RxChainbuf = 1<<10, /* stat */
  203. RxChainStart = 1<<9, /* stat */
  204. RxChainEnd = 1<<8, /* stat */
  205. Chainbuf = 1<<15, /* size rx & tx*/
  206. TxDisableCrc = 1<<16, /* size */
  207. TxChainStart = 1<<21, /* size */
  208. TxChainEnd = 1<<22, /* size */
  209. TxInt = 1<<23, /* size */
  210. };
  211. enum RhineMiiCrbits {
  212. Mdc = 1<<0,
  213. Mdi = 1<<1,
  214. Mdo = 1<<2,
  215. Mdout = 1<<3,
  216. Mdpm = 1<<4,
  217. Wcmd = 1<<5,
  218. Rcmd = 1<<6,
  219. Mauto = 1<<7,
  220. };
  221. static void
  222. attach(Ether *edev)
  223. {
  224. Ctlr *ctlr;
  225. Desc *txd, *rxd, *td, *rd;
  226. Mii *mi;
  227. MiiPhy *phy;
  228. int i, s;
  229. ctlr = edev->ctlr;
  230. qlock(&ctlr->attachlck);
  231. if (ctlr->attached == 0) {
  232. txd = ctlr->txd;
  233. rxd = ctlr->rxd;
  234. for (i = 0; i < Ntxd; ++i) {
  235. td = &txd[i];
  236. td->next = PCIWADDR(&txd[(i+1) % Ntxd]);
  237. td->buf = xspanalloc(sizeof(Etherpkt)+4, 4, 0);
  238. td->addr = PCIWADDR(td->buf);
  239. td->size = 0;
  240. coherence();
  241. td->stat = 0;
  242. }
  243. for (i = 0; i < Nrxd; ++i) {
  244. rd = &rxd[i];
  245. rd->next = PCIWADDR(&rxd[(i+1) % Nrxd]);
  246. rd->buf = xspanalloc(sizeof(Etherpkt)+4, 4, 0);
  247. rd->addr = PCIWADDR(rd->buf);
  248. rd->size = sizeof(Etherpkt)+4;
  249. coherence();
  250. rd->stat = OwnNic;
  251. }
  252. ctlr->txhead = ctlr->txtail = ctlr->rxtail = 0;
  253. mi = &ctlr->mii;
  254. miistatus(mi);
  255. phy = mi->curphy;
  256. s = splhi();
  257. iow32(ctlr, TxdAddr, PCIWADDR(&txd[0]));
  258. iow32(ctlr, RxdAddr, PCIWADDR(&rxd[0]));
  259. iow16(ctlr, Cr, (phy->fd? FullDuplex: 0) | NoAutoPoll | TxOn |
  260. RxOn | Start | Rdmd);
  261. iow16(ctlr, Isr, 0xFFFF);
  262. iow16(ctlr, Imr, 0xFFFF);
  263. iow8(ctlr, MiscIsr, 0xFF);
  264. iow8(ctlr, MiscImr, ~(3<<5));
  265. splx(s);
  266. ctlr->attached = 1;
  267. }
  268. qunlock(&ctlr->attachlck);
  269. }
  270. static void
  271. txstart(Ether *edev)
  272. {
  273. Ctlr *ctlr;
  274. Desc *txd, *td;
  275. int i, txused, n;
  276. RingBuf *tb;
  277. ctlr = edev->ctlr;
  278. txd = ctlr->txd;
  279. i = ctlr->txhead;
  280. n = 0;
  281. for (txused = ctlr->txused; txused < Ntxd; txused++) {
  282. tb = &edev->tb[edev->ti];
  283. if(tb->owner != Interface)
  284. break;
  285. td = &txd[i];
  286. memmove(td->buf, tb->pkt, tb->len);
  287. /* could reduce number of intrs here */
  288. td->size = tb->len | TxChainStart | TxChainEnd | TxInt;
  289. coherence();
  290. td->stat = OwnNic;
  291. i = (i + 1) % Ntxd;
  292. n++;
  293. tb->owner = Host;
  294. edev->ti = NEXT(edev->ti, edev->ntb);
  295. }
  296. if (n)
  297. iow16(ctlr, Cr, ior16(ctlr, Cr) | Tdmd);
  298. ctlr->txhead = i;
  299. ctlr->txused = txused;
  300. }
  301. static void
  302. transmit(Ether *edev)
  303. {
  304. Ctlr *ctlr;
  305. ctlr = edev->ctlr;
  306. ilock(&ctlr->tlock);
  307. txstart(edev);
  308. iunlock(&ctlr->tlock);
  309. }
  310. static void
  311. txcomplete(Ether *edev)
  312. {
  313. Ctlr *ctlr;
  314. Desc *txd, *td;
  315. int i, txused;
  316. ulong stat;
  317. ctlr = edev->ctlr;
  318. txd = ctlr->txd;
  319. i = ctlr->txtail;
  320. for (txused = ctlr->txused; txused > 0; txused--) {
  321. td = &txd[i];
  322. stat = td->stat;
  323. if (stat & OwnNic)
  324. break;
  325. i = (i + 1) % Ntxd;
  326. }
  327. ctlr->txused = txused;
  328. ctlr->txtail = i;
  329. if (txused <= Ntxd/2)
  330. txstart(edev);
  331. }
  332. static void
  333. interrupt(Ureg *, void *arg)
  334. {
  335. Ether *edev;
  336. Ctlr *ctlr;
  337. RingBuf *rb;
  338. ushort isr, misr;
  339. ulong stat;
  340. Desc *rxd, *rd;
  341. int i, n, size;
  342. edev = (Ether*)arg;
  343. ctlr = edev->ctlr;
  344. iow16(ctlr, Imr, 0);
  345. isr = ior16(ctlr, Isr);
  346. iow16(ctlr, Isr, 0xFFFF);
  347. /* don't care about used defined intrs */
  348. misr = ior16(ctlr, MiscIsr) & ~(3<<5);
  349. if (isr & RxOk) {
  350. rxd = ctlr->rxd;
  351. i = ctlr->rxtail;
  352. n = 0;
  353. while ((rxd[i].stat & OwnNic) == 0) {
  354. rd = &rxd[i];
  355. stat = rd->stat;
  356. if (stat & 0xFF)
  357. iprint("rx: %lux\n", stat & 0xFF);
  358. size = ((rd->stat>>16) & (2048-1)) - 4;
  359. rb = &edev->rb[edev->ri];
  360. if(rb->owner == Interface){
  361. rb->owner = Host;
  362. rb->len = size;
  363. memmove(rb->pkt, rd->buf, size);
  364. edev->ri = NEXT(edev->ri, edev->nrb);
  365. }
  366. rd->size = sizeof(Etherpkt)+4;
  367. coherence();
  368. rd->stat = OwnNic;
  369. i = (i + 1) % Nrxd;
  370. n++;
  371. }
  372. if (n)
  373. iow16(ctlr, Cr, ior16(ctlr, Cr) | Rdmd);
  374. ctlr->rxtail = i;
  375. isr &= ~RxOk;
  376. }
  377. if (isr & TxOk) {
  378. txcomplete(edev);
  379. isr &= ~TxOk;
  380. }
  381. if (isr | misr)
  382. iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n",
  383. isr, misr);
  384. iow16(ctlr, Imr, 0xFFFF);
  385. }
  386. static int
  387. miiread(Mii *mii, int phy, int reg)
  388. {
  389. Ctlr *ctlr;
  390. int n;
  391. ctlr = mii->ctlr;
  392. n = Nwait;
  393. while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
  394. microdelay(1);
  395. if (n == Nwait)
  396. iprint("etherrhine: miiread: timeout\n");
  397. iow8(ctlr, RhineMiiCr, 0);
  398. iow8(ctlr, RhineMiiPhy, phy);
  399. iow8(ctlr, RhineMiiAddr, reg);
  400. iow8(ctlr, RhineMiiCr, Rcmd);
  401. n = Nwait;
  402. while (n-- && ior8(ctlr, RhineMiiCr) & Rcmd)
  403. microdelay(1);
  404. if (n == Nwait)
  405. iprint("etherrhine: miiread: timeout\n");
  406. return ior16(ctlr, RhineMiiData);
  407. }
  408. static int
  409. miiwrite(Mii *mii, int phy, int reg, int data)
  410. {
  411. int n;
  412. Ctlr *ctlr;
  413. ctlr = mii->ctlr;
  414. n = Nwait;
  415. while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
  416. microdelay(1);
  417. if (n == Nwait)
  418. iprint("etherrhine: miiwrite: timeout\n");
  419. iow8(ctlr, RhineMiiCr, 0);
  420. iow8(ctlr, RhineMiiPhy, phy);
  421. iow8(ctlr, RhineMiiAddr, reg);
  422. iow16(ctlr, RhineMiiData, data);
  423. iow8(ctlr, RhineMiiCr, Wcmd);
  424. n = Nwait;
  425. while (n-- && ior8(ctlr, RhineMiiCr) & Wcmd)
  426. microdelay(1);
  427. if (n == Nwait)
  428. iprint("etherrhine: miiwrite: timeout\n");
  429. return 0;
  430. }
  431. static void
  432. reset(Ctlr* ctlr)
  433. {
  434. int r, timeo;
  435. /*
  436. * Soft reset the controller.
  437. */
  438. csr16w(ctlr, Cr, Stop);
  439. csr16w(ctlr, Cr, Stop|Reset);
  440. for(timeo = 0; timeo < 10000; timeo++){
  441. if(!(csr16r(ctlr, Cr) & Reset))
  442. break;
  443. microdelay(1);
  444. }
  445. if(timeo >= 1000)
  446. return;
  447. /*
  448. * Load the MAC address into the PAR[01]
  449. * registers.
  450. */
  451. r = csr8r(ctlr, Eecsr);
  452. csr8w(ctlr, Eecsr, EeAutoLoad|r);
  453. for(timeo = 0; timeo < 100; timeo++){
  454. if(!(csr8r(ctlr, Cr) & EeAutoLoad))
  455. break;
  456. microdelay(1);
  457. }
  458. if(timeo >= 100)
  459. return;
  460. /*
  461. * Configure DMA and Rx/Tx thresholds.
  462. * If the Rx/Tx threshold bits in Bcr[01] are 0 then
  463. * the thresholds are determined by Rcr/Tcr.
  464. */
  465. r = csr8r(ctlr, Bcr0) & ~(CrftMASK|DmaMASK);
  466. csr8w(ctlr, Bcr0, r|Crft64|Dma64);
  467. r = csr8r(ctlr, Bcr1) & ~CtftMASK;
  468. csr8w(ctlr, Bcr1, r|Ctft64);
  469. r = csr8r(ctlr, Rcr) & ~(RrftMASK|Prom|Ar|Sep);
  470. csr8w(ctlr, Rcr, r|Ab|Am);
  471. r = csr8r(ctlr, Tcr) & ~(RtsfMASK|Ofset|Lb1|Lb0);
  472. csr8w(ctlr, Tcr, r);
  473. }
  474. static void
  475. detach(Ether* edev)
  476. {
  477. reset(edev->ctlr);
  478. }
  479. static void
  480. init(Ether *edev)
  481. {
  482. Ctlr *ctlr;
  483. int i;
  484. ctlr = edev->ctlr;
  485. ilock(&ctlr->tlock);
  486. pcisetbme(ctlr->pci);
  487. reset(ctlr);
  488. iow8(ctlr, Eecsr, ior8(ctlr, Eecsr) | EeAutoLoad);
  489. for (i = 0; i < Nwait; ++i) {
  490. if ((ior8(ctlr, Eecsr) & EeAutoLoad) == 0)
  491. break;
  492. delay(5);
  493. }
  494. if (i >= Nwait)
  495. iprint("etherrhine: eeprom autoload timeout\n");
  496. for (i = 0; i < Eaddrlen; ++i)
  497. edev->ea[i] = ior8(ctlr, Eaddr + i);
  498. ctlr->mii.mir = miiread;
  499. ctlr->mii.miw = miiwrite;
  500. ctlr->mii.ctlr = ctlr;
  501. if(mii(&ctlr->mii, ~0) == 0 || ctlr->mii.curphy == nil){
  502. iunlock(&ctlr->tlock);
  503. iprint("etherrhine: init mii failure\n");
  504. return;
  505. }
  506. for (i = 0; i < NMiiPhy; ++i)
  507. if (ctlr->mii.phy[i])
  508. if (ctlr->mii.phy[i]->oui != 0xFFFFF)
  509. ctlr->mii.curphy = ctlr->mii.phy[i];
  510. miistatus(&ctlr->mii);
  511. iow16(ctlr, Imr, 0);
  512. iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
  513. iunlock(&ctlr->tlock);
  514. }
  515. static Pcidev *
  516. rhinematch(ulong)
  517. {
  518. static int nrhines = 0;
  519. int nfound = 0;
  520. Pcidev *p = nil;
  521. while(p = pcimatch(p, 0x1106, 0)){
  522. if(p->ccrb != Pcibcnet || p->ccru != Pciscether)
  523. continue;
  524. switch((p->did<<16)|p->vid){
  525. default:
  526. continue;
  527. case (0x3053<<16)|0x1106: /* Rhine III vt6105m (Soekris) */
  528. case (0x3065<<16)|0x1106: /* Rhine II */
  529. case (0x3106<<16)|0x1106: /* Rhine III */
  530. if (++nfound > nrhines) {
  531. nrhines++;
  532. return p;
  533. }
  534. break;
  535. }
  536. }
  537. return p;
  538. }
  539. int
  540. rhinepnp(Ether *edev)
  541. {
  542. Pcidev *p;
  543. Ctlr *ctlr;
  544. ulong port;
  545. if (edev->attach)
  546. return 0;
  547. p = rhinematch(edev->port);
  548. if (p == nil)
  549. return -1;
  550. port = p->mem[0].bar & ~1;
  551. if ((ctlr = malloc(sizeof(Ctlr))) == nil) {
  552. print("etherrhine: couldn't allocate memory for ctlr\n");
  553. return -1;
  554. }
  555. memset(ctlr, 0, sizeof(Ctlr));
  556. ctlr->txd = xspanalloc(sizeof(Desc) * Ntxd, 16, 0);
  557. ctlr->rxd = xspanalloc(sizeof(Desc) * Nrxd, 16, 0);
  558. ctlr->pci = p;
  559. ctlr->port = port;
  560. edev->ctlr = ctlr;
  561. edev->port = ctlr->port;
  562. edev->irq = p->intl;
  563. edev->tbdf = p->tbdf;
  564. init(edev);
  565. edev->attach = attach;
  566. edev->transmit = transmit;
  567. edev->interrupt = interrupt;
  568. edev->detach = detach;
  569. return 0;
  570. }
  571. int
  572. vt6102pnp(Ether *edev)
  573. {
  574. return rhinepnp(edev);
  575. }