archkw.c 5.1 KB

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  1. /*
  2. * stuff specific to marvell's kirkwood architecture
  3. * as seen in the sheevaplug
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "../port/error.h"
  11. #include "io.h"
  12. #include "../port/netif.h"
  13. #include "etherif.h"
  14. // #include "../port/flashif.h"
  15. typedef struct GpioReg GpioReg;
  16. struct GpioReg {
  17. ulong dataout;
  18. ulong dataoutena;
  19. ulong blinkena;
  20. ulong datainpol;
  21. ulong datain;
  22. ulong intrcause;
  23. ulong intrmask;
  24. ulong intrlevelmask;
  25. };
  26. typedef struct L2uncache L2uncache;
  27. typedef struct L2win L2win;
  28. struct L2uncache {
  29. struct L2win {
  30. ulong base;
  31. ulong size;
  32. } win[4];
  33. };
  34. enum {
  35. /* L2win->base bits */
  36. L2enable = 1<<0,
  37. };
  38. typedef struct Addrmap Addrmap;
  39. typedef struct Addrwin Addrwin;
  40. struct Addrmap {
  41. struct Addrwin {
  42. ulong ctl;
  43. ulong base;
  44. ulong remaplo;
  45. ulong remaphi;
  46. } win[8];
  47. ulong dirba; /* device internal reg's base addr.: Regbase */
  48. };
  49. enum {
  50. /* Addrwin->ctl bits */
  51. Winenable = 1<<0,
  52. };
  53. /*
  54. * u-boot leaves us with this address map:
  55. *
  56. * 0 targ 4 attr 0xe8 size 256MB addr 0x9:: remap addr 0x9:: pci mem
  57. * 1 targ 1 attr 0x2f size 8MB addr 0xf9:: remap addr 0xf9:: nand flash
  58. * 2 targ 4 attr 0xe0 size 16MB addr 0xf:: remap addr 0xc:: pci i/o
  59. * 3 targ 1 attr 0x1e size 16MB addr 0xf8:: remap addr 0x0 spi flash
  60. * 4 targ 1 attr 0x1d size 16MB addr 0xff:: boot rom
  61. * 5 targ 1 attr 0x1e size 128MB addr 0xe8:: disabled spi flash
  62. * 6 targ 1 attr 0x1d size 128MB addr 0xf:: disabled boot rom
  63. * 7 targ 3 attr 0x1 size 64K addr 0xfb:: crypto
  64. */
  65. #define WINTARG(ctl) (((ctl) >> 4) & 017)
  66. #define WINATTR(ctl) (((ctl) >> 8) & 0377)
  67. #define WIN64KSIZE(ctl) (((ctl) >> 16) + 1)
  68. enum {
  69. Targflash = 1,
  70. Attrspi = 0x1e,
  71. };
  72. static void
  73. addrmap(void)
  74. {
  75. int i, sawspi;
  76. ulong ctl, targ, attr, size64k;
  77. Addrmap *map;
  78. Addrwin *win;
  79. sawspi = 0;
  80. map = (Addrmap *)AddrWin;
  81. for (i = 0; i < nelem(map->win); i++) {
  82. win = &map->win[i];
  83. ctl = win->ctl;
  84. targ = WINTARG(ctl);
  85. attr = WINATTR(ctl);
  86. size64k = WIN64KSIZE(ctl);
  87. if (targ == Targflash && attr == Attrspi &&
  88. size64k == 128*MB/(64*1024)) {
  89. sawspi = 1;
  90. if (!(ctl & Winenable)) {
  91. win->ctl |= Winenable;
  92. coherence();
  93. iprint("address map: enabled window %d for spi:\n"
  94. "\ttarg %ld attr %#lux size %,ld addr %#lux",
  95. i, targ, attr, size64k * 64*1024,
  96. win->base);
  97. if (i < 4)
  98. iprint(" remap addr %#llux",
  99. (uvlong)win->remaphi<<32 |
  100. win->remaplo);
  101. iprint("\n");
  102. }
  103. }
  104. }
  105. if (!sawspi)
  106. panic("address map: no existing window for spi");
  107. // iprint("dirba %#lux\n", map->dirba);
  108. }
  109. void
  110. l2cacheon(void)
  111. {
  112. L2uncache *l2p;
  113. l1cachesoff();
  114. cacheuwbinv();
  115. /* disable caching of i/o registers */
  116. l2p = (L2uncache *)Addrl2cache;
  117. memset(l2p, 0, sizeof *l2p);
  118. /* l2: don't cache upper half of address space */
  119. l2p->win[0].base = 0x80000000 | L2enable; /* 64K multiple */
  120. l2p->win[0].size = (32768-1) << 16; /* 64K multiples */
  121. coherence();
  122. cacheuwbinv();
  123. /* writeback requires extra care */
  124. CPUCSREG->l2cfg |= L2on | L2ecc | L2writethru;
  125. coherence();
  126. cachedinv();
  127. l2cachecfgon();
  128. l1cacheson();
  129. print("l2 cache enabled write-through\n");
  130. }
  131. /* called late in main */
  132. void
  133. archconfinit(void)
  134. {
  135. m->cpuhz = 1200*1000*1000;
  136. m->delayloop = m->cpuhz/6000; /* only an initial estimate */
  137. addrmap();
  138. }
  139. void
  140. archkwlink(void)
  141. {
  142. }
  143. int
  144. archether(unsigned ctlno, Ether *ether)
  145. {
  146. if(ctlno >= 2)
  147. return -1;
  148. ether->type = "kirkwood";
  149. ether->port = ctlno;
  150. // ether->mbps = 1000;
  151. return 1;
  152. }
  153. /* LED/USB gpios */
  154. enum {
  155. /*
  156. * the bit assignments are MPP pin numbers from the last page of the
  157. * sheevaplug 6.0.1 schematic.
  158. */
  159. KWOEValHigh = 1<<(49-32), /* pin 49: LED pin */
  160. KWOEValLow = 1<<29, /* pin 29: USB_PWEN, pin 28: usb_pwerr */
  161. KWOELow = ~0,
  162. KWOEHigh = ~0,
  163. };
  164. /* called early in main */
  165. void
  166. archreset(void)
  167. {
  168. ulong clocks;
  169. CpucsReg *cpu;
  170. /* watchdog disabled */
  171. TIMERREG->ctl = 0;
  172. /* configure gpios */
  173. ((GpioReg*)AddrGpio0)->dataout = KWOEValLow;
  174. ((GpioReg*)AddrGpio0)->dataoutena = KWOELow;
  175. ((GpioReg*)AddrGpio1)->dataout = KWOEValHigh;
  176. ((GpioReg*)AddrGpio1)->dataoutena = KWOEHigh;
  177. coherence();
  178. cpu = CPUCSREG;
  179. cpu->mempm = 0; /* turn everything on */
  180. coherence();
  181. clocks = (1<<10) - 1;
  182. clocks |= ((1<<21) - 1) & ~((1<<14) - 1);
  183. clocks &= ~(1<<18 | 1<<1); /* reserved bits */
  184. cpu->clockgate |= clocks; /* enable all the clocks */
  185. cpu->l2cfg &= ~L2on;
  186. coherence();
  187. }
  188. void
  189. archreboot(void)
  190. {
  191. iprint("reset!\n");
  192. delay(100);
  193. CPUCSREG->rstout = RstoutSoft;
  194. CPUCSREG->softreset = ResetSystem;
  195. CPUCSREG->cpucsr = Reset;
  196. coherence();
  197. delay(500);
  198. splhi();
  199. iprint("waiting...");
  200. for(;;)
  201. idlehands();
  202. }
  203. long
  204. lcycles(void)
  205. {
  206. return 0;
  207. }
  208. void
  209. archconsole(void)
  210. {
  211. // uartconsole(0, "b115200");
  212. //serialputs("uart0 console @ 115200\n", strlen("uart0 console @ 115200\n"));
  213. }
  214. #ifdef USE_FLASH
  215. void
  216. archflashwp(Flash*, int)
  217. {
  218. }
  219. /*
  220. * for ../port/devflash.c:/^flashreset
  221. * retrieve flash type, virtual base and length and return 0;
  222. * return -1 on error (no flash)
  223. */
  224. int
  225. archflashreset(int bank, Flash *f)
  226. {
  227. if(bank != 0)
  228. return -1;
  229. f->type = "nand";
  230. f->addr = (void*)PHYSNAND;
  231. f->size = 0; /* done by probe */
  232. f->width = 1;
  233. f->interleave = 0;
  234. return 0;
  235. }
  236. #endif