io.h 9.2 KB

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  1. enum {
  2. BusCBUS = 0, /* Corollary CBUS */
  3. BusCBUSII, /* Corollary CBUS II */
  4. BusEISA, /* Extended ISA */
  5. BusFUTURE, /* IEEE Futurebus */
  6. BusINTERN, /* Internal bus */
  7. BusISA, /* Industry Standard Architecture */
  8. BusMBI, /* Multibus I */
  9. BusMBII, /* Multibus II */
  10. BusMCA, /* Micro Channel Architecture */
  11. BusMPI, /* MPI */
  12. BusMPSA, /* MPSA */
  13. BusNUBUS, /* Apple Macintosh NuBus */
  14. BusPCI, /* Peripheral Component Interconnect */
  15. BusPCMCIA, /* PC Memory Card International Association */
  16. BusTC, /* DEC TurboChannel */
  17. BusVL, /* VESA Local bus */
  18. BusVME, /* VMEbus */
  19. BusXPRESS, /* Express System Bus */
  20. BUSUNKNOWN = -1
  21. };
  22. #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  23. #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
  24. #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
  25. #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
  26. #define BUSTYPE(tbdf) ((tbdf)>>24)
  27. #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
  28. /*
  29. * PCI support code.
  30. */
  31. enum { /* type 0 & type 1 pre-defined header */
  32. PciVID = 0x00, /* vendor ID */
  33. PciDID = 0x02, /* device ID */
  34. PciPCR = 0x04, /* command */
  35. PciPSR = 0x06, /* status */
  36. PciRID = 0x08, /* revision ID */
  37. PciCCRp = 0x09, /* programming interface class code */
  38. PciCCRu = 0x0A, /* sub-class code */
  39. PciCCRb = 0x0B, /* base class code */
  40. PciCLS = 0x0C, /* cache line size */
  41. PciLTR = 0x0D, /* latency timer */
  42. PciHDT = 0x0E, /* header type */
  43. PciBST = 0x0F, /* BIST */
  44. };
  45. /* ccrb (base class code) values; controller types */
  46. enum {
  47. Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
  48. Pcibcstore = 1, /* mass storage */
  49. Pcibcnet = 2, /* network */
  50. Pcibcdisp = 3, /* display */
  51. Pcibcmmedia = 4, /* multimedia */
  52. Pcibcmem = 5, /* memory */
  53. Pcibcbridge = 6, /* bridge */
  54. Pcibccomm = 7, /* simple comms (e.g., serial) */
  55. Pcibcbasesys = 8, /* base system */
  56. Pcibcinput = 9, /* input */
  57. Pcibcdock = 0xa, /* docking stations */
  58. Pcibcproc = 0xb, /* processors */
  59. Pcibcserial = 0xc, /* serial bus (e.g., USB) */
  60. Pcibcwireless = 0xd, /* wireless */
  61. Pcibcintell = 0xe, /* intelligent i/o */
  62. Pcibcsatcom = 0xf, /* satellite comms */
  63. Pcibccrypto = 0x10, /* encryption/decryption */
  64. Pcibcdacq = 0x11, /* data acquisition & signal proc. */
  65. };
  66. /* ccru (sub-class code) values; common cases only */
  67. enum {
  68. /* mass storage */
  69. Pciscscsi = 0, /* SCSI */
  70. Pciscide = 1, /* IDE (ATA) */
  71. /* network */
  72. Pciscether = 0, /* Ethernet */
  73. /* display */
  74. Pciscvga = 0, /* VGA */
  75. Pciscxga = 1, /* XGA */
  76. Pcisc3d = 2, /* 3D */
  77. /* bridges */
  78. Pcischostpci = 0, /* host/pci */
  79. Pciscpcicpci = 1, /* pci/pci */
  80. /* simple comms */
  81. Pciscserial = 0, /* 16450, etc. */
  82. Pciscmultiser = 1, /* multiport serial */
  83. /* serial bus */
  84. Pciscusb = 3, /* USB */
  85. };
  86. enum { /* type 0 pre-defined header */
  87. PciCIS = 0x28, /* cardbus CIS pointer */
  88. PciSVID = 0x2C, /* subsystem vendor ID */
  89. PciSID = 0x2E, /* cardbus CIS pointer */
  90. PciEBAR0 = 0x30, /* expansion ROM base address */
  91. PciMGNT = 0x3E, /* burst period length */
  92. PciMLT = 0x3F, /* maximum latency between bursts */
  93. };
  94. enum { /* type 1 pre-defined header */
  95. PciPBN = 0x18, /* primary bus number */
  96. PciSBN = 0x19, /* secondary bus number */
  97. PciUBN = 0x1A, /* subordinate bus number */
  98. PciSLTR = 0x1B, /* secondary latency timer */
  99. PciIBR = 0x1C, /* I/O base */
  100. PciILR = 0x1D, /* I/O limit */
  101. PciSPSR = 0x1E, /* secondary status */
  102. PciMBR = 0x20, /* memory base */
  103. PciMLR = 0x22, /* memory limit */
  104. PciPMBR = 0x24, /* prefetchable memory base */
  105. PciPMLR = 0x26, /* prefetchable memory limit */
  106. PciPUBR = 0x28, /* prefetchable base upper 32 bits */
  107. PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
  108. PciIUBR = 0x30, /* I/O base upper 16 bits */
  109. PciIULR = 0x32, /* I/O limit upper 16 bits */
  110. PciEBAR1 = 0x28, /* expansion ROM base address */
  111. PciBCR = 0x3E, /* bridge control register */
  112. };
  113. enum { /* type 2 pre-defined header */
  114. PciCBExCA = 0x10,
  115. PciCBSPSR = 0x16,
  116. PciCBPBN = 0x18, /* primary bus number */
  117. PciCBSBN = 0x19, /* secondary bus number */
  118. PciCBUBN = 0x1A, /* subordinate bus number */
  119. PciCBSLTR = 0x1B, /* secondary latency timer */
  120. PciCBMBR0 = 0x1C,
  121. PciCBMLR0 = 0x20,
  122. PciCBMBR1 = 0x24,
  123. PciCBMLR1 = 0x28,
  124. PciCBIBR0 = 0x2C, /* I/O base */
  125. PciCBILR0 = 0x30, /* I/O limit */
  126. PciCBIBR1 = 0x34, /* I/O base */
  127. PciCBILR1 = 0x38, /* I/O limit */
  128. PciCBSVID = 0x40, /* subsystem vendor ID */
  129. PciCBSID = 0x42, /* subsystem ID */
  130. PciCBLMBAR = 0x44, /* legacy mode base address */
  131. };
  132. typedef struct Pcisiz Pcisiz;
  133. struct Pcisiz
  134. {
  135. Pcidev* dev;
  136. int siz;
  137. int bar;
  138. };
  139. typedef struct Pcidev Pcidev;
  140. struct Pcidev
  141. {
  142. int tbdf; /* type+bus+device+function */
  143. ushort vid; /* vendor ID */
  144. ushort did; /* device ID */
  145. ushort pcr;
  146. uchar rid;
  147. uchar ccrp;
  148. uchar ccru;
  149. uchar ccrb;
  150. uchar cls;
  151. uchar ltr;
  152. struct {
  153. ulong bar; /* base address */
  154. int size;
  155. } mem[6];
  156. struct {
  157. ulong bar;
  158. int size;
  159. } rom;
  160. uchar intl; /* interrupt line */
  161. Pcidev* list;
  162. Pcidev* link; /* next device on this bno */
  163. Pcidev* bridge; /* down a bus */
  164. struct {
  165. ulong bar;
  166. int size;
  167. } ioa, mema;
  168. int pmrb; /* power management register block */
  169. };
  170. #define PCIWINDOW 0
  171. #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
  172. #define ISAWINDOW 0
  173. #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
  174. /*
  175. * Kirkwood stuff
  176. */
  177. /* weird padding macro */
  178. #define PAD(next, last) (((next) - sizeof(ulong) - (last)) / sizeof(ulong))
  179. enum {
  180. Regbase = 0xf1000000, /* PHYSIO in mem.h */
  181. AddrSDramc = Regbase+0x01400,
  182. AddrSDramd = Regbase+0x01500,
  183. AddrMpp = Regbase+0x10000,
  184. AddrDevid = Regbase+0x10034,
  185. AddrClockctl = Regbase+0x1004c,
  186. AddrEfuse = Regbase+0x1008c,
  187. AddrIocfg0 = Regbase+0x100e0,
  188. AddrGpio0 = Regbase+0x10100,
  189. AddrGpio1 = Regbase+0x10140,
  190. AddrRtc = Regbase+0x10300,
  191. AddrNandf = Regbase+0x10418,
  192. AddrSpi = Regbase+0x10600,
  193. AddrUart0 = Regbase+0x12000,
  194. AddrUart1 = Regbase+0x12100,
  195. AddrWin = Regbase+0x20000,
  196. AddrCpucsr = Regbase+0x20100,
  197. AddrIntr = Regbase+0x20200,
  198. AddrTimer = Regbase+0x20300,
  199. Addrl2cache = Regbase+0x20a00, /* uncacheable addresses for L2 */
  200. Addrpci = Regbase+0x40000,
  201. Addrpcibase = Regbase+0x41800,
  202. Addrusb = Regbase+0x50000,
  203. AddrSdio = Regbase+0x90000,
  204. };
  205. enum {
  206. /* registers */
  207. PciBAR0 = Addrpcibase + 4, /* base address */
  208. PciBAR1 = Addrpcibase + 8,
  209. PciCP = Addrpci + 0x64, /* capabilities pointer */
  210. PciINTL = Addrpci + 0x3c, /* interrupt line */
  211. PciINTP = PciINTL + 1, /* interrupt pin */
  212. };
  213. /*
  214. * interrupt stuff
  215. */
  216. enum {
  217. Irqlo, Irqhi, Irqbridge,
  218. };
  219. enum {
  220. /* main interrupt cause low register bit #s (LE) */
  221. IRQ0hisum, /* summary of main intr high cause reg */
  222. IRQ0bridge,
  223. IRQ0h2cdoorbell,
  224. IRQ0c2hdoorbell,
  225. _IRQ0reserved0,
  226. IRQ0xor0chan0,
  227. IRQ0xor0chan1,
  228. IRQ0xor1chan0,
  229. IRQ0xor1chan1,
  230. IRQ0pex0int, /* pex = pci-express */
  231. _IRQ0reserved1,
  232. IRQ0gbe0sum,
  233. IRQ0gbe0rx,
  234. IRQ0gbe0tx,
  235. IRQ0gbe0misc,
  236. IRQ0gbe1sum,
  237. IRQ0gbe1rx,
  238. IRQ0gbe1tx,
  239. IRQ0gbe1misc,
  240. IRQ0usb0,
  241. _IRQ0reserved2,
  242. IRQ0sata,
  243. IRQ0crypto,
  244. IRQ0spi,
  245. IRQ0audio,
  246. _IRQ0reserved3,
  247. IRQ0ts0,
  248. _IRQ0reserved4,
  249. IRQ0sdio,
  250. IRQ0twsi,
  251. IRQ0avb,
  252. IRQ0tdm,
  253. /* main interrupt cause high register bit #s (LE) */
  254. _IRQ1reserved0 = 0,
  255. IRQ1uart0,
  256. IRQ1uart1,
  257. IRQ1gpiolo0,
  258. IRQ1gpiolo1,
  259. IRQ1gpiolo2,
  260. IRQ1gpiolo3,
  261. IRQ1gpiohi0,
  262. IRQ1gpiohi1,
  263. IRQ1gpiohi2,
  264. IRQ1gpiohi3,
  265. IRQ1xor0err,
  266. IRQ1xor1err,
  267. IRQ1pex0err,
  268. _IRQ1reserved1,
  269. IRQ1gbe0err,
  270. IRQ1gbe1err,
  271. IRQ1usberr,
  272. IRQ1cryptoerr,
  273. IRQ1audioerr,
  274. _IRQ1reserved2,
  275. _IRQ1reserved3,
  276. IRQ1rtc,
  277. /* bridged-interrupt causes */
  278. IRQcpuself = 0,
  279. IRQcputimer0,
  280. IRQcputimer1,
  281. IRQcputimerwd,
  282. };
  283. /*
  284. * interrupt controller
  285. */
  286. #define INTRREG ((IntrReg*)AddrIntr)
  287. typedef struct IntrReg IntrReg;
  288. struct IntrReg
  289. {
  290. struct {
  291. ulong irq; /* main intr cause reg (ro) */
  292. ulong irqmask;
  293. ulong fiqmask;
  294. ulong epmask;
  295. } lo, hi;
  296. };
  297. /*
  298. * CPU control & status (archkw.c and trap.c)
  299. */
  300. #define CPUCSREG ((CpucsReg*)AddrCpucsr)
  301. typedef struct CpucsReg CpucsReg;
  302. struct CpucsReg
  303. {
  304. ulong cpucfg;
  305. ulong cpucsr;
  306. ulong rstout;
  307. ulong softreset;
  308. ulong irq; /* mbus(-l) bridge interrupt cause */
  309. ulong irqmask; /* ⋯ mask */
  310. ulong mempm; /* memory power mgmt. control */
  311. ulong clockgate; /* clock enable bits */
  312. ulong biu;
  313. ulong pad0;
  314. ulong l2cfg; /* turn l2 cache on or off, set coherency */
  315. ulong pad1[2];
  316. ulong l2tm0;
  317. ulong l2tm1;
  318. ulong pad2[2];
  319. ulong l2pm;
  320. ulong ram0;
  321. ulong ram1;
  322. ulong ram2;
  323. ulong ram3;
  324. };
  325. enum {
  326. /* cpucfg bits */
  327. Cfgvecinithi = 1<<1, /* boot at 0xffff0000, not 0; default 1 */
  328. Cfgbigendreset = 3<<1, /* init. as big-endian at reset; default 0 */
  329. /* cpucsr bits */
  330. Reset = 1<<1,
  331. /* rstout bits */
  332. RstoutPex = 1<<0,
  333. RstoutWatchdog = 1<<1,
  334. RstoutSoft = 1<<2,
  335. /* softreset bits */
  336. ResetSystem = 1<<0,
  337. /* l2cfg bits */
  338. L2ecc = 1<<2,
  339. L2on = 1<<3,
  340. L2writethru = 1<<4, /* else write-back */
  341. };
  342. /*
  343. * clocks (clock.c and archkw.c)
  344. */
  345. enum {
  346. /* timer ctl bits */
  347. Tmr0enable = 1<<0,
  348. Tmr0periodic = 1<<1,
  349. Tmr1enable = 1<<2,
  350. Tmr1periodic = 1<<3,
  351. TmrWDenable = 1<<4,
  352. TmrWDperiodic = 1<<5,
  353. };
  354. #define TIMERREG ((TimerReg*)AddrTimer)
  355. typedef struct TimerReg TimerReg;
  356. struct TimerReg
  357. {
  358. ulong ctl;
  359. ulong pad[3];
  360. ulong reload0;
  361. ulong timer0;
  362. ulong reload1;
  363. ulong timer1;
  364. ulong reloadwd;
  365. ulong timerwd;
  366. };