pci.c 14 KB

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  1. /*
  2. * This file is part of the UCB release of Plan 9. It is subject to the license
  3. * terms in the LICENSE file found in the top-level directory of this
  4. * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
  5. * part of the UCB release of Plan 9, including this file, may be copied,
  6. * modified, propagated, or distributed except according to the terms contained
  7. * in the LICENSE file.
  8. */
  9. /*
  10. * PCI support code.
  11. * Needs a massive rewrite.
  12. */
  13. #include "u.h"
  14. #include "../port/lib.h"
  15. #include "mem.h"
  16. #include "dat.h"
  17. #include "fns.h"
  18. #include "io.h"
  19. void virtiosetup();
  20. int
  21. pcicapoff(Pcidev *p);
  22. enum
  23. {
  24. PciADDR = 0xCF8, /* CONFIG_ADDRESS */
  25. PciDATA = 0xCFC, /* CONFIG_DATA */
  26. Maxfn = 7,
  27. Maxdev = 31,
  28. Maxbus = 255,
  29. /* command register */
  30. IOen = (1<<0),
  31. MEMen = (1<<1),
  32. MASen = (1<<2),
  33. MemWrInv = (1<<4),
  34. PErrEn = (1<<6),
  35. SErrEn = (1<<8),
  36. Write,
  37. Read,
  38. };
  39. static Lock pcicfglock;
  40. static Lock pcicfginitlock;
  41. static int pcicfgmode = -1;
  42. static Pcidev* pciroot;
  43. static Pcidev* pcilist;
  44. static Pcidev* pcitail;
  45. static char* bustypes[] = {
  46. "CBUSI",
  47. "CBUSII",
  48. "EISA",
  49. "FUTURE",
  50. "INTERN",
  51. "ISA",
  52. "MBI",
  53. "MBII",
  54. "MCA",
  55. "MPI",
  56. "MPSA",
  57. "NUBUS",
  58. "PCI",
  59. "PCMCIA",
  60. "TC",
  61. "VL",
  62. "VME",
  63. "XPRESS",
  64. };
  65. static int
  66. pcicfgrw(int, int, int, int, int);
  67. static int
  68. tbdffmt(Fmt* fmt)
  69. {
  70. char *p;
  71. int l, r;
  72. uint type, tbdf;
  73. if((p = malloc(READSTR)) == nil)
  74. return fmtstrcpy(fmt, "(tbdfconv)");
  75. switch(fmt->r){
  76. case 'T':
  77. tbdf = va_arg(fmt->args, uint);
  78. type = BUSTYPE(tbdf);
  79. if(type < nelem(bustypes))
  80. l = snprint(p, READSTR, bustypes[type]);
  81. else
  82. l = snprint(p, READSTR, "%d", type);
  83. snprint(p+l, READSTR-l, ".%d.%d.%d",
  84. BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
  85. break;
  86. default:
  87. snprint(p, READSTR, "(tbdfconv)");
  88. break;
  89. }
  90. r = fmtstrcpy(fmt, p);
  91. free(p);
  92. return r;
  93. }
  94. static uint32_t
  95. pcibarsize(Pcidev *p, int rno)
  96. {
  97. uint32_t v, size;
  98. v = pcicfgr32(p, rno);
  99. pcicfgw32(p, rno, 0xFFFFFFF0);
  100. size = pcicfgr32(p, rno);
  101. if(v & 1)
  102. size |= 0xFFFF0000;
  103. pcicfgw32(p, rno, v);
  104. return -(size & ~0x0F);
  105. }
  106. static int
  107. pcilscan(int bno, char *path, Pcidev** list)
  108. {
  109. Pcidev *p, *head, *tail;
  110. int dno, fno, i, hdt, l, maxfno, maxubn, sbn, tbdf, ubn, capoff;
  111. maxubn = bno;
  112. head = nil;
  113. tail = nil;
  114. for(dno = 0; dno <= Maxdev; dno++){
  115. maxfno = 0;
  116. for(fno = 0; fno <= maxfno; fno++){
  117. /*
  118. * For this possible device, form the
  119. * bus+device+function triplet needed to address it
  120. * and try to read the vendor and device ID.
  121. * If successful, allocate a device struct and
  122. * start to fill it in with some useful information
  123. * from the device's configuration space.
  124. */
  125. tbdf = MKBUS(BusPCI, bno, dno, fno);
  126. l = pcicfgrw(tbdf, PciVID, 0, Read, 4);
  127. if(l == 0xFFFFFFFF || l == 0)
  128. continue;
  129. p = malloc(sizeof(*p));
  130. p->caplist = nil;
  131. p->capidx = nil;
  132. p->capcnt = 0;
  133. p->tbdf = tbdf;
  134. p->vid = l;
  135. p->did = l>>16;
  136. p->path = path;
  137. if(pcilist != nil)
  138. pcitail->list = p;
  139. else
  140. pcilist = p;
  141. pcitail = p;
  142. p->pcr = pcicfgr16(p, PciPCR);
  143. p->rid = pcicfgr8(p, PciRID);
  144. p->ccrp = pcicfgr8(p, PciCCRp);
  145. p->ccru = pcicfgr8(p, PciCCRu);
  146. p->ccrb = pcicfgr8(p, PciCCRb);
  147. p->cls = pcicfgr8(p, PciCLS);
  148. p->ltr = pcicfgr8(p, PciLTR);
  149. p->intl = pcicfgr8(p, PciINTL);
  150. p->intp = pcicfgr8(p, PciINTP);
  151. /*
  152. * If the device is a multi-function device adjust the
  153. * loop count so all possible functions are checked.
  154. */
  155. hdt = pcicfgr8(p, PciHDT);
  156. if(hdt & 0x80)
  157. maxfno = Maxfn;
  158. /*
  159. * If appropriate, read the base address registers
  160. * and work out the sizes.
  161. */
  162. switch(p->ccrb) {
  163. default:
  164. if((hdt & 0x7F) != 0)
  165. break;
  166. for(i = 0; i < nelem(p->mem); i++) {
  167. p->mem[i].bar = pcicfgr32(p, PciBAR0+4*i);
  168. p->mem[i].size = pcibarsize(p, PciBAR0+4*i);
  169. }
  170. break;
  171. /*
  172. * Some virtio-pci devices have ccrb == 0x00, their BARs and
  173. * sizes also should be picked here.
  174. */
  175. case 0x05: /* memory controller */
  176. case 0x06: /* bridge device */
  177. break;
  178. }
  179. /*
  180. * Try to gather PCI capabilities. If the offset of capabilities
  181. * in the config area cannot be found, skip this step. For simplicity,
  182. * capabilities will be linked in a LIFO so we don't deal with list
  183. * heads and tails.
  184. */
  185. capoff = pcicapoff(p);
  186. int off = capoff;
  187. while(capoff != -1) {
  188. off = pcicfgr8(p, off);
  189. if((off < 0x40) || (off & 3))
  190. break;
  191. off &= ~3;
  192. Pcicap *c = malloc(sizeof(*c));
  193. c->dev = p;
  194. c->link = p->caplist;
  195. p->caplist = c;
  196. p->capcnt++;
  197. c->vndr = pcicfgr8(p, off + PciCapVndr);
  198. c->caplen = pcicfgr8(p, off + PciCapLen);
  199. c->type = pcicfgr8(p, off + PciCapType);
  200. c->bar = pcicfgr8(p, off + PciCapBar);
  201. c->offset = pcicfgr32(p, off + PciCapOff);
  202. c->length = pcicfgr32(p, off + PciCapLength);
  203. off++;
  204. }
  205. if(p->capcnt > 0) {
  206. p->capidx = malloc(p->capcnt * sizeof(Pcicap *));
  207. Pcicap *pcp = p->caplist;
  208. for(int pix = 0; ; pix++) {
  209. p->capidx[pix] = pcp;
  210. pcp = pcp->link;
  211. if(pcp == nil)
  212. break;
  213. }
  214. }
  215. if(head != nil)
  216. tail->link = p;
  217. else
  218. head = p;
  219. tail = p;
  220. }
  221. }
  222. *list = head;
  223. for(p = head; p != nil; p = p->link) {
  224. /*
  225. * Find PCI-PCI bridges and recursively descend the tree.
  226. */
  227. if(p->ccrb != 0x06 || p->ccru != 0x04)
  228. continue;
  229. /*
  230. * If the secondary or subordinate bus number is not
  231. * initialised try to do what the PCI BIOS should have
  232. * done and fill in the numbers as the tree is descended.
  233. * On the way down the subordinate bus number is set to
  234. * the maximum as it's not known how many buses are behind
  235. * this one; the final value is set on the way back up.
  236. */
  237. sbn = pcicfgr8(p, PciSBN);
  238. ubn = pcicfgr8(p, PciUBN);
  239. if(sbn == 0 || ubn == 0) {
  240. print("%T: unconfigured bridge\n", p->tbdf);
  241. sbn = maxubn+1;
  242. /*
  243. * Make sure memory, I/O and master enables are
  244. * off, set the primary, secondary and subordinate
  245. * bus numbers and clear the secondary status before
  246. * attempting to scan the secondary bus.
  247. *
  248. * Initialisation of the bridge should be done here.
  249. */
  250. pcicfgw32(p, PciPCR, 0xFFFF0000);
  251. pcicfgw32(p, PciPBN, Maxbus<<16 | sbn<<8 | bno);
  252. pcicfgw16(p, PciSPSR, 0xFFFF);
  253. char *bus = mallocz(256, 1);
  254. snprint(bus, 256, "%s/%d.%d.0", path, BUSBNO(p->tbdf), BUSDNO(p->tbdf));
  255. maxubn = pcilscan(sbn, bus, &p->bridge);
  256. pcicfgw32(p, PciPBN, maxubn<<16 | sbn<<8 | bno);
  257. }
  258. else {
  259. /*
  260. * You can't go back.
  261. * This shouldn't be possible, but the
  262. * Iwill DK8-HTX seems to have subordinate
  263. * bus numbers which get smaller on the
  264. * way down. Need to look more closely at
  265. * this.
  266. */
  267. if(ubn > maxubn) {
  268. maxubn = ubn;
  269. }
  270. char *bus = mallocz(256, 1);
  271. snprint(bus, 256, "%s/%d.%d.0", path, BUSBNO(p->tbdf), BUSDNO(p->tbdf));
  272. pcilscan(sbn, bus, &p->bridge);
  273. }
  274. }
  275. return maxubn;
  276. }
  277. typedef struct Bridge Bridge;
  278. struct Bridge
  279. {
  280. uint16_t vid;
  281. uint16_t did;
  282. uint8_t (*get)(Pcidev *, uint8_t);
  283. void (*set)(Pcidev *, uint8_t, uint8_t);
  284. };
  285. typedef struct Slot Slot;
  286. struct Slot {
  287. uint8_t bus; // Pci bus number
  288. uint8_t dev; // Pci device number
  289. uint8_t maps[12]; // Avoid structs! Link and mask.
  290. uint8_t slot; // Add-in/built-in slot
  291. uint8_t reserved;
  292. };
  293. typedef struct Router Router;
  294. struct Router {
  295. uint8_t signature[4]; // Routing table signature
  296. uint8_t version[2]; // Version number
  297. uint8_t size[2]; // Total table size
  298. uint8_t bus; // Interrupt router bus number
  299. uint8_t devfn; // Router's devfunc
  300. uint8_t pciirqs[2]; // Exclusive PCI irqs
  301. uint8_t compat[4]; // Compatible PCI interrupt router
  302. uint8_t miniport[4]; // Miniport data
  303. uint8_t reserved[11];
  304. uint8_t checksum;
  305. };
  306. static void
  307. pcireservemem(void)
  308. {
  309. int i;
  310. Pcidev *p;
  311. for(p = nil; (p = pcimatch(p, 0, 0)) != nil;)
  312. for(i=0; i<nelem(p->mem); i++)
  313. if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
  314. asmmapinit(p->mem[i].bar&~0x0F, p->mem[i].size, 5);
  315. }
  316. static void
  317. pcicfginit(void)
  318. {
  319. int sbno, bno, n;
  320. Pcidev **list, *p;
  321. if(pcicfgmode != -1)
  322. return;
  323. lock(&pcicfginitlock);
  324. if(pcicfgmode != -1){
  325. unlock(&pcicfginitlock);
  326. return;
  327. }
  328. fmtinstall('T', tbdffmt);
  329. /*
  330. * Try to determine if PCI Mode1 configuration implemented.
  331. * (Bits [30:24] of PciADDR must be 0, according to the spec.)
  332. * Mode2 won't appear in 64-bit machines.
  333. */
  334. n = inl(PciADDR);
  335. if(!(n & 0x7F000000)){
  336. outl(PciADDR, 0x80000000);
  337. outb(PciADDR+3, 0);
  338. if(inl(PciADDR) & 0x80000000)
  339. pcicfgmode = 1;
  340. }
  341. outl(PciADDR, n);
  342. if(pcicfgmode < 0){
  343. unlock(&pcicfginitlock);
  344. return;
  345. }
  346. list = &pciroot;
  347. for(bno = 0; bno <= Maxbus; bno++) {
  348. sbno = bno;
  349. bno = pcilscan(bno, "0.0.0", list);
  350. while(*list)
  351. list = &(*list)->link;
  352. if(sbno != 0)
  353. continue;
  354. /*
  355. * If we have found a PCI-to-Cardbus bridge, make sure
  356. * it has no valid mappings anymore.
  357. */
  358. for(p = pciroot; p != nil; p = p->link){
  359. if (p->ccrb == 6 && p->ccru == 7) {
  360. /* reset the cardbus */
  361. pcicfgw16(p, PciBCR, 0x40 | pcicfgr16(p, PciBCR));
  362. delay(50);
  363. }
  364. }
  365. }
  366. pcireservemem();
  367. unlock(&pcicfginitlock);
  368. // Bring the virtio devices live.
  369. virtiosetup();
  370. //if(getconf("*pcihinv"))
  371. pcihinv(nil);
  372. }
  373. static int
  374. pcicfgrw(int tbdf, int r, int data, int rw, int w)
  375. {
  376. int o, x, er;
  377. pcicfginit();
  378. if(pcicfgmode != 1)
  379. return -1;
  380. if(BUSDNO(tbdf) > Maxdev)
  381. return -1;
  382. lock(&pcicfglock);
  383. o = r & (4-w);
  384. er = (r&0xfc) | ((r & 0xf00)<<16);
  385. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|er);
  386. if(rw == Read){
  387. x = -1;
  388. switch(w){
  389. case 1:
  390. x = inb(PciDATA+o);
  391. break;
  392. case 2:
  393. x = ins(PciDATA+o);
  394. break;
  395. case 4:
  396. x = inl(PciDATA+o);
  397. break;
  398. }
  399. }else{
  400. x = 0;
  401. switch(w){
  402. case 1:
  403. outb(PciDATA+o, data);
  404. break;
  405. case 2:
  406. outs(PciDATA+o, data);
  407. break;
  408. case 4:
  409. outl(PciDATA+o, data);
  410. break;
  411. }
  412. }
  413. // outl(PciADDR, 0);
  414. unlock(&pcicfglock);
  415. return x;
  416. }
  417. int
  418. pcicfgr8(Pcidev *p, int rno)
  419. {
  420. return pcicfgrw(p->tbdf, rno, 0, Read, 1);
  421. }
  422. void
  423. pcicfgw8(Pcidev *p, int rno, int data)
  424. {
  425. pcicfgrw(p->tbdf, rno, data, Write, 1);
  426. }
  427. int
  428. pcicfgr16(Pcidev *p, int rno)
  429. {
  430. return pcicfgrw(p->tbdf, rno, 0, Read, 2);
  431. }
  432. void
  433. pcicfgw16(Pcidev *p, int rno, int data)
  434. {
  435. pcicfgrw(p->tbdf, rno, data, Write, 2);
  436. }
  437. int
  438. pcicfgr32(Pcidev *p, int rno)
  439. {
  440. return pcicfgrw(p->tbdf, rno, 0, Read, 4);
  441. }
  442. void
  443. pcicfgw32(Pcidev *p, int rno, int data)
  444. {
  445. pcicfgrw(p->tbdf, rno, data, Write, 4);
  446. }
  447. Pcidev*
  448. pcimatch(Pcidev* prev, int vid, int did)
  449. {
  450. pcicfginit();
  451. prev = prev? prev->list: pcilist;
  452. for(; prev != nil; prev = prev->list){
  453. if((vid == 0 || prev->vid == vid)
  454. && (did == 0 || prev->did == did))
  455. break;
  456. }
  457. return prev;
  458. }
  459. Pcidev*
  460. pcimatchtbdf(int tbdf)
  461. {
  462. Pcidev *p;
  463. for(p = nil; (p = pcimatch(p, 0, 0)) != nil; )
  464. if(p->tbdf == tbdf)
  465. break;
  466. return p;
  467. }
  468. void
  469. pcishowdev(Pcidev* t)
  470. {
  471. int i;
  472. char intpin = 'x';
  473. /* intpin numbers can range from 1 to 8. */
  474. intpin = "xABCDEFGHxxxxxxx"[t->intp&0xf];
  475. print("%d %2d/%d %.2x %.2x %.2x %.4x %.4x %c %3d ",
  476. BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
  477. t->ccrb, t->ccru, t->ccrp, t->vid, t->did, intpin, t->intl);
  478. for(i = 0; i < nelem(t->mem); i++) {
  479. if(t->mem[i].size == 0)
  480. continue;
  481. print("%d:%.8llx %d ", i, t->mem[i].bar, t->mem[i].size);
  482. }
  483. if(t->ioa.bar || t->ioa.size)
  484. print("ioa:%.8llx %d ", t->ioa.bar, t->ioa.size);
  485. if(t->mema.bar || t->mema.size)
  486. if(t->bridge)
  487. print("->%d", BUSBNO(t->bridge->tbdf));
  488. print("\n");
  489. }
  490. static void
  491. pcilhinv(Pcidev* p)
  492. {
  493. Pcidev *t;
  494. for(t = p; t != nil; t = t->link)
  495. pcishowdev(t);
  496. for(; p != nil; p = p->link)
  497. if(p->bridge != nil)
  498. pcilhinv(p->bridge);
  499. }
  500. void
  501. pcihinv(Pcidev* p)
  502. {
  503. pcicfginit();
  504. lock(&pcicfginitlock);
  505. if(p == nil){
  506. p = pciroot;
  507. print("bus dev type vid did intl memory\n");
  508. }
  509. pcilhinv(p);
  510. unlock(&pcicfginitlock);
  511. }
  512. void
  513. pcireset(void)
  514. {
  515. Pcidev *p;
  516. for(p = nil; (p = pcimatch(p, 0, 0)) != nil;)
  517. /* don't mess with the bridges */
  518. if(p->ccrb != 0x06)
  519. pciclrbme(p);
  520. }
  521. void
  522. pcisetbme(Pcidev* p)
  523. {
  524. p->pcr |= MASen;
  525. pcicfgw16(p, PciPCR, p->pcr);
  526. }
  527. void
  528. pciclrbme(Pcidev* p)
  529. {
  530. p->pcr &= ~MASen;
  531. pcicfgw16(p, PciPCR, p->pcr);
  532. }
  533. void
  534. pcisetmwi(Pcidev* p)
  535. {
  536. p->pcr |= MemWrInv;
  537. pcicfgw16(p, PciPCR, p->pcr);
  538. }
  539. void
  540. pciclrmwi(Pcidev* p)
  541. {
  542. p->pcr &= ~MemWrInv;
  543. pcicfgw16(p, PciPCR, p->pcr);
  544. }
  545. // Find the capability offset in a PCI device configuration space.
  546. // It depends of whether a device is a bridge, or a regular PCI device.
  547. // Return a positive number (offset) if capabilities are present, or -1
  548. // if the device does not have capabilities.
  549. int
  550. pcicapoff(Pcidev *p)
  551. {
  552. int off;
  553. /* status register bit 4 has capabilities */
  554. if((pcicfgr16(p, PciPSR) & 1<<4) == 0)
  555. return -1;
  556. switch(pcicfgr8(p, PciHDT) & 0x7f){
  557. default:
  558. return -1;
  559. case 0: /* etc */
  560. case 1: /* pci to pci bridge */
  561. off = 0x34;
  562. break;
  563. case 2: /* cardbus bridge */
  564. off = 0x14;
  565. break;
  566. }
  567. return off;
  568. }
  569. // Obtain the offset to the needed capability (by its cap_vndr value)
  570. // in the device configuration space. Return a positive number (offset)
  571. // if the capability exists, or -1 otherwise.
  572. int
  573. pcicap(Pcidev *p, int cap)
  574. {
  575. int i, c, off;
  576. off = pcicapoff(p);
  577. if(off == -1)
  578. return -1;
  579. for(i = 48; i--;){
  580. off = pcicfgr8(p, off);
  581. if(off < 0x40 || (off & 3))
  582. break;
  583. off &= ~3;
  584. c = pcicfgr8(p, off);
  585. if(c == 0xff)
  586. break;
  587. if(c == cap)
  588. return off;
  589. off++;
  590. }
  591. return -1;
  592. }
  593. enum {
  594. Pmgcap = 2, /* capabilities; 2 bytes*/
  595. Pmgctl = 4, /* ctl/status; 2 bytes */
  596. Pmgbrg = 6, /* bridge support */
  597. Pmgdata = 7,
  598. };
  599. int
  600. pcigetpms(Pcidev* p)
  601. {
  602. int ptr;
  603. if((ptr = pcicap(p, PciCapPMG)) == -1)
  604. return -1;
  605. return pcicfgr16(p, ptr+Pmgctl) & 0x0003;
  606. }
  607. int
  608. pcisetpms(Pcidev* p, int state)
  609. {
  610. int pmc, pmcsr, ptr;
  611. if((ptr = pcicap(p, PciCapPMG)) == -1)
  612. return -1;
  613. pmc = pcicfgr16(p, ptr+Pmgcap);
  614. pmcsr = pcicfgr16(p, ptr+Pmgctl);
  615. switch(state){
  616. default:
  617. return -1;
  618. case 0:
  619. break;
  620. case 1:
  621. if(!(pmc & 0x0200))
  622. return -1;
  623. break;
  624. case 2:
  625. if(!(pmc & 0x0400))
  626. return -1;
  627. break;
  628. case 3:
  629. break;
  630. }
  631. pcicfgw16(p, ptr+4, (pmcsr & ~3) | state);
  632. return pmcsr & 3;
  633. }