sdiahci.c 45 KB

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  1. /*
  2. * This file is part of the UCB release of Plan 9. It is subject to the license
  3. * terms in the LICENSE file found in the top-level directory of this
  4. * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
  5. * part of the UCB release of Plan 9, including this file, may be copied,
  6. * modified, propagated, or distributed except according to the terms contained
  7. * in the LICENSE file.
  8. */
  9. /*
  10. * ahci serial ata driver
  11. * copyright © 2007-8 coraid, inc.
  12. */
  13. #include "u.h"
  14. #include "../port/lib.h"
  15. #include "mem.h"
  16. #include "dat.h"
  17. #include "fns.h"
  18. #include "io.h"
  19. #include "../port/error.h"
  20. #include "../port/sd.h"
  21. #include "ahci.h"
  22. enum {
  23. Vatiamd = 0x1002,
  24. Vintel = 0x8086,
  25. Vmarvell= 0x1b4b,
  26. };
  27. #define dprint(...) do if(debug) iprint(__VA_ARGS__); while(0)
  28. #define idprint(...) do if(prid) iprint(__VA_ARGS__); while(0)
  29. #define aprint(...) do if(datapi) iprint(__VA_ARGS__); while(0)
  30. #define Tname(c) tname[(c)->type]
  31. #define Intel(x) ((x)->pci->vid == Vintel)
  32. enum {
  33. NCtlr = 16,
  34. NCtlrdrv= 32,
  35. NDrive = NCtlr*NCtlrdrv,
  36. Read = 0,
  37. Write,
  38. Nms = 256, /* ms. between drive checks */
  39. Mphywait= 2*1024/Nms - 1,
  40. Midwait = 16*1024/Nms - 1,
  41. Mcomrwait= 64*1024/Nms - 1,
  42. Obs = 0xa0, /* obsolete device bits */
  43. /*
  44. * if we get more than this many interrupts per tick for a drive,
  45. * either the hardware is broken or we've got a bug in this driver.
  46. */
  47. Maxintrspertick = 2000, /* was 1000 */
  48. };
  49. /* pci space configuration */
  50. enum {
  51. Pmap = 0x90,
  52. Ppcs = 0x91,
  53. Prev = 0xa8,
  54. };
  55. enum {
  56. Tesb,
  57. Tich,
  58. Tsb600,
  59. Tunk,
  60. };
  61. static char *tname[] = {
  62. "63xxesb",
  63. "ich",
  64. "sb600",
  65. "unknown",
  66. };
  67. enum {
  68. Dnull,
  69. Dmissing,
  70. Dnew,
  71. Dready,
  72. Derror,
  73. Dreset,
  74. Doffline,
  75. Dportreset,
  76. Dlast,
  77. };
  78. static char *diskstates[Dlast] = {
  79. "null",
  80. "missing",
  81. "new",
  82. "ready",
  83. "error",
  84. "reset",
  85. "offline",
  86. "portreset",
  87. };
  88. enum {
  89. DMautoneg,
  90. DMsatai,
  91. DMsataii,
  92. DMsata3,
  93. };
  94. static char *modename[] = { /* used in control messages */
  95. "auto",
  96. "satai",
  97. "sataii",
  98. "sata3",
  99. };
  100. static char *descmode[] = { /* only printed */
  101. "auto",
  102. "sata 1",
  103. "sata 2",
  104. "sata 3",
  105. };
  106. static char *flagname[] = {
  107. "llba",
  108. "smart",
  109. "power",
  110. "nop",
  111. "atapi",
  112. "atapi16",
  113. };
  114. typedef struct Asleep Asleep;
  115. typedef struct Ctlr Ctlr;
  116. typedef struct Drive Drive;
  117. struct Drive {
  118. Lock Lock;
  119. Ctlr *ctlr;
  120. SDunit *unit;
  121. char name[10];
  122. Aport *port;
  123. Aportm portm;
  124. Aportc portc; /* redundant ptr to port and portm */
  125. unsigned char mediachange;
  126. unsigned char state;
  127. unsigned char smartrs;
  128. uint64_t sectors;
  129. uint32_t secsize;
  130. uint32_t intick; /* start tick of current transfer */
  131. uint32_t lastseen;
  132. int wait;
  133. unsigned char mode; /* DMautoneg, satai or sataii */
  134. unsigned char active;
  135. char serial[20+1];
  136. char firmware[8+1];
  137. char model[40+1];
  138. int infosz;
  139. uint16_t *info;
  140. uint16_t tinyinfo[2]; /* used iff malloc fails */
  141. int driveno; /* ctlr*NCtlrdrv + unit */
  142. /* controller port # != driveno when not all ports are enabled */
  143. int portno;
  144. uint32_t lastintr0;
  145. uint32_t intrs;
  146. };
  147. struct Ctlr {
  148. Lock Lock;
  149. int type;
  150. int enabled;
  151. SDev *sdev;
  152. Pcidev *pci;
  153. void* vector;
  154. /* virtual register addresses */
  155. unsigned char *mmio;
  156. uint32_t *lmmio;
  157. Ahba *hba;
  158. /* phyical register address */
  159. unsigned char *physio;
  160. Drive *rawdrive;
  161. Drive *drive[NCtlrdrv];
  162. int ndrive;
  163. int mport; /* highest drive # (0-origin) on ich9 at least */
  164. uint32_t lastintr0;
  165. uint32_t intrs; /* not attributable to any drive */
  166. };
  167. struct Asleep {
  168. Aport *p;
  169. int i;
  170. };
  171. extern SDifc sdiahciifc;
  172. static Ctlr iactlr[NCtlr];
  173. static SDev sdevs[NCtlr];
  174. static int niactlr;
  175. static Drive *iadrive[NDrive];
  176. static int niadrive;
  177. /* these are fiddled in iawtopctl() */
  178. static int debug;
  179. static int prid = 1;
  180. static int datapi;
  181. // TODO: does this get initialized correctly?
  182. static char stab[] = {
  183. [0] = 'i', 'm',
  184. [8] = 't', 'c', 'p', 'e',
  185. [16] = 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  186. };
  187. static void
  188. serrstr(uint32_t r, char *s, char *e)
  189. {
  190. int i;
  191. e -= 3;
  192. for(i = 0; i < nelem(stab) && s < e; i++)
  193. if(r & (1<<i) && stab[i]){
  194. *s++ = stab[i];
  195. if(SerrBad & (1<<i))
  196. *s++ = '*';
  197. }
  198. *s = 0;
  199. }
  200. static char ntab[] = "0123456789abcdef";
  201. static void
  202. preg(unsigned char *reg, int n)
  203. {
  204. int i;
  205. char buf[25*3+1], *e;
  206. e = buf;
  207. for(i = 0; i < n; i++){
  208. *e++ = ntab[reg[i]>>4];
  209. *e++ = ntab[reg[i]&0xf];
  210. *e++ = ' ';
  211. }
  212. *e++ = '\n';
  213. *e = 0;
  214. dprint(buf);
  215. }
  216. static void
  217. dreg(char *s, Aport *p)
  218. {
  219. dprint("ahci: %stask=%#lx; cmd=%#lx; ci=%#lx; is=%#lx\n",
  220. s, p->task, p->cmd, p->ci, p->isr);
  221. }
  222. static void
  223. esleep(int ms)
  224. {
  225. Proc *up = externup();
  226. if(waserror())
  227. return;
  228. tsleep(&up->sleep, return0, 0, ms);
  229. poperror();
  230. }
  231. static int
  232. ahciclear(void *v)
  233. {
  234. Asleep *s;
  235. s = v;
  236. return (s->p->ci & s->i) == 0;
  237. }
  238. static void
  239. aesleep(Aportm *pm, Asleep *a, int ms)
  240. {
  241. Proc *up = externup();
  242. if(waserror())
  243. return;
  244. tsleep(&pm->Rendez, ahciclear, a, ms);
  245. poperror();
  246. }
  247. static int
  248. ahciwait(Aportc *c, int ms)
  249. {
  250. Asleep as;
  251. Aport *p;
  252. p = c->p;
  253. p->ci = 1;
  254. as.p = p;
  255. as.i = 1;
  256. aesleep(c->pm, &as, ms);
  257. if((p->task&1) == 0 && p->ci == 0)
  258. return 0;
  259. dreg("ahciwait timeout ", c->p);
  260. return -1;
  261. }
  262. /* fill in cfis boilerplate */
  263. static unsigned char *
  264. cfissetup(Aportc *pc)
  265. {
  266. unsigned char *cfis;
  267. cfis = pc->pm->ctab->cfis;
  268. memset(cfis, 0, 0x20);
  269. cfis[0] = 0x27;
  270. cfis[1] = 0x80;
  271. cfis[7] = Obs;
  272. return cfis;
  273. }
  274. /* initialise pc's list */
  275. static void
  276. listsetup(Aportc *pc, int flags)
  277. {
  278. Alist *list;
  279. list = pc->pm->list;
  280. list->flags = flags | 5;
  281. list->len = 0;
  282. list->ctab = PCIWADDR(pc->pm->ctab);
  283. list->ctabhi = PCIWADDR(pc->pm->ctab)>>32;
  284. }
  285. static int
  286. nop(Aportc *pc)
  287. {
  288. unsigned char *c;
  289. if((pc->pm->feat & Dnop) == 0)
  290. return -1;
  291. c = cfissetup(pc);
  292. c[2] = 0;
  293. listsetup(pc, Lwrite);
  294. return ahciwait(pc, 3*1000);
  295. }
  296. static int
  297. setfeatures(Aportc *pc, unsigned char f)
  298. {
  299. unsigned char *c;
  300. c = cfissetup(pc);
  301. c[2] = 0xef;
  302. c[3] = f;
  303. listsetup(pc, Lwrite);
  304. return ahciwait(pc, 3*1000);
  305. }
  306. static int
  307. setudmamode(Aportc *pc, unsigned char f)
  308. {
  309. unsigned char *c;
  310. /* hack */
  311. if((pc->p->sig >> 16) == 0xeb14)
  312. return 0;
  313. c = cfissetup(pc);
  314. c[2] = 0xef;
  315. c[3] = 3; /* set transfer mode */
  316. c[12] = 0x40 | f; /* sector count */
  317. listsetup(pc, Lwrite);
  318. return ahciwait(pc, 3*1000);
  319. }
  320. static void
  321. asleep(int ms)
  322. {
  323. Proc *up = externup();
  324. if(up == nil)
  325. delay(ms);
  326. else
  327. esleep(ms);
  328. }
  329. static int
  330. ahciportreset(Aportc *c)
  331. {
  332. uint32_t *cmd, i;
  333. Aport *p;
  334. p = c->p;
  335. cmd = &p->cmd;
  336. *cmd &= ~(Afre|Ast);
  337. for(i = 0; i < 500; i += 25){
  338. if((*cmd&Acr) == 0)
  339. break;
  340. asleep(25);
  341. }
  342. p->sctl = 1|(p->sctl&~7);
  343. delay(1);
  344. p->sctl &= ~7;
  345. return 0;
  346. }
  347. static int
  348. smart(Aportc *pc, int n)
  349. {
  350. unsigned char *c;
  351. if((pc->pm->feat&Dsmart) == 0)
  352. return -1;
  353. c = cfissetup(pc);
  354. c[2] = 0xb0;
  355. c[3] = 0xd8 + n; /* able smart */
  356. c[5] = 0x4f;
  357. c[6] = 0xc2;
  358. listsetup(pc, Lwrite);
  359. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  360. dprint("ahci: smart fail %#lx\n", pc->p->task);
  361. // preg(pc->m->fis.r, 20);
  362. return -1;
  363. }
  364. if(n)
  365. return 0;
  366. return 1;
  367. }
  368. static int
  369. smartrs(Aportc *pc)
  370. {
  371. unsigned char *c;
  372. c = cfissetup(pc);
  373. c[2] = 0xb0;
  374. c[3] = 0xda; /* return smart status */
  375. c[5] = 0x4f;
  376. c[6] = 0xc2;
  377. listsetup(pc, Lwrite);
  378. c = pc->pm->fis.r;
  379. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  380. dprint("ahci: smart fail %#lx\n", pc->p->task);
  381. preg(c, 20);
  382. return -1;
  383. }
  384. if(c[5] == 0x4f && c[6] == 0xc2)
  385. return 1;
  386. return 0;
  387. }
  388. static int
  389. ahciflushcache(Aportc *pc)
  390. {
  391. unsigned char *c;
  392. c = cfissetup(pc);
  393. c[2] = pc->pm->feat & Dllba? 0xea: 0xe7;
  394. listsetup(pc, Lwrite);
  395. if(ahciwait(pc, 60000) == -1 || pc->p->task & (1|32)){
  396. dprint("ahciflushcache: fail %#lx\n", pc->p->task);
  397. // preg(pc->m->fis.r, 20);
  398. return -1;
  399. }
  400. return 0;
  401. }
  402. static uint16_t
  403. gbit16(void *a)
  404. {
  405. unsigned char *i;
  406. i = a;
  407. return i[1]<<8 | i[0];
  408. }
  409. static uint32_t
  410. gbit32(void *a)
  411. {
  412. uint32_t j;
  413. unsigned char *i;
  414. i = a;
  415. j = i[3] << 24;
  416. j |= i[2] << 16;
  417. j |= i[1] << 8;
  418. j |= i[0];
  419. return j;
  420. }
  421. static uint64_t
  422. gbit64(void *a)
  423. {
  424. unsigned char *i;
  425. i = a;
  426. return (uint64_t)gbit32(i+4) << 32 | gbit32(a);
  427. }
  428. static int
  429. ahciidentify0(Aportc *pc, void *id, int atapi)
  430. {
  431. unsigned char *c;
  432. Aprdt *p;
  433. static unsigned char tab[] = { 0xec, 0xa1, };
  434. c = cfissetup(pc);
  435. c[2] = tab[atapi];
  436. listsetup(pc, 1<<16);
  437. memset(id, 0, 0x100); /* magic */
  438. p = &pc->pm->ctab->prdt;
  439. p->dba = PCIWADDR(id);
  440. p->dbahi = PCIWADDR(id)>>32;
  441. p->count = 1<<31 | (0x200-2) | 1;
  442. return ahciwait(pc, 3*1000);
  443. }
  444. static int64_t
  445. ahciidentify(Aportc *pc, uint16_t *id)
  446. {
  447. int i, sig;
  448. int64_t s;
  449. Aportm *pm;
  450. pm = pc->pm;
  451. pm->feat = 0;
  452. pm->smart = 0;
  453. i = 0;
  454. sig = pc->p->sig >> 16;
  455. if(sig == 0xeb14){
  456. pm->feat |= Datapi;
  457. i = 1;
  458. }
  459. if(ahciidentify0(pc, id, i) == -1)
  460. return -1;
  461. i = gbit16(id+83) | gbit16(id+86);
  462. if(i & (1<<10)){
  463. pm->feat |= Dllba;
  464. s = gbit64(id+100);
  465. }else
  466. s = gbit32(id+60);
  467. if(pm->feat&Datapi){
  468. i = gbit16(id+0);
  469. if(i&1)
  470. pm->feat |= Datapi16;
  471. }
  472. i = gbit16(id+83);
  473. if((i>>14) == 1) {
  474. if(i & (1<<3))
  475. pm->feat |= Dpower;
  476. i = gbit16(id+82);
  477. if(i & 1)
  478. pm->feat |= Dsmart;
  479. if(i & (1<<14))
  480. pm->feat |= Dnop;
  481. }
  482. return s;
  483. }
  484. #if 0
  485. static int
  486. ahciquiet(Aport *a)
  487. {
  488. uint32_t *p, i;
  489. p = &a->cmd;
  490. *p &= ~Ast;
  491. for(i = 0; i < 500; i += 50){
  492. if((*p & Acr) == 0)
  493. goto stop;
  494. asleep(50);
  495. }
  496. return -1;
  497. stop:
  498. if((a->task & (ASdrq|ASbsy)) == 0){
  499. *p |= Ast;
  500. return 0;
  501. }
  502. *p |= Aclo;
  503. for(i = 0; i < 500; i += 50){
  504. if((*p & Aclo) == 0)
  505. goto stop1;
  506. asleep(50);
  507. }
  508. return -1;
  509. stop1:
  510. /* extra check */
  511. dprint("ahci: clo clear %#lx\n", a->task);
  512. if(a->task & ASbsy)
  513. return -1;
  514. *p |= Ast;
  515. return 0;
  516. }
  517. #endif
  518. #if 0
  519. static int
  520. ahcicomreset(Aportc *pc)
  521. {
  522. unsigned char *c;
  523. dprint("ahcicomreset\n");
  524. dreg("ahci: comreset ", pc->p);
  525. if(ahciquiet(pc->p) == -1){
  526. dprint("ahciquiet failed\n");
  527. return -1;
  528. }
  529. dreg("comreset ", pc->p);
  530. c = cfissetup(pc);
  531. c[1] = 0;
  532. c[15] = 1<<2; /* srst */
  533. listsetup(pc, Lclear | Lreset);
  534. if(ahciwait(pc, 500) == -1){
  535. dprint("ahcicomreset: first command failed\n");
  536. return -1;
  537. }
  538. microdelay(250);
  539. dreg("comreset ", pc->p);
  540. c = cfissetup(pc);
  541. c[1] = 0;
  542. listsetup(pc, Lwrite);
  543. if(ahciwait(pc, 150) == -1){
  544. dprint("ahcicomreset: second command failed\n");
  545. return -1;
  546. }
  547. dreg("comreset ", pc->p);
  548. return 0;
  549. }
  550. #endif
  551. static int
  552. ahciidle(Aport *port)
  553. {
  554. uint32_t *p, i, r;
  555. p = &port->cmd;
  556. if((*p & Arun) == 0)
  557. return 0;
  558. *p &= ~Ast;
  559. r = 0;
  560. for(i = 0; i < 500; i += 25){
  561. if((*p & Acr) == 0)
  562. goto stop;
  563. asleep(25);
  564. }
  565. r = -1;
  566. stop:
  567. if((*p & Afre) == 0)
  568. return r;
  569. *p &= ~Afre;
  570. for(i = 0; i < 500; i += 25){
  571. if((*p & Afre) == 0)
  572. return 0;
  573. asleep(25);
  574. }
  575. return -1;
  576. }
  577. /*
  578. * § 6.2.2.1 first part; comreset handled by reset disk.
  579. * - remainder is handled by configdisk.
  580. * - ahcirecover is a quick recovery from a failed command.
  581. */
  582. static int
  583. ahciswreset(Aportc *pc)
  584. {
  585. int i;
  586. i = ahciidle(pc->p);
  587. pc->p->cmd |= Afre;
  588. if(i == -1)
  589. return -1;
  590. if(pc->p->task & (ASdrq|ASbsy))
  591. return -1;
  592. return 0;
  593. }
  594. static int
  595. ahcirecover(Aportc *pc)
  596. {
  597. ahciswreset(pc);
  598. pc->p->cmd |= Ast;
  599. if(setudmamode(pc, 5) == -1)
  600. return -1;
  601. return 0;
  602. }
  603. static void*
  604. malign(int size, int align)
  605. {
  606. return mallocalign(size, align, 0, 0);
  607. }
  608. static void
  609. setupfis(Afis *f)
  610. {
  611. f->base = malign(0x100, 0x100); /* magic */
  612. f->d = f->base + 0;
  613. f->p = f->base + 0x20;
  614. f->r = f->base + 0x40;
  615. f->u = f->base + 0x60;
  616. f->devicebits = (uint32_t*)(f->base + 0x58);
  617. }
  618. static void
  619. ahciwakeup(Aport *p)
  620. {
  621. uint16_t s;
  622. s = p->sstatus;
  623. if((s & Intpm) != Intslumber && (s & Intpm) != Intpartpwr)
  624. return;
  625. if((s & Devdet) != Devpresent){ /* not (device, no phy) */
  626. iprint("ahci: slumbering drive unwakable %#x\n", s);
  627. return;
  628. }
  629. p->sctl = 3*Aipm | 0*Aspd | Adet;
  630. delay(1);
  631. p->sctl &= ~7;
  632. // iprint("ahci: wake %#x -> %#x\n", s, p->sstatus);
  633. }
  634. static int
  635. ahciconfigdrive(Drive *d)
  636. {
  637. char *name;
  638. Ahba *h;
  639. Aport *p;
  640. Aportm *pm;
  641. h = d->ctlr->hba;
  642. p = d->portc.p;
  643. pm = d->portc.pm;
  644. if(pm->list == 0){
  645. setupfis(&pm->fis);
  646. pm->list = malign(sizeof *pm->list, 1024);
  647. pm->ctab = malign(sizeof *pm->ctab, 128);
  648. }
  649. if (d->unit)
  650. name = d->unit->SDperm.name;
  651. else
  652. name = nil;
  653. if(p->sstatus & (Devphycomm|Devpresent) && h->cap & Hsss){
  654. /* device connected & staggered spin-up */
  655. dprint("ahci: configdrive: %s: spinning up ... [%#lx]\n",
  656. name, p->sstatus);
  657. p->cmd |= Apod|Asud;
  658. asleep(1400);
  659. }
  660. p->serror = SerrAll;
  661. p->list = PCIWADDR(pm->list);
  662. p->listhi = PCIWADDR(pm->list)>>32;
  663. p->fis = PCIWADDR(pm->fis.base);
  664. p->fishi = PCIWADDR(pm->fis.base)>>32;
  665. p->cmd |= Afre|Ast;
  666. /* drive coming up in slumbering? */
  667. if((p->sstatus & Devdet) == Devpresent &&
  668. ((p->sstatus & Intpm) == Intslumber ||
  669. (p->sstatus & Intpm) == Intpartpwr))
  670. ahciwakeup(p);
  671. /* "disable power managment" sequence from book. */
  672. p->sctl = (3*Aipm) | (d->mode*Aspd) | (0*Adet);
  673. p->cmd &= ~Aalpe;
  674. p->ie = IEM;
  675. return 0;
  676. }
  677. static void
  678. ahcienable(Ahba *h)
  679. {
  680. h->ghc |= Hie;
  681. }
  682. static void
  683. ahcidisable(Ahba *h)
  684. {
  685. h->ghc &= ~Hie;
  686. }
  687. static int
  688. countbits(uint32_t u)
  689. {
  690. int n;
  691. n = 0;
  692. for (; u != 0; u >>= 1)
  693. if(u & 1)
  694. n++;
  695. return n;
  696. }
  697. static int
  698. ahciconf(Ctlr *ctlr)
  699. {
  700. Ahba *h;
  701. uint32_t u;
  702. h = ctlr->hba = (Ahba*)ctlr->mmio;
  703. u = h->cap;
  704. if((u&Hsam) == 0)
  705. h->ghc |= Hae;
  706. dprint("#S/sd%c: type %s port %#p: sss %ld ncs %ld coal %ld "
  707. "%ld ports, led %ld clo %ld ems %ld\n",
  708. ctlr->sdev->idno, tname[ctlr->type], h,
  709. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1,
  710. (u & 0x1f) + 1, (u>>25) & 1, (u>>24) & 1, (u>>6) & 1);
  711. return countbits(h->pi);
  712. }
  713. #if 0
  714. static int
  715. ahcihbareset(Ahba *h)
  716. {
  717. int wait;
  718. h->ghc |= 1;
  719. for(wait = 0; wait < 1000; wait += 100){
  720. if(h->ghc == 0)
  721. return 0;
  722. delay(100);
  723. }
  724. return -1;
  725. }
  726. #endif
  727. static void
  728. idmove(char *p, uint16_t *a, int n)
  729. {
  730. int i;
  731. char *op, *e;
  732. op = p;
  733. for(i = 0; i < n/2; i++){
  734. *p++ = a[i] >> 8;
  735. *p++ = a[i];
  736. }
  737. *p = 0;
  738. while(p > op && *--p == ' ')
  739. *p = 0;
  740. e = p;
  741. for (p = op; *p == ' '; p++)
  742. ;
  743. memmove(op, p, n - (e - p));
  744. }
  745. static int
  746. identify(Drive *d)
  747. {
  748. uint16_t *id;
  749. int64_t osectors, s;
  750. unsigned char oserial[21];
  751. SDunit *u;
  752. if(d->info == nil) {
  753. d->infosz = 512 * sizeof(uint16_t);
  754. d->info = malloc(d->infosz);
  755. }
  756. if(d->info == nil) {
  757. d->info = d->tinyinfo;
  758. d->infosz = sizeof d->tinyinfo;
  759. }
  760. id = d->info;
  761. s = ahciidentify(&d->portc, id);
  762. if(s == -1){
  763. d->state = Derror;
  764. return -1;
  765. }
  766. osectors = d->sectors;
  767. memmove(oserial, d->serial, sizeof d->serial);
  768. u = d->unit;
  769. d->sectors = s;
  770. d->secsize = u->secsize;
  771. if(d->secsize == 0)
  772. d->secsize = 512; /* default */
  773. d->smartrs = 0;
  774. idmove(d->serial, id+10, 20);
  775. idmove(d->firmware, id+23, 8);
  776. idmove(d->model, id+27, 40);
  777. memset(u->inquiry, 0, sizeof u->inquiry);
  778. u->inquiry[2] = 2;
  779. u->inquiry[3] = 2;
  780. u->inquiry[4] = sizeof u->inquiry - 4;
  781. memmove(u->inquiry+8, d->model, 40);
  782. if(osectors != s || memcmp(oserial, d->serial, sizeof oserial) != 0){
  783. d->mediachange = 1;
  784. u->sectors = 0;
  785. }
  786. return 0;
  787. }
  788. static void
  789. clearci(Aport *p)
  790. {
  791. if(p->cmd & Ast) {
  792. p->cmd &= ~Ast;
  793. p->cmd |= Ast;
  794. }
  795. }
  796. static void
  797. updatedrive(Drive *d)
  798. {
  799. uint32_t cause, serr, s0, pr, ewake;
  800. char *name;
  801. Aport *p;
  802. static uint32_t last;
  803. pr = 1;
  804. ewake = 0;
  805. p = d->port;
  806. cause = p->isr;
  807. serr = p->serror;
  808. p->isr = cause;
  809. name = "??";
  810. if(d->unit && d->unit->SDperm.name)
  811. name = d->unit->SDperm.name;
  812. if(p->ci == 0){
  813. d->portm.flag |= Fdone;
  814. wakeup(&d->portm.Rendez);
  815. pr = 0;
  816. }else if(cause & Adps)
  817. pr = 0;
  818. if(cause & Ifatal){
  819. ewake = 1;
  820. dprint("ahci: updatedrive: %s: fatal\n", name);
  821. }
  822. if(cause & Adhrs){
  823. if(p->task & (1<<5|1)){
  824. dprint("ahci: %s: Adhrs cause %#lx serr %#lx task %#lx\n",
  825. name, cause, serr, p->task);
  826. d->portm.flag |= Ferror;
  827. ewake = 1;
  828. }
  829. pr = 0;
  830. }
  831. if((p->task & 1) && last != cause)
  832. dprint("%s: err ca %#lx serr %#lx task %#lx sstat %#lx\n",
  833. name, cause, serr, p->task, p->sstatus);
  834. if(pr)
  835. dprint("%s: upd %#lx ta %#lx\n", name, cause, p->task);
  836. if(cause & (Aprcs|Aifs)){
  837. s0 = d->state;
  838. switch(p->sstatus & Devdet){
  839. case 0: /* no device */
  840. d->state = Dmissing;
  841. break;
  842. case Devpresent: /* device but no phy comm. */
  843. if((p->sstatus & Intpm) == Intslumber ||
  844. (p->sstatus & Intpm) == Intpartpwr)
  845. d->state = Dnew; /* slumbering */
  846. else
  847. d->state = Derror;
  848. break;
  849. case Devpresent|Devphycomm:
  850. /* power mgnt crap for surprise removal */
  851. p->ie |= Aprcs|Apcs; /* is this required? */
  852. d->state = Dreset;
  853. break;
  854. case Devphyoffline:
  855. d->state = Doffline;
  856. break;
  857. }
  858. dprint("%s: %s → %s [Apcrs] %#lx\n", name,
  859. diskstates[s0], diskstates[d->state], p->sstatus);
  860. /* print pulled message here. */
  861. if(s0 == Dready && d->state != Dready)
  862. idprint("%s: pulled\n", name); /* wtf? */
  863. if(d->state != Dready)
  864. d->portm.flag |= Ferror;
  865. ewake = 1;
  866. }
  867. p->serror = serr;
  868. if(ewake){
  869. clearci(p);
  870. wakeup(&d->portm.Rendez);
  871. }
  872. last = cause;
  873. }
  874. static void
  875. pstatus(Drive *d, uint32_t s)
  876. {
  877. /*
  878. * s is masked with Devdet.
  879. *
  880. * bogus code because the first interrupt is currently dropped.
  881. * likely my fault. serror may be cleared at the wrong time.
  882. */
  883. switch(s){
  884. case 0: /* no device */
  885. d->state = Dmissing;
  886. break;
  887. case Devpresent: /* device but no phy. comm. */
  888. break;
  889. case Devphycomm: /* should this be missing? need testcase. */
  890. dprint("ahci: pstatus 2\n");
  891. /* fallthrough */
  892. case Devpresent|Devphycomm:
  893. d->wait = 0;
  894. d->state = Dnew;
  895. break;
  896. case Devphyoffline:
  897. d->state = Doffline;
  898. break;
  899. case Devphyoffline|Devphycomm: /* does this make sense? */
  900. d->state = Dnew;
  901. break;
  902. }
  903. }
  904. static int
  905. configdrive(Drive *d)
  906. {
  907. if(ahciconfigdrive(d) == -1)
  908. return -1;
  909. ilock(&d->Lock);
  910. pstatus(d, d->port->sstatus & Devdet);
  911. iunlock(&d->Lock);
  912. return 0;
  913. }
  914. static void
  915. setstate(Drive *d, int state)
  916. {
  917. ilock(&d->Lock);
  918. d->state = state;
  919. iunlock(&d->Lock);
  920. }
  921. static void
  922. resetdisk(Drive *d)
  923. {
  924. uint state, det, stat;
  925. Aport *p;
  926. p = d->port;
  927. det = p->sctl & 7;
  928. stat = p->sstatus & Devdet;
  929. state = (p->cmd>>28) & 0xf;
  930. dprint("ahci: resetdisk: icc %#x det %d sdet %d\n", state, det, stat);
  931. ilock(&d->Lock);
  932. state = d->state;
  933. if(d->state != Dready || d->state != Dnew)
  934. d->portm.flag |= Ferror;
  935. clearci(p); /* satisfy sleep condition. */
  936. wakeup(&d->portm.Rendez);
  937. if(stat != (Devpresent|Devphycomm)){
  938. /* device absent or phy not communicating */
  939. d->state = Dportreset;
  940. iunlock(&d->Lock);
  941. return;
  942. }
  943. d->state = Derror;
  944. iunlock(&d->Lock);
  945. qlock(&d->portm.ql);
  946. if(p->cmd&Ast && ahciswreset(&d->portc) == -1)
  947. setstate(d, Dportreset); /* get a bigger stick. */
  948. else {
  949. setstate(d, Dmissing);
  950. configdrive(d);
  951. }
  952. dprint("ahci: %s: resetdisk: %s → %s\n", (d->unit? d->unit->SDperm.name: nil),
  953. diskstates[state], diskstates[d->state]);
  954. qunlock(&d->portm.ql);
  955. }
  956. static int
  957. newdrive(Drive *d)
  958. {
  959. char *name;
  960. Aportc *c;
  961. Aportm *pm;
  962. c = &d->portc;
  963. pm = &d->portm;
  964. name = d->unit->SDperm.name;
  965. if(name == 0)
  966. name = "??";
  967. if(d->port->task == 0x80)
  968. return -1;
  969. qlock(&c->pm->ql);
  970. if(setudmamode(c, 5) == -1){
  971. dprint("%s: can't set udma mode\n", name);
  972. goto lose;
  973. }
  974. if(identify(d) == -1){
  975. dprint("%s: identify failure\n", name);
  976. goto lose;
  977. }
  978. if(pm->feat & Dpower && setfeatures(c, 0x85) == -1){
  979. pm->feat &= ~Dpower;
  980. if(ahcirecover(c) == -1)
  981. goto lose;
  982. }
  983. setstate(d, Dready);
  984. qunlock(&c->pm->ql);
  985. idprint("%s: %sLBA %,llu sectors: %s %s %s %s\n", d->unit->SDperm.name,
  986. (pm->feat & Dllba? "L": ""), d->sectors, d->model, d->firmware,
  987. d->serial, d->mediachange? "[mediachange]": "");
  988. return 0;
  989. lose:
  990. idprint("%s: can't be initialized\n", d->unit->SDperm.name);
  991. setstate(d, Dnull);
  992. qunlock(&c->pm->ql);
  993. return -1;
  994. }
  995. static void
  996. westerndigitalhung(Drive *d)
  997. {
  998. if((d->portm.feat&Datapi) == 0 && d->active &&
  999. TK2MS(sys->ticks - d->intick) > 5000){
  1000. dprint("%s: drive hung; resetting [%#lx] ci %#lx\n",
  1001. d->unit->SDperm.name, d->port->task, d->port->ci);
  1002. d->state = Dreset;
  1003. }
  1004. }
  1005. static uint16_t olds[NCtlr*NCtlrdrv];
  1006. static int
  1007. doportreset(Drive *d)
  1008. {
  1009. int i;
  1010. i = -1;
  1011. qlock(&d->portm.ql);
  1012. if(ahciportreset(&d->portc) == -1)
  1013. dprint("ahci: doportreset: fails\n");
  1014. else
  1015. i = 0;
  1016. qunlock(&d->portm.ql);
  1017. dprint("ahci: doportreset: portreset → %s [task %#lx]\n",
  1018. diskstates[d->state], d->port->task);
  1019. return i;
  1020. }
  1021. /* drive must be locked */
  1022. static void
  1023. statechange(Drive *d)
  1024. {
  1025. switch(d->state){
  1026. case Dnull:
  1027. case Doffline:
  1028. if(d->unit->sectors != 0){
  1029. d->sectors = 0;
  1030. d->mediachange = 1;
  1031. }
  1032. /* fallthrough */
  1033. case Dready:
  1034. d->wait = 0;
  1035. break;
  1036. }
  1037. }
  1038. static void
  1039. checkdrive(Drive *d, int i)
  1040. {
  1041. uint16_t s;
  1042. char *name;
  1043. if(d == nil) {
  1044. print("checkdrive: nil d\n");
  1045. return;
  1046. }
  1047. ilock(&d->Lock);
  1048. if(d->unit == nil || d->port == nil) {
  1049. if(0)
  1050. print("checkdrive: nil d->%s\n",
  1051. d->unit == nil? "unit": "port");
  1052. iunlock(&d->Lock);
  1053. return;
  1054. }
  1055. name = d->unit->SDperm.name;
  1056. s = d->port->sstatus;
  1057. if(s)
  1058. d->lastseen = sys->ticks;
  1059. if(s != olds[i]){
  1060. dprint("%s: status: %06#x -> %06#x: %s\n",
  1061. name, olds[i], s, diskstates[d->state]);
  1062. olds[i] = s;
  1063. d->wait = 0;
  1064. }
  1065. westerndigitalhung(d);
  1066. switch(d->state){
  1067. case Dnull:
  1068. case Dready:
  1069. break;
  1070. case Dmissing:
  1071. case Dnew:
  1072. switch(s & (Intactive | Devdet)){
  1073. case Devpresent: /* no device (pm), device but no phy. comm. */
  1074. ahciwakeup(d->port);
  1075. /* fall through */
  1076. case 0: /* no device */
  1077. break;
  1078. default:
  1079. dprint("%s: unknown status %06#x\n", name, s);
  1080. /* fall through */
  1081. case Intactive: /* active, no device */
  1082. if(++d->wait&Mphywait)
  1083. break;
  1084. reset:
  1085. if(++d->mode > DMsataii)
  1086. d->mode = 0;
  1087. if(d->mode == DMsatai){ /* we tried everything */
  1088. d->state = Dportreset;
  1089. goto portreset;
  1090. }
  1091. dprint("%s: reset; new mode %s\n", name,
  1092. modename[d->mode]);
  1093. iunlock(&d->Lock);
  1094. resetdisk(d);
  1095. ilock(&d->Lock);
  1096. break;
  1097. case Intactive|Devphycomm|Devpresent:
  1098. if((++d->wait&Midwait) == 0){
  1099. dprint("%s: slow reset %06#x task=%#lx; %d\n",
  1100. name, s, d->port->task, d->wait);
  1101. goto reset;
  1102. }
  1103. s = (unsigned char)d->port->task;
  1104. if(s == 0x7f || ((d->port->sig >> 16) != 0xeb14 &&
  1105. (s & ~0x17) != (1<<6)))
  1106. break;
  1107. iunlock(&d->Lock);
  1108. newdrive(d);
  1109. ilock(&d->Lock);
  1110. break;
  1111. }
  1112. break;
  1113. case Doffline:
  1114. if(d->wait++ & Mcomrwait)
  1115. break;
  1116. /* fallthrough */
  1117. case Derror:
  1118. case Dreset:
  1119. dprint("%s: reset [%s]: mode %d; status %06#x\n",
  1120. name, diskstates[d->state], d->mode, s);
  1121. iunlock(&d->Lock);
  1122. resetdisk(d);
  1123. ilock(&d->Lock);
  1124. break;
  1125. case Dportreset:
  1126. portreset:
  1127. if(d->wait++ & 0xff && (s & Intactive) == 0)
  1128. break;
  1129. /* device is active */
  1130. dprint("%s: portreset [%s]: mode %d; status %06#x\n",
  1131. name, diskstates[d->state], d->mode, s);
  1132. d->portm.flag |= Ferror;
  1133. clearci(d->port);
  1134. wakeup(&d->portm.Rendez);
  1135. if((s & Devdet) == 0){ /* no device */
  1136. d->state = Dmissing;
  1137. break;
  1138. }
  1139. iunlock(&d->Lock);
  1140. doportreset(d);
  1141. ilock(&d->Lock);
  1142. break;
  1143. }
  1144. statechange(d);
  1145. iunlock(&d->Lock);
  1146. }
  1147. static void
  1148. satakproc(void *v)
  1149. {
  1150. Proc *up = externup();
  1151. int i;
  1152. for(;;){
  1153. tsleep(&up->sleep, return0, 0, Nms);
  1154. for(i = 0; i < niadrive; i++)
  1155. if(iadrive[i] != nil)
  1156. checkdrive(iadrive[i], i);
  1157. }
  1158. }
  1159. static void
  1160. isctlrjabbering(Ctlr *c, uint32_t cause)
  1161. {
  1162. uint32_t now;
  1163. now = TK2MS(sys->ticks);
  1164. if (now > c->lastintr0) {
  1165. c->intrs = 0;
  1166. c->lastintr0 = now;
  1167. }
  1168. if (++c->intrs > Maxintrspertick) {
  1169. iprint("sdiahci: %lu intrs per tick for no serviced "
  1170. "drive; cause %#lx mport %d\n",
  1171. c->intrs, cause, c->mport);
  1172. c->intrs = 0;
  1173. }
  1174. }
  1175. static void
  1176. isdrivejabbering(Drive *d)
  1177. {
  1178. uint32_t now;
  1179. now = TK2MS(sys->ticks);
  1180. if (now > d->lastintr0) {
  1181. d->intrs = 0;
  1182. d->lastintr0 = now;
  1183. }
  1184. if (++d->intrs > Maxintrspertick) {
  1185. iprint("sdiahci: %lu interrupts per tick for %s\n",
  1186. d->intrs, d->unit->SDperm.name);
  1187. d->intrs = 0;
  1188. }
  1189. }
  1190. static void
  1191. iainterrupt(Ureg *u, void *a)
  1192. {
  1193. int i;
  1194. uint32_t cause, mask;
  1195. Ctlr *c;
  1196. Drive *d;
  1197. c = a;
  1198. ilock(&c->Lock);
  1199. cause = c->hba->isr;
  1200. if (cause == 0) {
  1201. isctlrjabbering(c, cause);
  1202. // iprint("sdiahci: interrupt for no drive\n");
  1203. iunlock(&c->Lock);
  1204. return;
  1205. }
  1206. for(i = 0; cause && i <= c->mport; i++){
  1207. mask = 1 << i;
  1208. if((cause & mask) == 0)
  1209. continue;
  1210. d = c->rawdrive + i;
  1211. ilock(&d->Lock);
  1212. isdrivejabbering(d);
  1213. if(d->port->isr && c->hba->pi & mask)
  1214. updatedrive(d);
  1215. c->hba->isr = mask;
  1216. iunlock(&d->Lock);
  1217. cause &= ~mask;
  1218. }
  1219. if (cause) {
  1220. isctlrjabbering(c, cause);
  1221. iprint("sdiachi: intr cause unserviced: %#lx\n", cause);
  1222. }
  1223. iunlock(&c->Lock);
  1224. }
  1225. /* checkdrive, called from satakproc, will prod the drive while we wait */
  1226. static void
  1227. awaitspinup(Drive *d)
  1228. {
  1229. int ms;
  1230. uint16_t s;
  1231. char *name;
  1232. ilock(&d->Lock);
  1233. if(d->unit == nil || d->port == nil) {
  1234. panic("awaitspinup: nil d->unit or d->port");
  1235. iunlock(&d->Lock);
  1236. return;
  1237. }
  1238. name = (d->unit? d->unit->SDperm.name: nil);
  1239. s = d->port->sstatus;
  1240. if(!(s & Devpresent)) { /* never going to be ready */
  1241. dprint("awaitspinup: %s absent, not waiting\n", name);
  1242. iunlock(&d->Lock);
  1243. return;
  1244. }
  1245. for (ms = 20000; ms > 0; ms -= 50)
  1246. switch(d->state){
  1247. case Dnull:
  1248. /* absent; done */
  1249. iunlock(&d->Lock);
  1250. dprint("awaitspinup: %s in null state\n", name);
  1251. return;
  1252. case Dready:
  1253. case Dnew:
  1254. if(d->sectors || d->mediachange) {
  1255. /* ready to use; done */
  1256. iunlock(&d->Lock);
  1257. dprint("awaitspinup: %s ready!\n", name);
  1258. return;
  1259. }
  1260. /* fall through */
  1261. default:
  1262. case Dmissing: /* normal waiting states */
  1263. case Dreset:
  1264. case Doffline: /* transitional states */
  1265. case Derror:
  1266. case Dportreset:
  1267. iunlock(&d->Lock);
  1268. asleep(50);
  1269. ilock(&d->Lock);
  1270. break;
  1271. }
  1272. print("awaitspinup: %s didn't spin up after 20 seconds\n", name);
  1273. iunlock(&d->Lock);
  1274. }
  1275. static int
  1276. iaverify(SDunit *u)
  1277. {
  1278. Ctlr *c;
  1279. Drive *d;
  1280. c = u->dev->ctlr;
  1281. d = c->drive[u->subno];
  1282. ilock(&c->Lock);
  1283. ilock(&d->Lock);
  1284. d->unit = u;
  1285. iunlock(&d->Lock);
  1286. iunlock(&c->Lock);
  1287. checkdrive(d, d->driveno); /* c->d0 + d->driveno */
  1288. /*
  1289. * hang around until disks are spun up and thus available as
  1290. * nvram, dos file systems, etc. you wouldn't expect it, but
  1291. * the intel 330 ssd takes a while to `spin up'.
  1292. */
  1293. awaitspinup(d);
  1294. return 1;
  1295. }
  1296. static int
  1297. iaenable(SDev *s)
  1298. {
  1299. char name[32];
  1300. Ctlr *c;
  1301. static int once;
  1302. c = s->ctlr;
  1303. ilock(&c->Lock);
  1304. if(!c->enabled) {
  1305. if(once == 0) {
  1306. once = 1;
  1307. kproc("ahci", satakproc, 0);
  1308. }
  1309. if(c->ndrive == 0)
  1310. panic("iaenable: zero s->ctlr->ndrive");
  1311. pcisetbme(c->pci);
  1312. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1313. c->vector = intrenable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1314. /* supposed to squelch leftover interrupts here. */
  1315. ahcienable(c->hba);
  1316. c->enabled = 1;
  1317. }
  1318. iunlock(&c->Lock);
  1319. return 1;
  1320. }
  1321. static int
  1322. iadisable(SDev *s)
  1323. {
  1324. char name[32];
  1325. Ctlr *c;
  1326. c = s->ctlr;
  1327. ilock(&c->Lock);
  1328. ahcidisable(c->hba);
  1329. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1330. intrdisable(c->vector);
  1331. c->enabled = 0;
  1332. iunlock(&c->Lock);
  1333. return 1;
  1334. }
  1335. static int
  1336. iaonline(SDunit *unit)
  1337. {
  1338. int r;
  1339. Ctlr *c;
  1340. Drive *d;
  1341. c = unit->dev->ctlr;
  1342. d = c->drive[unit->subno];
  1343. r = 0;
  1344. if(d->portm.feat & Datapi && d->mediachange){
  1345. r = scsionline(unit);
  1346. if(r > 0)
  1347. d->mediachange = 0;
  1348. return r;
  1349. }
  1350. ilock(&d->Lock);
  1351. if(d->mediachange){
  1352. r = 2;
  1353. d->mediachange = 0;
  1354. /* devsd resets this after online is called; why? */
  1355. unit->sectors = d->sectors;
  1356. unit->secsize = 512; /* default size */
  1357. } else if(d->state == Dready)
  1358. r = 1;
  1359. iunlock(&d->Lock);
  1360. return r;
  1361. }
  1362. /* returns locked list! */
  1363. static Alist*
  1364. ahcibuild(Drive *d, unsigned char *cmd, void *data, int n, int64_t lba)
  1365. {
  1366. unsigned char *c, acmd, dir, llba;
  1367. Alist *l;
  1368. Actab *t;
  1369. Aportm *pm;
  1370. Aprdt *p;
  1371. static unsigned char tab[2][2] = { {0xc8, 0x25}, {0xca, 0x35}, };
  1372. pm = &d->portm;
  1373. dir = *cmd != 0x28;
  1374. llba = pm->feat&Dllba? 1: 0;
  1375. acmd = tab[dir][llba];
  1376. qlock(&pm->ql);
  1377. l = pm->list;
  1378. t = pm->ctab;
  1379. c = t->cfis;
  1380. c[0] = 0x27;
  1381. c[1] = 0x80;
  1382. c[2] = acmd;
  1383. c[3] = 0;
  1384. c[4] = lba; /* sector lba low 7:0 */
  1385. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1386. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1387. c[7] = Obs | 0x40; /* 0x40 == lba */
  1388. if(llba == 0)
  1389. c[7] |= (lba>>24) & 7;
  1390. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1391. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1392. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1393. c[11] = 0; /* features (exp); */
  1394. c[12] = n; /* sector count */
  1395. c[13] = n >> 8; /* sector count (exp) */
  1396. c[14] = 0; /* r */
  1397. c[15] = 0; /* control */
  1398. *(uint32_t*)(c + 16) = 0;
  1399. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1400. if(dir == Write)
  1401. l->flags |= Lwrite;
  1402. l->len = 0;
  1403. l->ctab = PCIWADDR(t);
  1404. l->ctabhi = PCIWADDR(t)>>32;
  1405. p = &t->prdt;
  1406. p->dba = PCIWADDR(data);
  1407. p->dbahi = PCIWADDR(data)>>32;
  1408. if(d->unit == nil)
  1409. panic("ahcibuild: nil d->unit");
  1410. p->count = 1<<31 | (d->unit->secsize*n - 2) | 1;
  1411. return l;
  1412. }
  1413. static Alist*
  1414. ahcibuildpkt(Aportm *pm, SDreq *r, void *data, int n)
  1415. {
  1416. int fill, len;
  1417. unsigned char *c;
  1418. Alist *l;
  1419. Actab *t;
  1420. Aprdt *p;
  1421. qlock(&pm->ql);
  1422. l = pm->list;
  1423. t = pm->ctab;
  1424. c = t->cfis;
  1425. fill = pm->feat&Datapi16? 16: 12;
  1426. if((len = r->clen) > fill)
  1427. len = fill;
  1428. memmove(t->atapi, r->cmd, len);
  1429. memset(t->atapi+len, 0, fill-len);
  1430. c[0] = 0x27;
  1431. c[1] = 0x80;
  1432. c[2] = 0xa0;
  1433. if(n != 0)
  1434. c[3] = 1; /* dma */
  1435. else
  1436. c[3] = 0; /* features (exp); */
  1437. c[4] = 0; /* sector lba low 7:0 */
  1438. c[5] = n; /* cylinder low lba mid 15:8 */
  1439. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1440. c[7] = Obs;
  1441. *(uint32_t*)(c + 8) = 0;
  1442. *(uint32_t*)(c + 12) = 0;
  1443. *(uint32_t*)(c + 16) = 0;
  1444. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1445. if(r->write != 0 && data)
  1446. l->flags |= Lwrite;
  1447. l->len = 0;
  1448. l->ctab = PCIWADDR(t);
  1449. l->ctabhi = PCIWADDR(t)>>32;
  1450. if(data == 0)
  1451. return l;
  1452. p = &t->prdt;
  1453. p->dba = PCIWADDR(data);
  1454. p->dbahi = PCIWADDR(data)>>32;
  1455. p->count = 1<<31 | (n - 2) | 1;
  1456. return l;
  1457. }
  1458. static int
  1459. waitready(Drive *d)
  1460. {
  1461. uint32_t s, i, delta;
  1462. for(i = 0; i < 15000; i += 250){
  1463. if(d->state == Dreset || d->state == Dportreset ||
  1464. d->state == Dnew)
  1465. return 1;
  1466. delta = sys->ticks - d->lastseen;
  1467. if(d->state == Dnull || delta > 10*1000)
  1468. return -1;
  1469. ilock(&d->Lock);
  1470. s = d->port->sstatus;
  1471. iunlock(&d->Lock);
  1472. if((s & Intpm) == 0 && delta > 1500)
  1473. return -1; /* no detect */
  1474. if(d->state == Dready &&
  1475. (s & Devdet) == (Devphycomm|Devpresent))
  1476. return 0; /* ready, present & phy. comm. */
  1477. esleep(250);
  1478. }
  1479. print("%s: not responding; offline\n", d->unit->SDperm.name);
  1480. setstate(d, Doffline);
  1481. return -1;
  1482. }
  1483. static int
  1484. lockready(Drive *d)
  1485. {
  1486. int i;
  1487. qlock(&d->portm.ql);
  1488. while ((i = waitready(d)) == 1) { /* could wait forever? */
  1489. qunlock(&d->portm.ql);
  1490. esleep(1);
  1491. qlock(&d->portm.ql);
  1492. }
  1493. return i;
  1494. }
  1495. static int
  1496. flushcache(Drive *d)
  1497. {
  1498. int i;
  1499. i = -1;
  1500. if(lockready(d) == 0)
  1501. i = ahciflushcache(&d->portc);
  1502. qunlock(&d->portm.ql);
  1503. return i;
  1504. }
  1505. static int
  1506. iariopkt(SDreq *r, Drive *d)
  1507. {
  1508. Proc *up = externup();
  1509. int n, count, try, max, flag, task, wormwrite;
  1510. char *name;
  1511. unsigned char *cmd, *data;
  1512. Aport *p;
  1513. Asleep as;
  1514. cmd = r->cmd;
  1515. name = d->unit->SDperm.name;
  1516. p = d->port;
  1517. aprint("ahci: iariopkt: %04#x %04#x %c %d %p\n",
  1518. cmd[0], cmd[2], "rw"[r->write], r->dlen, r->data);
  1519. if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1520. return sdmodesense(r, cmd, d->info, d->infosz);
  1521. r->rlen = 0;
  1522. count = r->dlen;
  1523. max = 65536;
  1524. try = 0;
  1525. retry:
  1526. data = r->data;
  1527. n = count;
  1528. if(n > max)
  1529. n = max;
  1530. ahcibuildpkt(&d->portm, r, data, n);
  1531. switch(waitready(d)){
  1532. case -1:
  1533. qunlock(&d->portm.ql);
  1534. return SDeio;
  1535. case 1:
  1536. qunlock(&d->portm.ql);
  1537. esleep(1);
  1538. goto retry;
  1539. }
  1540. /* d->portm qlock held here */
  1541. ilock(&d->Lock);
  1542. d->portm.flag = 0;
  1543. iunlock(&d->Lock);
  1544. p->ci = 1;
  1545. as.p = p;
  1546. as.i = 1;
  1547. d->intick = sys->ticks;
  1548. d->active++;
  1549. while(waserror())
  1550. ;
  1551. /* don't sleep here forever */
  1552. tsleep(&d->portm.Rendez, ahciclear, &as, 3*1000);
  1553. poperror();
  1554. if(!ahciclear(&as)) {
  1555. qunlock(&d->portm.ql);
  1556. print("%s: ahciclear not true after 3 seconds\n", name);
  1557. r->status = SDcheck;
  1558. return SDcheck;
  1559. }
  1560. d->active--;
  1561. ilock(&d->Lock);
  1562. flag = d->portm.flag;
  1563. task = d->port->task;
  1564. iunlock(&d->Lock);
  1565. if((task & (Efatal<<8)) || ((task & (ASbsy|ASdrq)) && d->state == Dready)){
  1566. d->port->ci = 0;
  1567. ahcirecover(&d->portc);
  1568. task = d->port->task;
  1569. flag &= ~Fdone; /* either an error or do-over */
  1570. }
  1571. qunlock(&d->portm.ql);
  1572. if(flag == 0){
  1573. if(++try == 10){
  1574. print("%s: bad disk\n", name);
  1575. r->status = SDcheck;
  1576. return SDcheck;
  1577. }
  1578. /*
  1579. * write retries cannot succeed on write-once media,
  1580. * so just accept any failure.
  1581. */
  1582. wormwrite = 0;
  1583. switch(d->unit->inquiry[0] & SDinq0periphtype){
  1584. case SDperworm:
  1585. case SDpercd:
  1586. switch(cmd[0]){
  1587. case 0x0a: /* write (6?) */
  1588. case 0x2a: /* write (10) */
  1589. case 0x8a: /* int32_t write (16) */
  1590. case 0x2e: /* write and verify (10) */
  1591. wormwrite = 1;
  1592. break;
  1593. }
  1594. break;
  1595. }
  1596. if (!wormwrite) {
  1597. print("%s: retry\n", name);
  1598. goto retry;
  1599. }
  1600. }
  1601. if(flag & Ferror){
  1602. if((task&Eidnf) == 0)
  1603. print("%s: i/o error task=%#x\n", name, task);
  1604. r->status = SDcheck;
  1605. return SDcheck;
  1606. }
  1607. data += n;
  1608. r->rlen = data - (unsigned char*)r->data;
  1609. r->status = SDok;
  1610. return SDok;
  1611. }
  1612. static int
  1613. iario(SDreq *r)
  1614. {
  1615. Proc *up = externup();
  1616. int i, n, count, try, max, flag, task;
  1617. int64_t lba;
  1618. char *name;
  1619. unsigned char *cmd, *data;
  1620. Aport *p;
  1621. Asleep as;
  1622. Ctlr *c;
  1623. Drive *d;
  1624. SDunit *unit;
  1625. unit = r->unit;
  1626. c = unit->dev->ctlr;
  1627. d = c->drive[unit->subno];
  1628. if(d->portm.feat & Datapi)
  1629. return iariopkt(r, d);
  1630. cmd = r->cmd;
  1631. name = d->unit->SDperm.name;
  1632. p = d->port;
  1633. if(r->cmd[0] == 0x35 || r->cmd[0] == 0x91){
  1634. if(flushcache(d) == 0)
  1635. return sdsetsense(r, SDok, 0, 0, 0);
  1636. return sdsetsense(r, SDcheck, 3, 0xc, 2);
  1637. }
  1638. if((i = sdfakescsi(r, d->info, d->infosz)) != SDnostatus){
  1639. r->status = i;
  1640. return i;
  1641. }
  1642. if(*cmd != 0x28 && *cmd != 0x2a){
  1643. print("%s: bad cmd %.2#x\n", name, cmd[0]);
  1644. r->status = SDcheck;
  1645. return SDcheck;
  1646. }
  1647. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1648. count = cmd[7]<<8 | cmd[8];
  1649. if(r->data == nil)
  1650. return SDok;
  1651. if(r->dlen < count * unit->secsize)
  1652. count = r->dlen / unit->secsize;
  1653. max = 128;
  1654. try = 0;
  1655. retry:
  1656. data = r->data;
  1657. while(count > 0){
  1658. n = count;
  1659. if(n > max)
  1660. n = max;
  1661. ahcibuild(d, cmd, data, n, lba);
  1662. switch(waitready(d)){
  1663. case -1:
  1664. qunlock(&d->portm.ql);
  1665. return SDeio;
  1666. case 1:
  1667. qunlock(&d->portm.ql);
  1668. esleep(1);
  1669. goto retry;
  1670. }
  1671. /* d->portm qlock held here */
  1672. ilock(&d->Lock);
  1673. d->portm.flag = 0;
  1674. iunlock(&d->Lock);
  1675. p->ci = 1;
  1676. as.p = p;
  1677. as.i = 1;
  1678. d->intick = sys->ticks;
  1679. d->active++;
  1680. while(waserror())
  1681. ;
  1682. /* don't sleep here forever */
  1683. tsleep(&d->portm.Rendez, ahciclear, &as, 3*1000);
  1684. poperror();
  1685. if(!ahciclear(&as)) {
  1686. qunlock(&d->portm.ql);
  1687. print("%s: ahciclear not true after 3 seconds\n", name);
  1688. r->status = SDcheck;
  1689. return SDcheck;
  1690. }
  1691. d->active--;
  1692. ilock(&d->Lock);
  1693. flag = d->portm.flag;
  1694. task = d->port->task;
  1695. iunlock(&d->Lock);
  1696. if((task & (Efatal<<8)) ||
  1697. ((task & (ASbsy|ASdrq)) && d->state == Dready)){
  1698. d->port->ci = 0;
  1699. ahcirecover(&d->portc);
  1700. task = d->port->task;
  1701. }
  1702. qunlock(&d->portm.ql);
  1703. if(flag == 0){
  1704. if(++try == 10){
  1705. print("%s: bad disk\n", name);
  1706. r->status = SDeio;
  1707. return SDeio;
  1708. }
  1709. print("%s: retry blk %lld\n", name, lba);
  1710. goto retry;
  1711. }
  1712. if(flag & Ferror){
  1713. print("%s: i/o error task=%#x @%,lld\n",
  1714. name, task, lba);
  1715. r->status = SDeio;
  1716. return SDeio;
  1717. }
  1718. count -= n;
  1719. lba += n;
  1720. data += n * unit->secsize;
  1721. }
  1722. r->rlen = data - (unsigned char*)r->data;
  1723. r->status = SDok;
  1724. return SDok;
  1725. }
  1726. /*
  1727. * configure drives 0-5 as ahci sata (c.f. errata).
  1728. * what about 6 & 7, as claimed by marvell 0x9123?
  1729. */
  1730. static int
  1731. iaahcimode(Pcidev *p)
  1732. {
  1733. dprint("iaahcimode: %#x %#x %#x\n", pcicfgr8(p, 0x91), pcicfgr8(p, 92),
  1734. pcicfgr8(p, 93));
  1735. pcicfgw16(p, 0x92, pcicfgr16(p, 0x92) | 0x3f); /* ports 0-5 */
  1736. return 0;
  1737. }
  1738. static void
  1739. iasetupahci(Ctlr *c)
  1740. {
  1741. /* disable cmd block decoding. */
  1742. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1743. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1744. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1745. c->lmmio[0xc/4] = (1 << 6) - 1; /* 5 ports. (supposedly ro pi reg.) */
  1746. /* enable ahci mode and 6 ports; from ich9 datasheet */
  1747. pcicfgw16(c->pci, 0x90, 1<<6 | 1<<5);
  1748. }
  1749. static int
  1750. didtype(Pcidev *p)
  1751. {
  1752. switch(p->vid){
  1753. case Vintel:
  1754. if((p->did & 0xfffc) == 0x2680)
  1755. return Tesb;
  1756. /*
  1757. * 0x27c4 is the intel 82801 in compatibility (not sata) mode.
  1758. */
  1759. if (p->did == 0x1e02 || /* c210 */
  1760. p->did == 0x24d1 || /* 82801eb/er */
  1761. (p->did & 0xfffb) == 0x27c1 || /* 82801g[bh]m ich7 */
  1762. p->did == 0x2821 || /* 82801h[roh] */
  1763. (p->did & 0xfffe) == 0x2824 || /* 82801h[b] */
  1764. (p->did & 0xfeff) == 0x2829 || /* ich8/9m */
  1765. (p->did & 0xfffe) == 0x2922 || /* ich9 */
  1766. p->did == 0x3a02 || /* 82801jd/do */
  1767. (p->did & 0xfefe) == 0x3a22 || /* ich10, pch */
  1768. (p->did & 0xfff8) == 0x3b28) /* pchm */
  1769. return Tich;
  1770. break;
  1771. case Vatiamd:
  1772. if(p->did == 0x4380 || p->did == 0x4390 || p->did == 0x4391){
  1773. print("detected sb600 vid %#x did %#x\n", p->vid, p->did);
  1774. return Tsb600;
  1775. }
  1776. break;
  1777. case Vmarvell:
  1778. if (p->did == 0x9123)
  1779. print("ahci: marvell sata 3 controller has delusions "
  1780. "of something on unit 7\n");
  1781. break;
  1782. }
  1783. if(p->ccrb == Pcibcstore && p->ccru == Pciscsata && p->ccrp == 1){
  1784. print("ahci: Tunk: vid %#4.4x did %#4.4x\n", p->vid, p->did);
  1785. return Tunk;
  1786. }
  1787. return -1;
  1788. }
  1789. static int
  1790. newctlr(Ctlr *ctlr, SDev *sdev, int nunit)
  1791. {
  1792. int i, n;
  1793. Drive *drive;
  1794. ctlr->ndrive = sdev->nunit = nunit;
  1795. ctlr->mport = ctlr->hba->cap & ((1<<5)-1);
  1796. i = (ctlr->hba->cap >> 20) & ((1<<4)-1); /* iss */
  1797. print("#S/sd%c: %s: %#p %s, %d ports, irq %d\n", sdev->idno,
  1798. Tname(ctlr), ctlr->physio, descmode[i], nunit, ctlr->pci->intl);
  1799. /* map the drives -- they don't all need to be enabled. */
  1800. n = 0;
  1801. ctlr->rawdrive = malloc(NCtlrdrv * sizeof(Drive));
  1802. if(ctlr->rawdrive == nil) {
  1803. print("ahci: out of memory\n");
  1804. return -1;
  1805. }
  1806. for(i = 0; i < NCtlrdrv; i++) {
  1807. drive = ctlr->rawdrive + i;
  1808. drive->portno = i;
  1809. drive->driveno = -1;
  1810. drive->sectors = 0;
  1811. drive->serial[0] = ' ';
  1812. drive->ctlr = ctlr;
  1813. if((ctlr->hba->pi & (1<<i)) == 0)
  1814. continue;
  1815. drive->port = (Aport*)(ctlr->mmio + 0x80*i + 0x100);
  1816. drive->portc.p = drive->port;
  1817. drive->portc.pm = &drive->portm;
  1818. drive->driveno = n++;
  1819. ctlr->drive[drive->driveno] = drive;
  1820. iadrive[niadrive + drive->driveno] = drive;
  1821. }
  1822. for(i = 0; i < n; i++)
  1823. if(ahciidle(ctlr->drive[i]->port) == -1){
  1824. dprint("ahci: %s: port %d wedged; abort\n",
  1825. Tname(ctlr), i);
  1826. return -1;
  1827. }
  1828. for(i = 0; i < n; i++){
  1829. ctlr->drive[i]->mode = DMsatai;
  1830. configdrive(ctlr->drive[i]);
  1831. }
  1832. return n;
  1833. }
  1834. static SDev*
  1835. iapnp(void)
  1836. {
  1837. int n, nunit, type;
  1838. uintptr_t io;
  1839. Ctlr *c;
  1840. Pcidev *p;
  1841. SDev *head, *tail, *s;
  1842. static int done;
  1843. if(done++)
  1844. return nil;
  1845. memset(olds, 0xff, sizeof olds);
  1846. p = nil;
  1847. head = tail = nil;
  1848. while((p = pcimatch(p, 0, 0)) != nil){
  1849. type = didtype(p);
  1850. if (type == -1 || p->mem[Abar].bar == 0)
  1851. continue;
  1852. if(niactlr == NCtlr){
  1853. print("ahci: iapnp: %s: too many controllers\n",
  1854. tname[type]);
  1855. break;
  1856. }
  1857. c = iactlr + niactlr;
  1858. s = sdevs + niactlr;
  1859. memset(c, 0, sizeof *c);
  1860. memset(s, 0, sizeof *s);
  1861. io = p->mem[Abar].bar & ~0xf;
  1862. c->physio = (unsigned char *)io;
  1863. c->mmio = vmap(io, p->mem[Abar].size);
  1864. if(c->mmio == 0){
  1865. print("ahci: %s: address %#lX in use did=%#x\n",
  1866. Tname(c), io, p->did);
  1867. continue;
  1868. }
  1869. c->lmmio = (uint32_t*)c->mmio;
  1870. c->pci = p;
  1871. c->type = type;
  1872. s->ifc = &sdiahciifc;
  1873. s->idno = 'E' + niactlr;
  1874. s->ctlr = c;
  1875. c->sdev = s;
  1876. if(Intel(c) && p->did != 0x2681)
  1877. iasetupahci(c);
  1878. nunit = ahciconf(c);
  1879. // ahcihbareset((Ahba*)c->mmio);
  1880. if(Intel(c) && iaahcimode(p) == -1)
  1881. break;
  1882. if(nunit < 1){
  1883. vunmap(c->mmio, p->mem[Abar].size);
  1884. continue;
  1885. }
  1886. n = newctlr(c, s, nunit);
  1887. if(n < 0)
  1888. continue;
  1889. niadrive += n;
  1890. niactlr++;
  1891. if(head)
  1892. tail->next = s;
  1893. else
  1894. head = s;
  1895. tail = s;
  1896. }
  1897. return head;
  1898. }
  1899. static char* smarttab[] = {
  1900. "unset",
  1901. "error",
  1902. "threshold exceeded",
  1903. "normal"
  1904. };
  1905. static char *
  1906. pflag(char *s, char *e, unsigned char f)
  1907. {
  1908. unsigned char i;
  1909. for(i = 0; i < 8; i++)
  1910. if(f & (1 << i))
  1911. s = seprint(s, e, "%s ", flagname[i]);
  1912. return seprint(s, e, "\n");
  1913. }
  1914. static int
  1915. iarctl(SDunit *u, char *p, int l)
  1916. {
  1917. char buf[32];
  1918. char *e, *op;
  1919. Aport *o;
  1920. Ctlr *c;
  1921. Drive *d;
  1922. c = u->dev->ctlr;
  1923. if(c == nil) {
  1924. print("iarctl: nil u->dev->ctlr\n");
  1925. return 0;
  1926. }
  1927. d = c->drive[u->subno];
  1928. o = d->port;
  1929. e = p+l;
  1930. op = p;
  1931. if(d->state == Dready){
  1932. p = seprint(p, e, "model\t%s\n", d->model);
  1933. p = seprint(p, e, "serial\t%s\n", d->serial);
  1934. p = seprint(p, e, "firm\t%s\n", d->firmware);
  1935. if(d->smartrs == 0xff)
  1936. p = seprint(p, e, "smart\tenable error\n");
  1937. else if(d->smartrs == 0)
  1938. p = seprint(p, e, "smart\tdisabled\n");
  1939. else
  1940. p = seprint(p, e, "smart\t%s\n",
  1941. smarttab[d->portm.smart]);
  1942. p = seprint(p, e, "flag\t");
  1943. p = pflag(p, e, d->portm.feat);
  1944. }else
  1945. p = seprint(p, e, "no disk present [%s]\n", diskstates[d->state]);
  1946. serrstr(o->serror, buf, buf + sizeof buf - 1);
  1947. p = seprint(p, e, "reg\ttask %#lx cmd %#lx serr %#lx %s ci %#lx "
  1948. "is %#lx; sig %#lx sstatus %06#lx\n",
  1949. o->task, o->cmd, o->serror, buf,
  1950. o->ci, o->isr, o->sig, o->sstatus);
  1951. if(d->unit == nil)
  1952. panic("iarctl: nil d->unit");
  1953. p = seprint(p, e, "geometry %llu %lu\n", d->sectors, d->unit->secsize);
  1954. return p - op;
  1955. }
  1956. static void
  1957. runflushcache(Drive *d)
  1958. {
  1959. int32_t t0;
  1960. t0 = sys->ticks;
  1961. if(flushcache(d) != 0)
  1962. error(Eio);
  1963. dprint("ahci: flush in %ld ms\n", sys->ticks - t0);
  1964. }
  1965. static void
  1966. forcemode(Drive *d, char *mode)
  1967. {
  1968. int i;
  1969. for(i = 0; i < nelem(modename); i++)
  1970. if(strcmp(mode, modename[i]) == 0)
  1971. break;
  1972. if(i == nelem(modename))
  1973. i = 0;
  1974. ilock(&d->Lock);
  1975. d->mode = i;
  1976. iunlock(&d->Lock);
  1977. }
  1978. static void
  1979. runsmartable(Drive *d, int i)
  1980. {
  1981. Proc *up = externup();
  1982. if(waserror()){
  1983. qunlock(&d->portm.ql);
  1984. d->smartrs = 0;
  1985. nexterror();
  1986. }
  1987. if(lockready(d) == -1)
  1988. error(Eio);
  1989. d->smartrs = smart(&d->portc, i);
  1990. d->portm.smart = 0;
  1991. qunlock(&d->portm.ql);
  1992. poperror();
  1993. }
  1994. static void
  1995. forcestate(Drive *d, char *state)
  1996. {
  1997. int i;
  1998. for(i = 0; i < nelem(diskstates); i++)
  1999. if(strcmp(state, diskstates[i]) == 0)
  2000. break;
  2001. if(i == nelem(diskstates))
  2002. error(Ebadctl);
  2003. setstate(d, i);
  2004. }
  2005. /*
  2006. * force this driver to notice a change of medium if the hardware doesn't
  2007. * report it.
  2008. */
  2009. static void
  2010. changemedia(SDunit *u)
  2011. {
  2012. Ctlr *c;
  2013. Drive *d;
  2014. c = u->dev->ctlr;
  2015. d = c->drive[u->subno];
  2016. ilock(&d->Lock);
  2017. d->mediachange = 1;
  2018. u->sectors = 0;
  2019. iunlock(&d->Lock);
  2020. }
  2021. static int
  2022. iawctl(SDunit *u, Cmdbuf *cmd)
  2023. {
  2024. Proc *up = externup();
  2025. char **f;
  2026. Ctlr *c;
  2027. Drive *d;
  2028. uint i;
  2029. c = u->dev->ctlr;
  2030. d = c->drive[u->subno];
  2031. f = cmd->f;
  2032. if(strcmp(f[0], "change") == 0)
  2033. changemedia(u);
  2034. else if(strcmp(f[0], "flushcache") == 0)
  2035. runflushcache(d);
  2036. else if(strcmp(f[0], "identify") == 0){
  2037. i = strtoul(f[1]? f[1]: "0", 0, 0);
  2038. if(i > 0xff)
  2039. i = 0;
  2040. dprint("ahci: %04d %#x\n", i, d->info[i]);
  2041. }else if(strcmp(f[0], "mode") == 0)
  2042. forcemode(d, f[1]? f[1]: "satai");
  2043. else if(strcmp(f[0], "nop") == 0){
  2044. if((d->portm.feat & Dnop) == 0){
  2045. cmderror(cmd, "no drive support");
  2046. return -1;
  2047. }
  2048. if(waserror()){
  2049. qunlock(&d->portm.ql);
  2050. nexterror();
  2051. }
  2052. if(lockready(d) == -1)
  2053. error(Eio);
  2054. nop(&d->portc);
  2055. qunlock(&d->portm.ql);
  2056. poperror();
  2057. }else if(strcmp(f[0], "reset") == 0)
  2058. forcestate(d, "reset");
  2059. else if(strcmp(f[0], "smart") == 0){
  2060. if(d->smartrs == 0){
  2061. cmderror(cmd, "smart not enabled");
  2062. return -1;
  2063. }
  2064. if(waserror()){
  2065. qunlock(&d->portm.ql);
  2066. d->smartrs = 0;
  2067. nexterror();
  2068. }
  2069. if(lockready(d) == -1)
  2070. error(Eio);
  2071. d->portm.smart = 2 + smartrs(&d->portc);
  2072. qunlock(&d->portm.ql);
  2073. poperror();
  2074. }else if(strcmp(f[0], "smartdisable") == 0)
  2075. runsmartable(d, 1);
  2076. else if(strcmp(f[0], "smartenable") == 0)
  2077. runsmartable(d, 0);
  2078. else if(strcmp(f[0], "state") == 0)
  2079. forcestate(d, f[1]? f[1]: "null");
  2080. else{
  2081. cmderror(cmd, Ebadctl);
  2082. return -1;
  2083. }
  2084. return 0;
  2085. }
  2086. static char *
  2087. portr(char *p, char *e, uint x)
  2088. {
  2089. int i, a;
  2090. p[0] = 0;
  2091. a = -1;
  2092. for(i = 0; i < 32; i++){
  2093. if((x & (1<<i)) == 0){
  2094. if(a != -1 && i - 1 != a)
  2095. p = seprint(p, e, "-%d", i - 1);
  2096. a = -1;
  2097. continue;
  2098. }
  2099. if(a == -1){
  2100. if(i > 0)
  2101. p = seprint(p, e, ", ");
  2102. p = seprint(p, e, "%d", a = i);
  2103. }
  2104. }
  2105. if(a != -1 && i - 1 != a)
  2106. p = seprint(p, e, "-%d", i - 1);
  2107. return p;
  2108. }
  2109. /* must emit exactly one line per controller (sd(3)) */
  2110. static char*
  2111. iartopctl(SDev *sdev, char *p, char *e)
  2112. {
  2113. uint32_t cap;
  2114. char pr[25];
  2115. Ahba *hba;
  2116. Ctlr *ctlr;
  2117. #define has(x, str) if(cap & (x)) p = seprint(p, e, "%s ", (str))
  2118. ctlr = sdev->ctlr;
  2119. hba = ctlr->hba;
  2120. p = seprint(p, e, "sd%c ahci port %#p: ", sdev->idno, ctlr->physio);
  2121. cap = hba->cap;
  2122. has(Hs64a, "64a");
  2123. has(Hsalp, "alp");
  2124. has(Hsam, "am");
  2125. has(Hsclo, "clo");
  2126. has(Hcccs, "coal");
  2127. has(Hems, "ems");
  2128. has(Hsal, "led");
  2129. has(Hsmps, "mps");
  2130. has(Hsncq, "ncq");
  2131. has(Hssntf, "ntf");
  2132. has(Hspm, "pm");
  2133. has(Hpsc, "pslum");
  2134. has(Hssc, "slum");
  2135. has(Hsss, "ss");
  2136. has(Hsxs, "sxs");
  2137. portr(pr, pr + sizeof pr, hba->pi);
  2138. return seprint(p, e,
  2139. "iss %ld ncs %ld np %ld; ghc %#lx isr %#lx pi %#lx %s ver %#lx\n",
  2140. (cap>>20) & 0xf, (cap>>8) & 0x1f, 1 + (cap & 0x1f),
  2141. hba->ghc, hba->isr, hba->pi, pr, hba->ver);
  2142. #undef has
  2143. }
  2144. static int
  2145. iawtopctl(SDev *sdev, Cmdbuf *cmd)
  2146. {
  2147. int *v;
  2148. char **f;
  2149. f = cmd->f;
  2150. v = 0;
  2151. if (f[0] == nil)
  2152. return 0;
  2153. if(strcmp(f[0], "debug") == 0)
  2154. v = &debug;
  2155. else if(strcmp(f[0], "idprint") == 0)
  2156. v = &prid;
  2157. else if(strcmp(f[0], "aprint") == 0)
  2158. v = &datapi;
  2159. else
  2160. cmderror(cmd, Ebadctl);
  2161. switch(cmd->nf){
  2162. default:
  2163. cmderror(cmd, Ebadarg);
  2164. case 1:
  2165. *v ^= 1;
  2166. break;
  2167. case 2:
  2168. if(f[1])
  2169. *v = strcmp(f[1], "on") == 0;
  2170. else
  2171. *v ^= 1;
  2172. break;
  2173. }
  2174. return 0;
  2175. }
  2176. SDifc sdiahciifc = {
  2177. "iahci",
  2178. iapnp,
  2179. nil, /* legacy */
  2180. iaenable,
  2181. iadisable,
  2182. iaverify,
  2183. iaonline,
  2184. iario,
  2185. iarctl,
  2186. iawctl,
  2187. scsibio,
  2188. nil, /* probe */
  2189. nil, /* clear */
  2190. iartopctl,
  2191. iawtopctl,
  2192. };