io.h 4.5 KB

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  1. enum {
  2. IrqCLOCK = 0,
  3. IrqKBD = 1,
  4. IrqUART1 = 3,
  5. IrqUART0 = 4,
  6. IrqPCMCIA = 5,
  7. IrqFLOPPY = 6,
  8. IrqLPT = 7,
  9. IrqIRQ7 = 7,
  10. IrqAUX = 12, /* PS/2 port */
  11. IrqIRQ13 = 13, /* coprocessor on 386 */
  12. IrqATA0 = 14,
  13. IrqATA1 = 15,
  14. MaxIrqPIC = 15,
  15. VectorPIC = 64,
  16. MaxVectorPIC = VectorPIC+MaxIrqPIC,
  17. VectorPCI = 16, /* PCI bus (PLD) */
  18. };
  19. typedef struct Vctl {
  20. Vctl* next; /* handlers on this vector */
  21. char name[KNAMELEN]; /* of driver */
  22. int isintr; /* interrupt or fault/trap */
  23. int irq;
  24. int tbdf;
  25. int (*isr)(int); /* get isr bit for this irq */
  26. int (*eoi)(int); /* eoi */
  27. void (*f)(Ureg*, void*); /* handler to call */
  28. void* a; /* argument to call it with */
  29. } Vctl;
  30. enum {
  31. BusCBUS = 0, /* Corollary CBUS */
  32. BusCBUSII, /* Corollary CBUS II */
  33. BusEISA, /* Extended ISA */
  34. BusFUTURE, /* IEEE Futurebus */
  35. BusINTERN, /* Internal bus */
  36. BusISA, /* Industry Standard Architecture */
  37. BusMBI, /* Multibus I */
  38. BusMBII, /* Multibus II */
  39. BusMCA, /* Micro Channel Architecture */
  40. BusMPI, /* MPI */
  41. BusMPSA, /* MPSA */
  42. BusNUBUS, /* Apple Macintosh NuBus */
  43. BusPCI, /* Peripheral Component Interconnect */
  44. BusPCMCIA, /* PC Memory Card International Association */
  45. BusTC, /* DEC TurboChannel */
  46. BusVL, /* VESA Local bus */
  47. BusVME, /* VMEbus */
  48. BusXPRESS, /* Express System Bus */
  49. };
  50. #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  51. #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
  52. #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
  53. #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
  54. #define BUSTYPE(tbdf) ((tbdf)>>24)
  55. #define BUSDF(tbdf) ((tbdf)&0x000FF00)
  56. #define BUSBDF(tbdf) ((tbdf)&0x0FFFF00)
  57. #define BUSUNKNOWN (-1)
  58. enum {
  59. MaxEISA = 16,
  60. EISAconfig = 0xC80,
  61. };
  62. /*
  63. * PCI support code.
  64. */
  65. enum { /* type 0 and type 1 pre-defined header */
  66. PciVID = 0x00, /* vendor ID */
  67. PciDID = 0x02, /* device ID */
  68. PciPCR = 0x04, /* command */
  69. PciPSR = 0x06, /* status */
  70. PciRID = 0x08, /* revision ID */
  71. PciCCRp = 0x09, /* programming interface class code */
  72. PciCCRu = 0x0A, /* sub-class code */
  73. PciCCRb = 0x0B, /* base class code */
  74. PciCLS = 0x0C, /* cache line size */
  75. PciLTR = 0x0D, /* latency timer */
  76. PciHDT = 0x0E, /* header type */
  77. PciBST = 0x0F, /* BIST */
  78. PciBAR0 = 0x10, /* base address */
  79. PciBAR1 = 0x14,
  80. PciROM = 0x30,
  81. PciINTL = 0x3C, /* interrupt line */
  82. PciINTP = 0x3D, /* interrupt pin */
  83. };
  84. enum { /* type 0 pre-defined header */
  85. PciCIS = 0x28, /* cardbus CIS pointer */
  86. PciSVID = 0x2C, /* subsystem vendor ID */
  87. PciSID = 0x2E, /* cardbus CIS pointer */
  88. PciEBAR0 = 0x30, /* xpansion ROM base address */
  89. PciMGNT = 0x3E, /* burst period length */
  90. PciMLT = 0x3F, /* maximum latency between bursts */
  91. };
  92. enum { /* type 1 pre-defined header */
  93. PciPBN = 0x18, /* primary bus number */
  94. PciSBN = 0x19, /* secondary bus number */
  95. PciUBN = 0x1A, /* subordinate bus number */
  96. PciSLTR = 0x1B, /* secondary latency timer */
  97. PciIBR = 0x1C, /* I/O base */
  98. PciILR = 0x1D, /* I/O limit */
  99. PciSPSR = 0x1E, /* secondary status */
  100. PciMBR = 0x20, /* memory base */
  101. PciMLR = 0x22, /* memory limit */
  102. PciPMBR = 0x24, /* prefetchable memory base */
  103. PciPMLR = 0x26, /* prefetchable memory limit */
  104. PciPUBR = 0x28, /* prefetchable base upper 32 bits */
  105. PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
  106. PciIUBR = 0x30, /* I/O base upper 16 bits */
  107. PciIULR = 0x32, /* I/O limit upper 16 bits */
  108. PciEBAR1 = 0x28, /* expansion ROM base address */
  109. PciBCR = 0x3E, /* bridge control register */
  110. };
  111. typedef struct Pcidev Pcidev;
  112. typedef struct Pcidev {
  113. int tbdf; /* type+bus+device+function */
  114. ushort vid; /* vendor ID */
  115. ushort did; /* device ID */
  116. ushort pcr;
  117. uchar rid;
  118. uchar ccrp;
  119. uchar ccru;
  120. uchar ccrb;
  121. uchar cls;
  122. uchar ltr;
  123. struct {
  124. ulong bar; /* base address */
  125. int size;
  126. } mem[6];
  127. uchar intl; /* interrupt line */
  128. Pcidev* list;
  129. Pcidev* link; /* next device on this bno */
  130. Pcidev* bridge; /* down a bus */
  131. struct {
  132. ulong bar;
  133. int size;
  134. } ioa, mema;
  135. int pmrb; /* power management register block */
  136. };
  137. #define PCIWINDOW 0x40000000
  138. #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
  139. #define ISAWINDOW 0x00800000
  140. #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
  141. /*
  142. * PCMCIA support code.
  143. */
  144. /*
  145. * Map between ISA memory space and PCMCIA card memory space.
  146. */
  147. struct PCMmap {
  148. ulong ca; /* card address */
  149. ulong cea; /* card end address */
  150. ulong isa; /* ISA address */
  151. int len; /* length of the ISA area */
  152. int attr; /* attribute memory */
  153. int ref;
  154. };